Design, Synthesis and Implementing Digital Finite

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National Conference on New Approaches in Electrical and Computer Engineering(NAECE2017) March.10th2017–Islamic Azad University Of Khorram Abad Branch

‫واﺣﺪ ﺧﺮم آﺑﺎد‬

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Design, Synthesis and Implementing Digital Finite Impulse Response Filter using High Level Modeling Tools FPGA Nader Ahmadzadeh khosroshah

Amir Amirabadi

Young Researchers and Elite Club, South Tehran Branch, Islamic Azad University, Tehran, Iran [email protected]

Department of Electrical Engineering, College of Engineering, South Tehran Branch, Islamic Azad university, Tehran Iran [email protected]

FIR filters use some internal components implemented on FPGA. So we have used the distributed it.

Abstract- The paper introduces structure characteristics and the principles of the finite impulse response (FIR) digital filter, and gives an efficient filter design based on Xilinx FPGA. Use MATLAB 2015b, FDATool to determine filter coefficients, and designed a 9-order constant coefficient FIR filter by VHDL language, take use of Active HDL 8.3 to compile filters, Modelsim 10 and ISE 14.7 Xilinx Virtex7 Dsp Tool obtain the results meet performance requirements. Aiming at the requirements of real time signal processing, a cut-off frequency of 12 MHz, Fs= 50 MHz 9-order direct form FIR linear-phase, low-pass filter using Window Kaiser 0.5 and Gaussian 0.5 use Fdatool function and designed out based on DSP Builder system.

II.

TRANSVERSAL STRUCTURE OF FIR FILTER

The system function of FIR filter can be written as H (Z) =∑ h (n)z-n for n=0 to N-1. H (Z) =h(0) + h(1) z-1 + h(2)z-2 ….+h(N-1)z-(N-1)

(1) (2)

And Y(Z)=h(0)X(Z)+h(1)z-1X(Z)+h(2)z-2X(Z)+….h(N-1)z-(n-1) X(Z) (3)

Keywords: Fir Filter- Low pass Filter- FPGA Xilinx –mat lab –

This equation is realized transversal structure. This structure requires N multipliers, N-1 adders, and N-1 delay elements. Figure.1 and Figure2.

Active HDl – Design- Synthesis – Implement – 9 orders

I.

INTRODUCTION

As the word indicates, a filter separates a desired signal from unwanted disturbances. The first useful filter is a linear filter because we have a good understanding of how a linear system operates. It is only when a design fails; we look for other solutions, such as nonlinear or, adaptive techniques. In the electronic industry, device known as Digital filters are taking digital input, process, and provide digital output. These filters are used in abundance in many consumer level products especially those related with image processing and video communication [1]. FIR filters may follow more than one stage. To implement High Speed Digital Signal Processor (DSP) systems, on FPGA used as hardware platform. The advantages of FPGA is of project cost, flexibility, reconfigures ability and reliability [2]. However, the FPGA platform provides high performance and flexibility with the option to reconfigure. In wireless communication system [3].

Figure1. Direct Form FIR Structure

Figure2. Modified Direct Form FIR Structure

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III.

FIR FILTER DESIGN STEPS

Filter specification may include stating the type of filter ex. Low pass filter, Amplitude or phase responses and …, the sampling frequency and the word length to input data. We determine the coefficients of the transfer function H(z) by Matlab FDATOOL then using export coefficient to generate HDL code to use in Active HDL8.3 and realizae involves the converting the transfer into a suitable filter network or structure. Analysis of finite word length of quantizing the filter coefficients and the input data cause to filtering operation using fixed word lengths on the filter performance. finaly Implement the production of the software code and/ or hardware and performing the actual filtering. IV.

DESIGN FILTER COEFF IN FDATOOL MATLAB

FDA tool’ [8] is the basic tool of MATLAB used to design a filter. There are different response types of filter design in it, and Design Methods (IIR, FIR) to implement the filter. These windows can be customized by providing order of the filter, cut-off, sampling, pass-band and stop-band frequencies and magnitude specifications. Through the specifications provided, the tool creates coefficients that are saved as matrix in MATLAB workspace show in figure (3-12).

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Figure13. Chart of design

Figure (3-12). Mat lab FDATOOL result

V.

GENERATING THE HDL CODE Figure14. Delay Pipeline process & Output Register Precess

Now we use VHDL code to using in Xilinx ISE 14.7 cosimulation with ModelSim 10 and Altara active HDL design 8.3 as show the result in figures(13-23 ).

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Figure15.Simulation and Synthesis Vertex7

Figure19. Mapping of Filter Figure16.Simulation and Synthesis

Figure17. RTL Schematic of filter

Figure18. Layout Schematic

Figure20. Package of Design

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Figure21. RTL Block of filter

Figure23. Modalism simulation

VI.

IMPLIMENTATION OF FIR FILTER

Different models of Implementation use and test as shown in figures (24-28).

Figure24. Implementation use Fir compiler 6.3

Figure25. mixed-mode Modalism simulation

Figure22. FIR Compiler design 6.3 Figure26. MAC Based FIR block and then design

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Figure27. FIR Filter using system generator

Figure28. Comparison of input and output signal on spectrum scope

VII.

Figure29. Input and output of filter compiler

OTHER FILTER SOFTWARE DESIGN

Finally, we design this Filter with other Filter Designing software to compare between them for further work. Figure (29-33). VIII.

RESULT AND CONCLUSION

Use MATLAB 2015b, FDATool to determine filter coefficients, and designed a 9-order constant coefficient FIR filter by VHDL language, take use of Active HDL 8.3 to compile filters, Modelsim 10 and ISE 14.7 Xilinx Virtex7 Dsp Tool obtain the results meet performance requirements. Aiming at the requirements of real time signal processing, a cut-off frequency of 12 MHz, Fs= 50 MHz 9-order direct form FIR linear-phase, low-pass filter using Window Kaiser 0.5 and Gaussian 0.5 use Fdatool function and designed out based on DSP Builder system.

Figure30. Iowa Hills FIR Filter Designer

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[3] Meyer-Baese Digital signal processing with field programmable gate arrays, 2nd edn. Springer, Berlin/New York U (2006) [4] Ljiljana Milic, Tapio Saramaki and Robert Bregovic, “Multirate Filters: An Overview”, IEEE Journal, 1-4244- 0387, 2006 [5] Zhang Haijun, "Design and implementation of 16 order FIR filter based on FPGA," Journal of Anhui University Natural Science Edition, Vol. 33, Jan. 2009, pp. 62-65 [6] Suraj R. Gaikwad and Gopal S. Gawande, “Design and Implementation of Efficient FIR Filter Structures using Xilinx System Generator”, International Journal of scientific research and management, volume2 issue 3 March 2014 [7] Harish V. Dixit , Dr. Vikas Gupta, International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622,Vol. 2, Issue 5, September- October 2012,pp.303-307 [8] U. Nithirochananont, S. Chivapreecha and K. Dejhan, “An FPGA based implementation of variable fractional delay filter,” in Proc. IEEE Int. Colloq. on Signal Processing and its Applications, 2009, pp. 104–107

Figure31. Spectrum of Iowa Hills FIR Filter Designer

Figure32 Win Filter Designer Schematic

Figure33 FIR Designer 12.1

IX.


REFRENCES

[1] Efficient FPGA and ASIC Realizations of DA-Based Reconfigurable FIR Digital Filterǁ IEEE transactions 2014 on circuits and system. [2] P. K. Meher and S. Y. Park, ―High-throughput pipelined realization of adaptive FIR filter based on distributed arithmetic,ǁ in Proc. 2011 IEEE/IFIP 19th Int. Conf. VLSI, System-on-Chip, (VLSI-SOC’11), Oct. 2011, pp. 428

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