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Charging Effects on Reliability of HfOz Devices with Polysilicon Gate Electrode. Katsunori Onishi, Chang Seok Kang, Rino Choi, Hag-Ju Cho, Sundar Gopalan,.

Charging Effects on Reliability of HfOz Devices with Polysilicon Gate Electrode Katsunori Onishi, Chang Seok Kang, Rino Choi, Hag-Ju Cho, Sundar Gopalan, Renee Nieh, Siddharth Krishnan, and Jack C. Lee Microelectronics Research Center, The University of Texas at Austin, Austin, Texas 78758, USA Tel: (512) 471-1627, Fax: (512) 471-5625, e-mail: [email protected]

Abstract Time dependent dielectric breakdown and bias temperature instability of Hf02 devices with polysilicon gate electrode have been studied. Both N and PMOS capacitors have sufficient TDDB lifetime, whereas PMOS capacitors show gradual increase in the leakage current during stress. Hf02 PMOSFET’s without nitridation have sufficient immunity against negative bias temperature instability. Bias temperature instability for NMOS can be a potential scaling limit for Hf02. Introduction Through extensive research in recent years, some high-k gate dielectrics, such as Hf02 and ZrO;?, have shown promising electrical characteristics for the CMOS device application. Hf02, in particular, is one of the most promising candidates, due to its high dielectric constant, a large bandgap, and thermal stability in contact with silicon. Hf02 can be readily introduced to the existing self-align CMOS process, since polysilicon gate MOSFET’s have already been reported [l]. On the other hand, reliability of high-k dielectrics has not been hlly explored except some of TDDB data [1, 21 or instability of PMOSFET characteristics [3]. In this paper, dielectric breakdown and transistor instability due to gate voltage stressing have been studied on both N and PMOS devices with H a 2 gate dielectric. Experiments Hf02 was deposited using reactive dc magnetron sputtering with O2 modulation technique [l], followed by post-deposition annealing (PDA) typically at 500°C. Surface nitridation technique (SN) has been applied for some samples prior to HfO2 deposition [4]. Detailed description about MOSFET fabrication can be found in [3]. TDDB was tested on various sizes of MOS capacitors using constant voltage stress (CVS) in accumulation conditions. Dielectric breakdown was detected at 50 YO increase of the leakage current between measurements. Long channel MOSFET’s (L 2 5 Km) were used to test bias temperature instability without edge effects.

lifetime at V, of 1.7 V and 1.5 V, respectively. It should be noted that, despite the fact that boron in H f Q is more concentrated for the SN devices due to the barrier effect of the SN layer 141, it did not exacerbate the degradation. After negative bias temperature instability (NBTI) stressing, negative Vt shift and Gm degradation have been observed on Hf02 PMOSFET (Fig. 7). Setting the device lifetime as AV, = 50 mV, its V, dependence is summarized in Fig. 8 for different temperatures. Whereas sufficient V, at 10-year lifetime was obtained for those without SN, the SN devices exhibited shorter lifetime. , This is attributed to the existence of nitrogen at the interface, as observed on oxynitride dielectrics [5]. Note that HfO2 itself does not degrade NBTI, comparing Fig. 8 to ref. [5]. Unlike SiOzbased dielectrics, thicker equivalent oxide thickness (EOT) resulted in worse NBTI immunity (Fig. 9). It was found that AGm was smaller for the thicker films when the same AVt was reached (not shown). This implies that, in addition to the conventional mechanism of NBTI with positive charge generation at the Si-Si02 (of interfacial layer) [6], HfO2 has bulk charge traps particularly for those with thicker EOT. Fig. 10 shows that higher PDA temperature improved NBTI significantly, although it slightly increased EOT. NMOS instability has also been tested under positive gate bias. Turnaround effect of V, degradation is observed for relatively high voltages (Fig. 11). It is speculated that this is due to the competing effects of electron trapping (AV, > 0) and positive charge geneFation at the interface (AVt < 0). Lifetime at 125°C is summarized in Fig. 12. Although accurate extrapolation is difficult due to the turn-around effect, lifetime seems to be dominated by V, degradation.

Conclusion Reliability of HfOz with polysilicon gate electrode has been studied, in terms of TDDB and transistor instabilities on both N and PMOS. Both N and PMOS capacitors have high enough TDDB lifetimes, with gradual increase in the leakage current of PMOS. HfOz PMOSFET’s show sufficient NBTI immunity, although it can be degraded with nitrogen existence at the interface. NBTI can be further improved by optimizing EOT and post deposition annealing temperature. NMOS V, instability due. to bias temperature can be a potential scaling limit for Hf02. ,

Results and Discussions TDDB distribution of NMOS capacitors is shown on Fig. 1. From the distribution and the area dependence of TBD (Fig. 2), Weibull slope p was calculated to be -1.2. V, for Acknowledgement: This work was partially supported by SRCEEMATECH through FEP Research Center, and Texas 10-year lifetime of the measured 100 pm2 devices was extrapolated to be --1.9 V using the E-model (Fig. 3), and the Advanced Technology Program. projected V, for 0.1 cm2 devices was --1.3V using p -1.2. References PMOS was also stressed with CVS, but gate leakage current [l] L. Kang et al., IEDM Tech. Dig.;p. 35,2000. showed gradual increase without clear breakdown, for both [2] W.-J. Qi et al., IRPS, p. 72,2000. stressing bias and monitoring condition at 1.5 V (Fig. 4). A practical breakdown criterion of 100 mA/cm2 at 1.5 V was set [3] K. Onishi et al., IEDM Tech. Dig., p. 659, 2001. and evaluated for various bias conditions (Fig. 5), and 50 YO [4] K. Onishi et al., Symp. VLSI Tech., p. 131, 2001. [5]N. Kimizuka et al., Symp. VLSl Tech., p. 92,2000. time-to-failure was extrapolated in Fig. 6. Both devices with and without SN show similar behaviors with‘the 10-year [6] S. Ogawa et al., JAP 77, p. 1137, 1995. 0-7803-7352-9/02/$17.0002002 IEEE


IEEE 02CH37320.40th Annual International Reliability

Physics Symposium, Dallas, Texas, 2002



- .

. . ......



,' NMOS capwitor

fOlO.1 c"

loo pm' IO' -3.5

TBD (sec) Fig. I. NMOScapacitor TDDB. TDDB was measured by constant voltage stress at room

Area (cm2) Fig. 2. Area dependence of TBD. Weibull slope p was calculited to be -1.2.


2.7V 2.6V

-2.5 -2 -1.5 -1 Gale Voltage (V) Fig. 3. For :ipractical device area of 0.1 em2, V, for 10-year lifetime was extrapolated to be -1.3 V for NMOS capacitors. -3

2.5V 10' EOT-12A EOT-15A .-



PMOSCAP'~100 pm'






g ate Vdiwe (v) Fig. 1. PMOSFET Id-Vacharacteristics before and afler stress. Negative V, shift and slight Gm degradation are observed.



Lifetime (sec) Fig. 5. Distibutians of time to leakage current of 100 d c m ' on PMOS capacitors. Tail of 2.5 V is from sofl breakdown-like behavior.

2 25 3 vg (VI Fig. 6. Lifetimc extrapolation of PMOS capacitorr. for time to leakage current of 100 dcm'.

GateVoitage (V) Fig. 8. Lifetime extrapolation far PMOS NBTI. SN devices have stranger temperature dependence.

EOT (h) Fig. 9. E,OTdependence of gate voltages to asswe IC1 years lifetime. Thicker EOT does not neccssanly extend the lifetime.


Time (sec) Fig. 4. Time evolution of gate leakage current on PMOS capacitors. While stressing at 2.5 V, leakage has been periodically monitored at I .5 V.






+ AGm = -5 % -0.-

AVt = 50mV

NMOSFET L = 5 pm

-2 -1.5 -1 vg (VI Fig IO.NBTl dependence on post deposition annealing (PDA) t~mpetarure.



Time (sec) Fig. 11, BT on NMOSFET's. Tum-around of V, is observed at higher voltages.


Vg (V) Fig. 12. NMOSFET lifetime extrapolation for BT. V, degradation dominates the lifetime.

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