DIGITAL ULTRAFAST CARRIER RECOVERY FOR ... - IEEE Xplore

IEEE Transactions on Consumer Electronics,Vol. 42, No. 1, FEBRUARY 1996

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DIGITAL ULTRAFAST CARRIER RECOVERY FOR INTERACTIVE TRANSMISSION SYSTEMS Chuck Brown, Member, I€€€, Gary Do, Student Member, I€€€, and Kamilo Feher, fellow, /€€E Digital Wireless Communication Research Laboratory University of California, Davis

Abstract - An ultrafast, all-digital method for phase synchronization and coherent carrier recovery i s presented for time division multiple access (TDMA) and code division multiple access (CDMA) burst data communication systems. A new adaptive phase tracking (APT) method, presented and analyzed in this paper, uses a hard-limited IF signal in a feed forward configuration for carrier phase detection and recovery. A novel new technique of phase window filtering is presented as a means to combat noise induced phase errors, and improved the performance of a digital controlled phase shift oscillator by 7 dB. Experimental measurements show APT provides robust bit error rate (BER) performance within 1 dB of the theoretical binary phase shift keyed (BPSK) and tenths of dBs of an ideal hard wired clock. APT achieves acquisition within one- to four-bits -- 5 to 10 times faster than present requirements. A low power, low cost single chip fast carrier synchronization and demodulation solution for QPSK, GMSK and GSM compatible OQPSK and Feher's quadrature phase shift keyed (FQPSK) and binary phase shift keyed (FBPSK) systems [lo] are also presented.

I. INTRODUCTION

In interactive digital data transmission systems using burst phase shift keyed (PSK) or frequency shift keyed (FSK) modulation, the receiver is often faced with the dilemma of quickly and accurately estimating the incoming carrier phase and frequency coherently in order to demodulate the data with minimal error. In cable systems, the receivers or subscribers of burst transmissions are typically located at various distances away from the transmitter on the same cable. If each of the subscribers can identify the transmitter carrier frequency, A, with reasonable high accuracy, then it is only necessary to synchronize and track the incoming carrier phase information. Similarly, the head of end (base station) having knowledge of the subscriber's reply frequency simply needs to perform fast phase synchronization and tracking. Coherent demodulation is desired because it offers low power consumption and good bit error rate (BER) performance [ 11. However, traditional analog coherent demodulation techniques require longer acquisition times and are not

Manuscript received June 12, 1995

0098 3063/96 $04.00

well suited for burst signal demodulation. Unlike traditional carrier recovery circuits where the recovered carrier is a function of phase averaging in a limited bandwidth Phase-Locked-Loop (PLL), nonlinear estimation of canier phase uses an entirely different approach to synthesize the recovered clock. This method, frst proposed in El] and studied in [2] estimates the carrier frequency offset by using a nonlinear element to detect the baseband differential phase error and average it over a burst frame. [3] proposed an adaptive carrier tracking technique using the hardlimited baseband signal in combination with a feedback Costas loop to estimate frequency error. And [4] used a hardlimited filtered intermediate frequency (IF) signal in an automatic controlled feedback loop to estimate baud timing in combination with differential detection. This paper presents a new adaptive phase tracking (APT) technique that uses a hardlimited IF signal and a novel phase noise rejection method to estimate phase error and synthesize a coherent recovered clock in a feedforward configuration. All digital, single-chip carrier recovery designs are presented for the demodulation of BPSK, FBPSK, FQPSK and traditional QPSK signals. The experimental BPSK design provides phase acquisition to within a range k 11.25 degrees and acquisition time within 1 to 4 bits. Smaller phase acquisition error can be achieved by slight modification to the design and sampling rate. Since this design is an entirely digital architecture, it is suitable for field programmable gate array (FPGA) implementation with fewer and less expensive components than found in its PLL counterpart (such as Costas Loop) where analog, digital and RF circuits are found in mixed variety. Results are verified in a BPSK test environment which simulates an interactive cable transmission medium with instantaneous phase shift in the received carrier. Over the entire 360 degrees phase change range, the carrier recovery circprit maintained phase alignment for coherent detection. The system was evaluated under Additive White Gaussian Noise (AWGN) conditions. Results are exceptional, providing bit error rate performance within 1 dB of theory, and tenths of dB within hardwired carrier recovery. Research on Raleigh faded interference is underway.

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Brown, Do, and Feher: Digital Ultrafast Carrier Recovery for Interactive Transmission Systems

phase and frequency differences between the transmitter and receiver clocks are zero [ 5 ] .

“(t)

Recovery

B. Phase Synchronizationper burstfiame To achieve synchronization, the carrier frequency uncertainty Af = f; - f, must be kept small relative to the symbol rate I/Tv This condition can easily be achieved using stable oscillator sources andor tracking the frequency. [ 11 showed that the phase accuracy can not be maintained from one data burst to the next because the phase difference between frames is a function of the frame duration tfOme. That is to say,

-9

Recovery

Fig. 1. Carrier Modulated Digital Transmission (3)

11. COHERENT SYNCHRONIZATION PRINCIPLE

A. Synchronization and Carrier Recovery Consider an interactive data transmission system (Fig. l), to support multiple channels (users) on the same physical transmission medium (cable or wireless frequency spectrum) it is common to modulate the transmitted baseband signal sL(@onto a carrier cos(oa@using various phase or frequency modulation techniques. The resulting transmitted signal is represented by

where A(@is the amplitude, $a(@ is a constant phase shift, ak is the binary data symbol taking on values of f l , gT is the data signal pulse shape, T, is the symbol duration and eo is a constant time shift. The received signal at the input of the receiver y(@ consists of the modulated signal s(@, noise n(@ and intersymbol interference (ISI) i(@expressed as y ( t ) = s(t)+ n(t)+ i(t) = A(r)s,(t - -EcT,)cos(oOr- e , ( t ) ) with

If synchronization is to be achieved in a data transmission system, the phase must be estimated for each burst. C. Avoiding Frame Synchronization Errors Proper frame synchronization is achieved by sampling the demodulated baseband signal yL(@ in the middle of the symbol duration T, within a certain 6% of T, for a given performance level. Any frequency uncertainty between the transmitter and receiver, Af = f; - f,, limits the maximum burst length L, without some means of maintaining (tracking) the frequency drift. The time between the beginning of the burst frame and the middle of the last bit at the transmitter is

tframe-xmirr =

1

(5+ L a x 11 f, .

And similarly at the receiver is

To avoid a framing error, the difference between the transmitted and received frame duration must be within 6% of the symbol duration T,. That is to say,

(2)

@~(t)=em(t>+ec(t)The transmitted phase ed@is a combination of the modulated phase em(()and carrier phase e,(@. To retrieve the information sequence {ak), the received signal U(@ is converted (demodulated) back to a baseband signal yL(@. For coherent carrier recovery to operate correctly, the receiver oscillator with a frequency or must match the transmitted carrier frequency U,, = 2 j ; with the same phase, e,.(() = e,($. Synchronization occurs when the estimated

(4)

or

Thus, the maximum burst length is given by

IEEE Transactions on Consumer Electronics, Vol. 42, No. 1, FEBRUARY 1996

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Provided the frequency uncertainty and phase error #=e,0,.can be maintained with an acceptable range to support the desired burst length, phase tracking alone provides robust clock synchronization - as our results will show.

D. Degradation Effects of Phase Estimation Error For binary phase shift keyed (BPSK) modulation, [6] shows that provided the variation of the phase error d$ / dt is slow with respect to symbol rate T, , then the probability of a bit being received in error (for BPSK) becomes

:

1. PBPSK(e) = -[1-erf(A2T’cos2$/2N,)’/2] 2

18

1olog,,(l-sin20 )

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14 12

QPSWFQPSK

and the resulting signal-to-noise ratio (S/N) is degraded by

2o

BPSWFBPSK

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2

6

:

0

(6)

10 log,,cos

i

16

10

20

30

50

40

Phase Error

I$

60

70

80

90

(degrees)

Fig. 2. Degradation of S/N Due to Phase Error

$1

IlOlog,, cos2 dB as plotted in Fig. 2. For example, assume the frequency uncertainty is zero, a phase uncertainty of k11.25 degrees (27c/32 radians) results in less than 0.2 dB degradation for a BPSK signal. Quadrature phase shift keyed (QPSK and FQPSK) modulation can be viewed as a combination of two BPSK signals, each with a 7c/4 phase error shift from the ideal phase /3 [6]. Substituting 4=7c/4+p and Ts=2T, into (6) yields a bit error rate probability of each signal of 1 Pbl,bZ(e)= - (1 - erf [A2T,COS2 (Z / 4 5 p ) / 2N,]’’2) 2 (7) 1 = - (1 - erf[A2kb(1 k sin 2p) / 2N,]”2} 2 Assuming random data, each signal has equal probability of occurring, thus the total probability of bit error for QPSK becomes 1 1 PQPSK ( e )= pbl (e>+ pb2 (e>

5

zz

1 1 -{I- -erf[A2Tb (1 - S i n 2p) / 2N,]”2 2

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(8)

1 2

- - erf[A2Tb(1 + sin2P) / 2N,]”*} For p > 5” and low BER, Pb,(e)>>Pb2(e)and 1

P ~ p s ~ (ze-(1) erf[A2Tb(1-sin2p)l 2N,]”2) 2

(9)

Thus for QPSK the S/N degradation is proportional to (1 sin2p) as shown in Fig. 2. To achieve a degradation less than 1 dB requires a phase uncertainty less than +6 degrees (2d64 radians).

III. NONLINEAR IF COHERENT DEMODULATOR WITH ADAPTIVE PHASE TRACKING CIRCUIT A. A New Carrier Recovely Technique Fig. 3 shows the basic concept of the APT carrier recovery technique. The modulated BPSK IF signal y(t) is feed through a nonlinear hardlimiting amplifier where amplitude variations are removed and the total phase of resulting limited IF signal %& contains the modulated carrier phase f3,@ given by

where ecfgis the desired carrier signal to be recovered. According to (14) the modulated IF phase experiences a 7t radian phase shift based on the transmitted data symbol fad. Such instantaneous phase shifts occur during symbol transitions and if the receiver tries to synchronize on every symbol the recovered LO will lose tracking (jumping out of phase on transitions). To achieve proper synchronization, the carrier recovery circuit must detect and track the phase corresponding to one, and only one, of the symbols. Using this phase information, the phase of receiver local oscillator is aligned with the carrier phase and used to demodulated the signal. The carrier recovery circuit, however, may not be capable of distinguishing e,(q from eC(t)+n.If the latter is selected, a steady 180” phase error in the recovered carrier is possible. This phase error causes a 100% error rate. Fortunately, differential encoding can be used to avoid error introduced by phase ambiguity [ 101 ~

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Brown, Do, and Feher:

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Digital Ultrafast Carrier Recovery for Interactive Transmission Systems

B. Phase Tracking Circuit Operationfor BPSK and FBPSK The method used to estimate and recover the carrier phase is known as the digital controlled oscillator based on controlled phase shifting [7]. It does not suffer from limited bandwidth loop dynamics and is inherently fast. The basic structure of the phase tracking circuit consists of a duty-cycle comparator, phase window detector, phase counter, phase and selection latch, an 2" cell ring connected shift register (SHR) and multiplexer (MUX) as shown in Fig. 4. The receiver LO drives the SHR and phase counter at a rate equal to 2" times the desired output frequency. That is to say,

Phase1 f3c(t)

&(t)

BC(t)+TI

Limited IF, yHL(f)

Phase Counter

3

Recovered LO

- -/ The SHR is initially preset with an equal number of ones and zeros as shown to provide an output with a 50% duty cycle. The contents of the n bit wide selection latch control the MUX that selects a signal from one of the 2" outputs of the SHR. By latching a different phase state, the phase of the output signal e,, is adjusted over a range of 2n radians. For proper synchronization to occur, the latched phase state fiJ,fchmust be equal to the transmitted carrier phase 6,. The duty cycle comparator consists of an edge and pulse width detector to compare the time between rising edges of limited IF signal (Fig. 5 ) . When the comparison differs by more than a set number of LO counts, it is assumed that a phase transition has occurred. By adjusting the count threshold, symbol jitter may be rejected within limits. Once the phase change is determined, a circuit gates the 2nd IF rising edge (from the start of the symbol) to latch the phase count error. In a noiseless or high signal-to-noise environment, this phase error count can be used to select the nearest phase from the 2" SHR outputs [connecting the phase state latch directly to the MUX selection inputs]. Our initial experimental research results show that prior to our improvements, the use of the phase change pulse to directly trigger the selection latch is very sensitive to missing or extra Vansitions, and can not be used in a noisy environment without significant performance degradation. While our initial results are very encouraging for high S / N environments, fortunately we discovered the phase window filtering method as a means to improve performance under low S / N conditions. The phase window detector (Fig. 6 ) verifies that the latched phase error is within a predetermined phase range (shaded region of Fig. 7) of the previously adjusted fOub thereby filtering out noisy transitions. This circuit prevents the phase off,,, from latching to the phase of an incorrect symbol (cos (0,(t) + nj in the case of BPSK) or a noise induced phase state outside the desired window range.

f3c(t)

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Adjust Phase

FLO Fout = 2n

18c(t)+TTI

1-tacquisition

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Fig. 3. BPSK Phase Demodulation and Adaptive Tracking Limited IF

SHR

VFout N

LO

Fig. 4. BPSK and FBPSK Phase Tracking Circuit Basic Structure

lSET

Edge Detectoi Rising IF Edge Pulse

/

ulse Width Detect

Duration

Fig. 5 . Duty Cycle Comparator


136

phase of the hardlimited IF QPSK or FQPSK signal given bY

Selection

. PHASE-CNT

I

1 x

LO I SYNC-RESET

1 -

I

I IFXED

Fig. 6. Phase Window Detector

+

c

Im yn.(t)

-

I Fig. 7. Phase Noise Rejection Following a system reset or end of a burst frame, a SYNC-RESET signal, aligned to the symbol edge, is generated. This signal latches the phase state, X,of the first symbol into the selection latch. At the same time, the track state latch is triggered -- capturing the desired phase state value Y. Resynchronization of the recovered carrier phase occurs only when subsequent phase states are with the desired range window of _+ m. Once the latched phase count compares with the window range, Y-m 5 X _< Y+m , an adjust pulse is created and latches the phase error count in the selection register. The phase noise (error) can be easily controlled in the design thus reducing output phase jitter. Total output phase noise is an accumulation of shift register induced phase jitter and jitter noise from digital logic switching circuitry. The estimated phase error is

In the phase window detector the phase tracking range must be reduced to a value no greater than 4n/4 to prevent the circuit inadvertently locking onto the phase of another symbol quadrant, this inducing errors. For GMSK, QPSK and FQPSK, the phase of the desired canier signal is not contained in the limited IF signal as it was in BPSK transmission. To accommodate, the selection inputs ofthe MUXes are adjusted to provide the desired shift of nf4 radians. The circuit latches to the phase of the first symbol and readjusts the LO each time it can be determined that the present phase is within the desired window range. To track slow varying phase drift beyond f n/4, the EIXED signal (Fig. 6 ) is set to a logic high level to reload the track state latch with the phase offset following an adjustment. Setting /FIXED low fixes the window range. Other changes include the addition of a second output (recovered carrier plus 90 degrees) as required by the quadrature demodulator mixer. This is easily accomplished by adding a second output MUX with the same selection inputs as the primary MUX, but with its inputs shifting to achieve the 90 degree phase shifted output, as shown in Fig. 8. To reduce the degradation effects of phase uncertainty, the length of the SHR must also be increased to provide greater phase resolution. Increasing the length from 16 to 32 bits provides a phase resolution of k5.6" for a degradation of 1dB according to (9). Additional slight modifications can be made to accommodate the demodulation of Gaussian frequency shift keyed signals, GFSK.

IV. IMPLEMENTATION

C. Phase Tracking Circuitfor GMSK, OQPSK and FQPSK To support the demodulation of quadrature phase shift keyed signals like GMSK, OQPSK and FQPSK, modification are needed to the phase window detector and output MUX. To understand these changes, consider the total

The all-digital APT carrier recovery circuit was implemented in a field programmable gate array (FPGA). The FPGA contains the duty-cycle comparator, phase quadrant detector, phase counter, phase and selection latch, a 16 bit (n=4,2"=16) ring connected shift register (SHR) and a 16:1 multiplexer as shown in Fig. 4. A 1 MHz clock frequency



BERNetwork

137

LPF

RPSK

AWGN Soucre

U Threshold Detector

Fig. 9. Experimental Test Setup

Fig. 8. GMSK, OQPSK and FQPSK Adaptive Phase Tracking Circuit was used to provide a phase resolution of k 2 d 1 6 radians (k11.25 degrees) for a data rate of 15.625Kb/s according to (9). This limits the S / N degradation to within 0.2 dB according to (6).

v. EXPERIMENTAL RESULTS An experimental data transmission system (Fig. 9) was setup to analyze the performance of the APT carrier recovery method. The transmitter produced a 15.625Kbls pseudo-random BPSK data signal. The BPSK signal was pulse shaped by a 4th order Butterworth low pass filter (LPF) with a BTb=0.55, and transmitted on a cabled transmission channel at an intermediate frequency of 62.5KHz. This low bit rate was selected to eliminate the effects of propagation and routing delays within the FPGA. However, analysis shows that this design can accommodate IF frequencies of 2 MHz or more with only minor changes to adjust for internal delays. The APT circuit, hard limiter, 4th order LPF and threshold detector made up the rest of the receiver.

A. Signal Detection Fig. 10 shows the demodulated eye-diagram pattern at the input of the threshold detector for the APT circuit under various SM levels. Under high signal to noise conditions, the demodulated signal was free IS1 interference and contained only small amounts of jitter due to filter imperfections. As the S / N level was decreased, the IS1 increased as expected, but the phase noise variations are removed by the phase window detector, providing an open eye in the middle of each symbol time slot (Fig. lob).

B. Bit Error Rate Performance Additive White Gaussian Noise (AWGN) was injected into the test system to characterize the bit error rate performance of the carrier recovery circuit in a static environment. Fig. 11 shows the results of the continuous mode BER measurements. The static AWGN BER performance measurements of the APT with phase window detector are within 1 dB of theory and within tenths of dBs of the measured hard wired carrier recovery control test [ideal demodulation using the exact transmitter frequency and phase at the receiver]. The phase window detector improved the BER performance 7 dB. The hard wired carrier recovery control test case was also within 1 dB of theoretical performance. The deviation from theory for the control case can be attributed to the test setup, and suggests that the proposed digital APT carrier recovery circuit operates at near theoretical performance within the limits set by (6) and (9). Adaptive phase tracking provides exceptional receiver synchronization when the frequency offset and drift between the receiver and transmitter that are maintained within expectable limits. C. Acquisition Time The acquisition time (measured in bits) is a function of the initial frequency uncertainty between the transmitter and receiver clocks and the probability of a noise induced phase error. Computer timing simulations show the APT circuit achieves phase lock within the first transmitted symbol assuming no frequency uncertainty and low noise environment ( S / N > 20dB). Multiple samples per IF duration provides large processing capability during each bit duration. This allows the APT to achieve locking within one- to fourbits, depending on the noise level. This is 4 to 5 time faster than conventional synchronizationrequirements. A detailed evaluation using computer simulation and measured data is underway.


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VI. CONCLUSION

A new all-digital method for phase synchronization and coherent carrier recovery was presented and analyzed for BPSK, FBPSK, QPSK and FQPSK demodulation. The adaptive phase tracking method uses a hard-limited IF signal for carrier phase detection and recovery. A novel phase window detector circuit was presented as a means to reject phase noise variations and improved performance in a low S/N environment by 7 dB or more. Simulation results show the APT circuit achieves synchronization within the first four symbols and is thus well suited for interactive transmission systems using time division multiple access (TDMA) ar code division multiple access (CDMA) burst data communications. It was also shown experimentally that the APT method is quite robust with respect to bit error rate (BER) performance, within 1 dB of theoretical levels for coherent BPSK and tenths of dBs within hard wired carrier recovery. The APT scheme provides a low cost, single chip solution to fast synchronization problems, and can be easily adapted for other demodulation methods such as GMSK and GFSK.

(a) Noise-free environment, S/N > 30dB (slight jitter due to filter imperfections)

ACKNOWLEDGMENT The authors would llke to acknowledge Wei Gao for his assistance in the experimental setup and testing.

(E,/N,=lO.ldB,within 1dB of theory) Fig. 10. Demodulated Eye Diagram

REFERENCES [l] A.J. Viterbi and A.M. Viterbi, “Nonlinear estimation of PSK modu-

4

I

(ideal)

0

4

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8

I

12

16

Signal-to-Noise

I

I

20 24 EblNo (dB)

Fig. 1 1. Static AWGN BER Performance (Af=O, fixed window, m = +1)

lated carrier phase with application to burst digital transmission,” IEEE Trans. Info. 7lleoly. vol.IT-32, July 1983, pp. 543-551. [2] I. Chuang and N.R. Sollenberger, “Burst coherent demodulation with combined symbol timing, frequency offset estimation and diversity selection,” IEEE Trans. on Comm., July 1991. [3] S. Saito and H. Suzuki, “Fast carrier-tracking coherent detection with dual mode carrier recovery circuit for digital land mobile radio transmission,” IEEE Journal on Selected Areas in Comm., vol. 7, no. 1, January 1989, pp.130-139. [4] H. Tomita, Y . Yokoyama and T. Matsuki, “Digital intermediate frequency demodulation technique for cellular communication systems,” Proceedings IEEE GLOBECOM ‘90, San Diego, Ca, December 1990, pp. 1827-1831. [5] H. Meyr and G. Ascheid, “Synchronization in Digital Communications-vol. 1,” John Wiley, 1990. [6] K. Feher and D. Chan, “PSK combiners for fading microwave channeIs,”IEEE Trans. on Comm., May 1975, pp.554-558. [7] G. Donzellini, D.D. Caviglia, G. Parodi, D. Ponta and P. Repetto, “A digital oscillator based on controlled phase shifting,” IEEE Trans. on CircuitsundSystems, vo1.36, no.8, August 1989, pp.1101-1105. [8] K. Feher, ‘‘Filters,” U S . Patent 4339724, isssued July 13, 1982; Canada Patent 1130871, Aug. 31, 1982. [9] S. Kat0 and K. Feher, “Correlated Signal Processor,” U S . Patent 4567602, isssued January 28, 1986. [lo] K. Feher, “Wireless Digital Communications: Modulation and Spread Spectrum Techniques,” Prentice Hall, 1995. [l 11 K. Feher, “Digital Communications; SatellitelEarth Station Engineering,” Prentice Hall, 1983.



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BIOGFWPHIES Chuck Brown received his Bachelor’s degree in electrical engineering from the University of California at Davis in 1984, and obtained his Master’s degree in 1986 from Stanford University. He joined IBM’s development lab in 1984 where he worked as a design engineer on high speed data communication ASICs. Since 1993 he has been employed by Intel Corporation as a Senior Engineer working on advanced personal communication systems. He also is engaged in research at the Digital Wireless Communications Laboratory at the University of California at Davis in pursuit of his Ph.D. in electrical engineering. His research interests are in the areas of digital communications, development and evaluation of digital synchronization algorithms, reconfigurable modulation methods and fully digital implementation of transceivers. Gary Do received his Bachelor’s Degree from the University of California at San Diego in 1990 and shortly after joined TRWs Space and Defense sector where worked as a phaselocked-loop design engineer. While at TRW, he worked towards his Master’s Degree which he received in 1993 from the University of Southern California. He joined the Digital Wireless Communications Lab in 1994 where he is currently working towards his Ph.D. His research interests are in computer modeling of communication systenis, frequency synthesis, digital synchronization and signal processing teckmiques.

Kamilo Feher, Fellow of IEEE and Professor of electrical and computer engineering at the University of California at Davis. He directs one of the most productive experimental digital wireless modulatiodRF design research laboratories. This laboratory includes the operation of a multi-base station cellular campus-wide “test b e d facility. He is author of six books and many publications. Through Dr. Feher’s associates-Digcom Inc. and the FQPSK consortium, he is active in consulting, training, technology transfer and licensing of his DSP, filter, processor, GMSK, GFSK, “F-Modem,” FBPSK and FQPSK family of patented inventions. His most recent book “Wireless Digital Communications: Modulation and Spread Spectrum Applications” is now available from Prentice Hall.