Effects of Measurement Temperature on NBTI - CiteSeerX

5 downloads 0 Views 94KB Size Report
Authorized licensed use limited to: LIVERPOOL JOHN MOORES UNIVERSITY. Downloaded on May 5, 2009 at 09:25 from IEEE Xplore. Restrictions apply.

298

IEEE ELECTRON DEVICE LETTERS, VOL. 28, NO. 4, APRIL 2007

Effects of Measurement Temperature on NBTI J. F. Zhang, M. H. Chang, and G. Groeseneken

Abstract—Negative bias temperature instability (NBTI) is a pressing reliability issue for the CMOS industry. NBTI has been measured at stress temperature in most of the recent works. For the first time, this letter will demonstrate that, for a given number of defects, the threshold-voltage shift measured at stress temperature can be less than half of its value at room temperature. As a result, the data obtained at different measurement temperatures should not be used for extracting the thermal enhancement of defect creation. In the future, this newly identified dependence on measurement temperature should be taken into account when estimating the NBTI limited lifetime of pMOSFETs. Index Terms—Bias temperature instability (BTI), defects, degradation, gate dielectric, lifetime, negative BTI (NBTI), oxynitrides.

I. I NTRODUCTION

A

S THE thickness of gate oxynitrides (SiOxNy) reduces, the density of nitrogen has increased rapidly in order to suppress boron penetration and to reduce gate leakage current. One adverse effect of this increase in nitrogen density is a substantial enhancement of the negative bias temperature instability (NBTI) [1]–[5]. The NBTI is so severe now that it limits the lifetime of pMOSFETs and becomes a pressing reliability issue for the CMOS industry [1]–[6]. This has motivated intensive research on NBTI recently [1]–[6], but many issues remain to be solved. One of these issues is the effect of the measurement temperature on NBTI. Traditionally, after stressed at an elevated temperature, the device was cooled down, and defects were assessed at room temperature (RT) [7], [8]. Recently, the NBTI has often been measured at stress temperature [2], [9]–[11]. The threshold-voltage shift ∆Vt measured at different temperatures is often compared and used to extract the activation energy of the defect generation. How the measurement temperature affecting ∆Vt is not addressed, and the objective of this letter is to clarify this issue by reporting new experimental findings. It will be shown that, for a given level of defects, the ∆Vt measured at different temperatures can be substantially different. Consequently, the ∆Vt measured at different temperatures cannot be used to assess the thermal activation of defect creation by the negative bias temperature stress (NBTS). The defects and physical process responsible for this phenomenon will be discussed. Manuscript received November 15, 2006; revised January 6, 2007. The review of this letter was arranged by Editor A. Chatterjee. J. F. Zhang and M. H. Chang are with the School of Engineering, Liverpool John Moores University, L3 3AF Liverpool, U.K. (e-mail: [email protected]). G. Groeseneken is with the Interuniversity Microelectronics Center (IMEC), B3001 Leuven, Belgium, and also with the Department of Electrical Engineering (ESAT), Katholieke Universiteit Leuven, Leuven, Belgium. Digital Object Identifier 10.1109/LED.2007.893219

II. D EVICES AND E XPERIMENTS The pMOSFET used for NBTI tests has a surface channel and a p+ poly-Si gate. The channel length is 0.15 µm, and the channel width is 10 µm. The gate dielectric is a silicon oxynitride of 2.7 nm, oxidized at 850 ◦ C, and then nitrided in NO at 1050 ◦ C for 10 s. The stress temperature is in the range of RT to 200 ◦ C. To assess the effect of the measurement temperature on NBTI, the typical test procedure involves four steps. First, to find the threshold voltage Vt of a fresh device by the extrapolation method, the transfer characteristic (TC) was measured at a drain bias of −25 mV for several selected temperature points between RT and the stress temperature. For each TC, the gate bias was swept from 0 to −1 V in 20-mV steps, and the measurement took about 25 s. Second, the NBTS was carried out, and Vt was monitored periodically from the TC at the stress temperature. Third, at the end of the stress, the device was cooled to RT. Finally, the poststress Vt was measured at the same selected temperature points again. It should be pointed out that Vt itself in a fresh device changes with the measurement temperature. To eliminate the effect of this Vt variation, the NBTS-induced shift of Vt at a given temperature ∆Vt was evaluated from the difference in the Vt measured at the same temperature before and after the stress [12], [13]. The maximum measurement temperature is the stress temperature. The stress gate bias was −3.17 V. III. R ESULTS AND D ISCUSSIONS Fig. 1 shows the degradation of the threshold voltage ∆Vt when stressed and measured at 200 ◦ C. After the stress, the device was cooled down, and the ∆Vt was evaluated again at RT. The effect of the measurement temperature may appear small (< 15%), and one could say that the ∆Vt is insensitive to the measurement temperature. However, in the following, we will show that such “insensitivity” is an artifact. It is well known that NBTI is highly dynamic, and considerable recovery could occur after the stress. To measure the ∆Vt at RT in Fig. 1, the device must be cooled down from 200 ◦ C, which took 4 min. The recovery of ∆Vt during this period must be assessed. Fig. 1 shows that ∆Vt indeed recovers rapidly once the stress was removed. If the ∆Vt was truly insensitive to the measurement temperature, the recovery should lead to a decrease of ∆Vt when measured at RT. Such a decrease cannot be observed in Fig. 1, and a correct explanation for the “insensitivity” will be searched. It is possible that the “insensitivity” results from the balance of two competing processes. One is the recovery that reduces ∆Vt . The other is an increase of ∆Vt at lower measurement temperature. To study whether ∆Vt indeed increases for lower

0741-3106/$25.00 © 2007 IEEE

Authorized licensed use limited to: LIVERPOOL JOHN MOORES UNIVERSITY. Downloaded on May 5, 2009 at 09:25 from IEEE Xplore. Restrictions apply.

ZHANG et al.: EFFECTS OF MEASUREMENT TEMPERATURE ON NBTI

Fig. 1. Threshold-voltage shift ∆Vt during NBTS and recovery. Two devices were subjected to the same NBTS at Vgs = −3.17 V and 200 ◦ C for 1000 s. One of them was then kept at 200 ◦ C under Vgs = 0, and the recovery of ∆Vt was monitored (symbol “×”). The other was cooled down to RT, and the ∆Vt was measured again. Despite the loss of charges and defects during the cooling, there is a modest increase of ∆Vt at RT.

299

Fig. 2. Impact of measurement temperature on ∆Vt . In (a), one device was stressed at 200 ◦ C for 1000 s and then cooled to RT. The temperature was raised back to 200 ◦ C in a sequence of RT → 65 ◦ C → 100 ◦ C → 150 ◦ C → 200 ◦ C. The symbol “o” represents the ∆Vt measured at each temperature. After reaching 200 ◦ C, the device was cooled down again, and ∆Vt was measured for the second time at RT. In (b), one device was stressed at 65 ◦ C for 1000 s. The ∆Vt (RT) was measured after cooling down to RT, and ∆Vt (T ) was obtained after warming up back to the stress temperature; T · ∆Vt (RT)/∆Vt (T ) reaches 2.5 when T = 65 ◦ C.

measurement temperature, it is desirable to fix the number of defects when varying the measurement temperature. Fig. 1 shows that the recovery mainly occurs in the initial period, and ∆Vt becomes reasonably stable after, say, 100 s. As a result, it is better to investigate the impact of measurement temperature after this initial recovery period. It is possible that the rapid recovery phase is covered by the cooling period, and consequently, the ∆Vt becomes stable after the cooling. The effect of measurement temperature can be assessed by raising the temperature back to 200 ◦ C in the following sequence: RT → 65 ◦ C → 100 ◦ C → 150 ◦ C → 200 ◦ C. Fig. 2(a) shows that the ∆Vt reduces progressively as the measurement temperature rises. To check that the number of defects remains approximately constant during the above sequence, the device was cooled down and measured at RT again after reaching 200 ◦ C. Fig. 2(a) confirms the difference in the two ∆Vt measured at RT is insignificant. Furthermore, the ∆Vt measured after raising the temperature back to 200 ◦ C [64 mV in Fig. 2(a)] is also close to the “postrecovery” ∆Vt (66 mV) shown in Fig. 1. We conclude that, for a given number of defects, ∆Vt reduces for the higher measurement temperature. The device was stressed at 200 ◦ C in Fig. 2(a). The question is what will the measurement temperature effect be when stressing at lower temperature. Fig. 2(a) shows that when the measurement temperature is closer to RT, the ∆Vt is also closer to its value at RT. This may lead to the expectation that after stressing at lower temperature, the impact of measurement temperature should always reduce. For example, according to Fig. 2(a), ∆Vt at 65 ◦ C is only 8% lower than the ∆Vt at RT. One may assume that after stressing at 65 ◦ C, the impact of measurement at RT will be close to 8%.

Fig. 3. (a) Dependence of ∆Vt (RT)/∆Vt (T ) on the stress temperature. At each temperature, the NBTS was carried out under the same bias (Vgs = −3.17 V) and time (1000 s). The definition of ∆Vt (RT) and ∆Vt (T ) is shown in Fig. 2(b). ∆Vt (RT)/∆Vt (T ) drops toward 200 ◦ C, but it is still about 1.5 at 200 ◦ C. (b) Schematic energy band diagram is given to illustrate that positive charging reduces at higher measurement temperature for a given number of defects.

An experiment was carried out to test the above assumption. A device was stressed at 65 ◦ C, cooled down, and then warmed up to 65 ◦ C again. The ∆Vt measured at each temperature point is shown in Fig. 2(b). The ∆Vt after warming up back to 65 ◦ C was reduced by more than half, rather than the 8% suggested by Fig. 2(a). To assess the relative importance of the impact of measurement temperature, the ratio of ∆Vt (RT) against ∆Vt (T ) can be used, where ∆Vt (T ) is measured after warming up to the stress temperature, as shown in Fig. 2(b). Fig. 3(a) shows that ∆Vt (RT)/∆Vt (T ) reaches a maximum around 65 ◦ C and then actually reduces for the higher stress temperature. In the following, some speculations will be given on the defects and physical processes responsible for the observed measurement temperature effect. On the nature of the defect, it should be noted that these defects behave similarly to the “antineutralization positive charges (ANPC)” reported recently after substrate hole injection

Authorized licensed use limited to: LIVERPOOL JOHN MOORES UNIVERSITY. Downloaded on May 5, 2009 at 09:25 from IEEE Xplore. Restrictions apply.

300

IEEE ELECTRON DEVICE LETTERS, VOL. 28, NO. 4, APRIL 2007

[14]–[16]. The ANPC is one type of the generated hole traps [15]. When positively charged, they have energy levels above the bottom edge of the silicon conduction band, as shown in Fig. 3(b). This makes them able to survive neutralization even under the accumulation condition of pMOSFETs [15]. Fig. 3(b) illustrates that neutralizing the ANPC is a thermally activated process. It implies that, for a given number of defects, their positive charging increases for lower temperature. This can explain the enhanced ∆Vt at lower measurement temperature observed in Fig. 2(a) and (b). As a result, we speculate that ANPC was also created during NBTS, and they are responsible for the effect of measurement temperature on ∆Vt . The ANPC can also explain why the ∆Vt (RT)/∆Vt (T ) reduces for T > 65 ◦ C in Fig. 3(a). Our early work [15] clearly shows that ANPC is not stable and can be partially annealed. The higher the stress temperature, the more ANPC is annealed during the stress. As a result, the relative importance of ANPC reduces after stressing at higher temperature, resulting in a lower ∆Vt (RT)/∆Vt (T ). When compared with Fig. 2(b), the smaller ∆Vt (RT) − ∆Vt (65 ◦ C) in Fig. 2(a) is caused by the difference in stress temperature: 200 ◦ C in Fig. 2(a) but 65 ◦ C in Fig. 2(b). The good agreement between the properties of ANPC and the behavior of ∆Vt (RT)/∆Vt (T ) supports that ANPC is responsible for the impact of measurement temperature on NBTI. Finally, we explore the implication of our results to NBTS tests and whether our observation is sensitive to stress voltage and nitridation conditions. For the same number of defects, ∆Vt reduces for higher measurement temperature. Consequently, the ∆Vt measured at different temperatures should not be used to assess the thermal acceleration of the defect generation. On the stress voltage, there is clear evidence that both the injected holes and the released hydrogen can generate the ANPC responsible for the effect of measurement temperature [14]–[16]. Since it is well known that hydrogen is always released by the NBTS whatever is the stress voltage, the impact of measurement temperature will be visible as ANPC builds up. On the nitridation conditions, it has been reported that the thermal nitridation used here enhances positive charges and NBTI when compared with plasma nitridation [17]–[19]. However, ANPC can be generated even in pure SiO2 [14]–[16], and nitridation is not a necessary condition for creating ANPC. As a result, the observed temperature effect in this letter is not process specific. IV. C ONCLUSION The effect of measurement temperature on NBTI is investigated. To the best of our knowledge, for the first time, this letter clearly shows: 1) for a given number of defects, the threshold-voltage shift measured at stress temperature can be less than half of its value at RT and 2) the relative importance of measurement temperature to ∆Vt depends on the stress temperature. Consequently, the ∆Vt measured at different temperatures should not be used to assess the thermal acceleration of defect generation. It is proposed that the defect responsible for this temperature dependence is the ANPC. The ANPC has an energy level above the bottom edge of the silicon conduction

band, and its neutralization is thermally enhanced, leading to a lower ∆Vt at the higher measurement temperature. When modeling NBTI, this dependence of ∆Vt on measurement temperature was not taken into account in the past and should be taken into account in the future. R EFERENCES [1] N. K. Jha and V. R. Rao, “A new oxide trap-assisted NBTI degradation model,” IEEE Electron Device Lett., vol. 26, no. 9, pp. 687–689, Sep. 2005. [2] B. Kaczer, V. Arkhipov, M. Jurczak, and G. Groeseneken, “Negative bias temperature instability (NBTI) in SiO2 and SiON gate dielectrics understood through disorder-controlled kinetics,” Microelectron. Eng., vol. 80, pp. 122–125, 2005. [3] V. Huard, M. Denais, F. Perrier, N. Revil, C. Parthasarathy, A. Bravaix, and E. Vincent, “A thorough investigation of MOSFETs NBTI degradation,” Microelectron. Reliab., vol. 45, no. 1, pp. 83–98, Jan. 2005. [4] S. S. Tan, T. P. Chen, J. M. Soon, K. P. Loh, C. H. Ang, and L. Chen, “Nitrogen-enhanced negative bias temperature instability: An insight by experiment and first-principle calculations,” Appl. Phys. Lett., vol. 82, no. 12, pp. 1881–1883, Mar. 2003. [5] M. Houssa, M. Aoulaiche, J. L. Autran, C. Parthasarathy, N. Revil, and E. Vincent, “Modeling negative bias temperature instabilities in hole channel metal-oxide-semiconductor field effect transistors with ultrathin gate oxide layers,” J. Appl. Phys., vol. 95, no. 5, pp. 2786–2791, Mar. 2004. [6] S. Mahapatra, P. B. Kumar, and M. A. Alam, “Investigation and modeling of interface and bulk trap generation during negative bias temperature instability of p-MOSFETs,” IEEE Trans. Electron Devices, vol. 51, no. 9, pp. 1371–1379, Sep. 2004. [7] K. O. Jeppson and C. M. Svensson, “Negative bias stress of MOS devices at high electric fields and degradation of MNOS devices,” J. Appl. Phys., vol. 48, no. 5, pp. 2004–2014, May 1977. [8] C. E. Blat, E. H. Nicollian, and E. H. Poindexter, “Mechanism of negativebias-temperature instability,” J. Appl. Phys., vol. 69, no. 3, pp. 1712–1720, Feb. 1991. [9] M. Denais, A. Bravaix, V. Huard, C. Parthasarathy, G. Ribes, F. Perrier, Y. Rey-Tauriac, and N. Revil, “On-the-fly characterization of NBTI in ultra-thin gate oxide pMOSFET’s,” in IEDM Tech. Dig., Dec. 2004, pp. 109–112. [10] M. Ershov, S. Saxena, H. Karbasi, S. Winters, S. Minehane, J. Babcock, R. Lindley, P. Clifton, M. Redford, and A. Shibkov, “Dynamic recovery of negative bias temperature instability in p-type metal-oxide-semiconductor field-effect transistors,” Appl. Phys. Lett., vol. 83, no. 8, pp. 1647–1649, Aug. 2003. [11] K. Onishi, R. Choi, C. S. Kang, H. J. Cho, Y. H. Kim, R. E. Nieh, J. Han, S. A. Krishnan, M. S. Akbar, and J. C. Lee, “Bias-temperature instabilities of polysilicon gate HfO2 MOSFETs,” IEEE Trans. Electron Devices, vol. 50, no. 6, pp. 1517–1524, Jun. 2003. [12] J. F. Zhang and W. Eccleston, “Donor-like interface trap generation in pMOSFET’s at room temperature,” IEEE Trans. Electron Devices, vol. 41, no. 5, pp. 740–744, May 1994. [13] ——, “Positive bias temperature instability in MOSFET’s,” IEEE Trans. Electron Devices, vol. 45, no. 1, pp. 116–124, Jan. 1998. [14] C. Z. Zhao and J. F. Zhang, “Effects of hydrogen on positive charges in gate oxides,” J. Appl. Phys., vol. 97, no. 7, pp. 073703-1–073703-8, Apr. 2005. [15] J. F. Zhang, C. Z. Zhao, A. H. Chen, G. Groeseneken, and R. Degraeve, “Hole-traps in silicon dioxides—Part I: Properties,” IEEE Trans. Electron Devices, vol. 51, no. 8, pp. 1267–1273, Aug. 2004. [16] C. Z. Zhao, J. F. Zhang, G. Groeseneken, and R. Degraeve, “Hole-traps in silicon dioxides—Part II: Generation mechanism,” IEEE Trans. Electron Devices, vol. 51, no. 8, pp. 1274–1280, Aug. 2004. [17] V. Huard and M. Denais, “Hole trapping effect on methodology for dc and ac negative bias temperature instability measurements in pMOS transistors,” in Proc. IRPS, Apr. 2004, pp. 40–45. [18] C. H. Liu, M. T. Lee, C. Y. Lin, J. Chen, K. Schruefer, J. Brighten, N. Rovedo, T. B. Hook, M. V. Khare, S.-F. Huang, C. Wann, T.-C. Chen, and T. H. Ning, “Mechanism and process dependence of negative bias temperature instability (NBTI) for pMOSFETs with ultrathin gate dielectrics,” in IEDM Tech. Dig., Dec. 2001, pp. 861–864. [19] C. H. Ang, C. M. Lek, S. S. Tan, B. J. Cho, T. P. Chen, W. H. Lin, and J. Z. Zhen, “Negative bias temperature instability on plasma-nitrided silicon dioxide film,” Jpn. J. Appl. Phys., vol. 41, no. 3B, pp. L314–L316, Mar. 2002.

Authorized licensed use limited to: LIVERPOOL JOHN MOORES UNIVERSITY. Downloaded on May 5, 2009 at 09:25 from IEEE Xplore. Restrictions apply.

Suggest Documents