Japanese Journal of Applied Physics 49 (2010) 06GG14
REGULAR PAPER
Electrical Characteristics of TiSi2 Nanocrystal Nonvolatile Memory with Barrier-Engineered Tunnel Layer Seung Jong Han, Dong Uk Lee, Ki Bong Seo, Seon Pil Kim, Eun Kyu Kim, Jun-Seok Oh1 , and Won-Ju Cho1 Department of Physics and Research Institute for Natural Sciences, Hanyang University, Seoul 133-791, Korea 1 Department of Electronic Materials Engineering, Kwangwoon University, Seoul 139-701, Korea Received November 27, 2009; accepted March 7, 2010; published online June 21, 2010 In this study, we fabricated TiSi2 nanocrystal nonvolatile memory devices with silicon nitride–oxide–nitride (NON) and SiO2 tunnel barriers. The TiSi2 nanocrystals with diameters of 2 – 5 nm and a density of 1:5 1012 cm 2 were formed using radio frequency magnetron sputtering in argon and a postannealing process. The memory effect of the TiSi2 nanocrystal memory device with the NON tunnel barrier was observed at about 0.7 V at 100 ms when the applied program/erase voltages were +7 V/ 7 V. Also, the memory window of the NON tunnel barrier device was maintained up to 1.3 V after 103 s. These results indicate that the NON tunnel barrier provides an effective tunneling thickness for the fast program/erase speeds and an adequate physical thickness for long charge retention characteristics in nonvolatile memory devices. # 2010 The Japan Society of Applied Physics DOI: 10.1143/JJAP.49.06GG14
1.
Introduction
Nanocrystal nonvolatile memory is very attractive for nonvolatile memory applications because these devices have a small operating voltage, long retention properties, and fast program/erase speeds. The performance of nanocrystal memory has been improved by using various materials including Si, Au, SiC, NiSi, and CoSi.1–8) In particular, metal-silicide nanocrystals have resulted in higher densities of state and work functions and stronger coupling between the nanocrystals and the channel region. In addition, they have better thermal stability and compatibility for Si-based fabrication processes. Furthermore, TiSi2 has a large work function of 4.5 eV, good thermal stability, and chemical stability with Si atoms. Therefore, nanocrystal memory devices with TiSi2 nanocrystals are expected to demonstrate good electrical performance.9,10) When the thickness of a single-layered SiO2 tunnel barrier is less than 5 nm, the program and erase speeds will be enhanced, but the retention time is reduced owing to the degradation effect of the tunnel barrier during the program/erase bias. To overcome the limitations of conventional SiO2 tunnel barriers, a crested and variable oxide thickness (VARIOT) tunnel barrier has been proposed.11–13) A crested tunnel barrier consisting of a Si3 N4 –SiO2 –Si3 N4 (NON) structure has been used to decrease the program/erase voltage and improve the long retention time due to the Fowler–Nordheim (FN) tunneling between the Si substrate and the multiple stack dielectric materials. In this study, we demonstrated TiSi2 nanocrystal memory devices with NON and SiO2 tunnel barriers. Their electrical properties including subthreshold characteristics (ID –VG ), output characteristics (ID –VD ), threshold voltage shift, program/erase speeds, and retention time were evaluated. The effects of the crested tunnel barrier on the electrical performance of TiSi2 nanocrystal memory devices are also discussed in this paper. 2.
Experimental Methods
The TiSi2 nanocrystal memory devices with NON and SiO2 tunnel barriers were fabricated on p-type (100) wafers. The wafers had a 300-nm-thick SiO2 layer on a Si substrate.
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The active region was formed using photolithography and reactive ion etching (RIE) on a field oxide with a thickness of 400 nm. Subsequently, a phosphorus-doped polycrystalline silicon (poly-Si) layer with a thickness of 100 nm was deposited on the source and drain regions using low-pressure chemical vapor deposition (LPCVD) at 650 C. The doped poly-Si layer was partially removed to define the active region, and the channel region was etched to a depth of 30 nm for the recessed channel structure using photolithography and plasma RIE. Then, a tunnel barrier composed of NON (2 nm Si3 N4 /3 nm SiO2 /3 nm Si3 N4 ) and SiO2 was deposited by thermal oxidation, LPCVD, and LPCVDtetraethylorthosilicate (TEOS). The ultrathin TiSi2 films with a thickness of 5 nm were deposited onto the NON and SiO2 tunnel barriers by direct current magnetron sputtering. After these processes, a control barrier with a thickness of 30 nm was deposited by radio frequency magnetron sputtering with a SiO2 target. Subsequently, a postannealing process was carried out at 800 C for 2 min by rapid thermal annealing (RTA) under nitrogen gas to form the TiSi2 nanocrystals. Finally, a 200nm-thick aluminum gate electrode was deposited on the control barrier using a thermal evaporator, photolithography, and a phosphoric acid etching process. A schematic cross section of the memory device is shown in Fig. 1(a). The electrical characteristics of the TiSi2 nanocrystal memory devices were evaluated using an HP 4156A semiconductor parameter analyzer. Also, the structural characteristics and morphologies of the TiSi2 nanocrystals were observed using a Technai G2 F30 transmission electron microscope (TEM). 3.
Results and Discussion
Figure 1(b) shows the cross-sectional TEM images of the TiSi2 nanocrystal memory device with the SiO2 tunnel barrier. The TiSi2 nanocrystals are distributed between the 5 – 7-nm-thick tunnel barrier and the 30-nm-thick SiO2 control barrier. The TiSi2 nanocrystals were spherically shaped with diameters and an average density of about 2 – 5 nm and 1:5 1012 cm2 , respectively. Since the electrical performance of the NVM devices depends on the tunneling probability through tunnel barriers, the gate currents of the NON-engineered tunnel barriers were calculated. Figure 2 shows the simulation results of
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the gate current density–voltage (J–V) behavior as a function of the thickness of the SiO2 and/or the Si3 N4 tunnel barriers. The gate current density was calculated from the direct quantum tunneling model using a one-dimensional potential energy profile and quantized energy levels given by a self-consistent Schro¨dinger–Poisson solver.14) As a result, it is found that the gate field-sensitivity of the tunneling current is largely improved by stacking SiO2 and Si3 N4 layers owing to the barrier height modulation and effective barrier thickness modulation effects.15) The electron tunneling probability of the NON barrier increases under program/erase operations because the barrier height decreases with increasing applied gate bias, which results in the enhancement of program/erase speeds. Meanwhile, the
retention characteristics are improved because the increased tunnel barrier thickness caused by stacking NON dielectrics could effectively reduce the leakage current of the NVM devices. Figure 3 shows the ID –VG and the output current characteristics of the TiSi2 nanocrystal memory device with the NON tunnel barrier. When drain voltages were applied at 0.05 and 1.0 V, the on-current was about 105 A at a 1.0 V drain bias, and the on/off current ratio was estimated to be about 104 . Also, the subthreshold swing and drain-induced barrier lowering were 350 mV/dec and 63 mV/V, respectively. Additionally, the ID –VD behavior is shown in Fig. 3(b). The output drain current increased gradually as the gate voltage increased and was then saturated at about 20 mA at VG VT ¼ 2 V and VDS ¼ 3:0 V. Through these results, it was concluded that the fabricated TiSi2 nanocrystal memory device operated well as a transistor. The program/erase operations of the TiSi2 nanocrystal memory devices with the NON and SiO2 tunnel barriers are shown in Fig. 4. The threshold voltage shift of the nanocrystal memory device is strongly affected by the carrier charging into the nanocrystals. Therefore, the program/erase operations of the TiSi2 nanocrystal memory device can be measured using the threshold voltage shifts in the ID –VG curve. Also, when the gate voltage was swept from 14 to
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14 V for 500 ms to compare the program/erase operations between the NON and SiO2 tunnel barrier devices, the memory windows of the NON and SiO2 tunnel barrier devices were about 4.0 and 1.6 V, respectively. These results indicate that the program/erase operation of the NON tunnel barrier device has a good memory effect due to carrier charging and discharging into the TiSi2 nanocrystals. The program/erase speed characteristics as measured from the TiSi2 nanocrystal memory devices with the NON and SiO2 tunnel barriers are shown in Fig. 5. The threshold voltage shifts increased as the stress time increased. As shown in Fig. 5, the memory window of the NON tunnel barrier device was about 0.7 V when the program/erase operations were performed at +7 V/7 V for 100 ms. On the other hand, the memory window of the SiO2 tunnel barrier device was about 0.3 V during the program/erase operations at +13 V/13 V for 100 ms. The equivalent oxide thickness (EOT) of the SiO2 tunnel barrier (5 nm) is smaller than the NON tunnel barrier (5.2 nm), and the effective tunneling thickness of the NON tunnel barrier decreased with increasing stress time due to the electric field enhancement. As a result, the NON tunnel barrier device showed a better program/erase speed than the SiO2 tunnel barrier device.
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Fig. 6. (Color online) Charge retention characteristics of TiSi2 nanocrystal memory devices with NON and SiO2 tunnel barriers.
Figure 6 shows a comparison of the charge retention characteristics in the TiSi2 nanocrystal memory devices with the NON and SiO2 tunnel barriers. All the measurements were carried out at room temperature. The memory window of the NON tunnel barrier device decreased from 2.1 to 1.3 V after 103 s, when the program/erase operations were performed at +8 V/11 V for 500 ms. The memory window of the SiO2 tunnel barrier device decreased from 2.0 to 1 V after 103 s during program/erase operations at +10 V/ 16 V for 1 s. At the program retention stage, the charge loss rate of the SiO2 tunnel barrier device was faster than that of the NON tunnel barrier device. In this case, the charge carriers should tunnel through the NON tunnel barrier successively from the TiSi2 nanocrystals. This means that the physical thickness of the NON tunnel barrier (7 nm) was sufficient to prevent charge loss. At the initial step of the erase retention stage, the charge loss rate of the NON tunnel barrier device was faster than that of the SiO2 tunnel barrier device. However, after 102 s, the charge loss rate of the NON tunnel barrier device became very stable. The charge loss in the initial stage of the NON tunnel barrier device can be possibly attributed to the charges stored in the interface states between the TiSi2 nanocrystals and Si3 N4 or to charges trapped in the Si3 N4 layer.16,17) 4.
Conclusions
TiSi2 nanocrystal memory devices with a barrier-engineered multiple stacked tunnel layer were fabricated and their electrical properties were characterized. The threshold voltage shift of the NON tunnel barrier device was observed to be about 4.0 V at 500 ms when the applied program/ erase voltages were +14 V/14 V. The memory window of the NON tunnel barrier device was observed to be about 0.7 V at 100 ms at applied program/erase voltages of +7 V/ 7 V. Also, the memory window of the NON tunnel barrier device was maintained up to 1.3 V after 103 s. These results show that the NON tunnel barrier has better electrical properties than the SiO2 tunnel barrier in the TiSi2 nanocrystal memory device. Therefore, TiSi2 nanocrystal memory devices with a NON tunnel barrier can be feasibly applied to NVM devices and may possibly overcome the trade-off between program/erase speeds and charge retention characteristics.
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Acknowledgements
This work was supported by the National Program for 0.1 Terabit Non-Volatile Memory Device by the Ministry of Knowledge Economy and the Basic Science Research Program through the National Research Foundation of Korea funded by the Ministry of Education, Science and Technology (Contract No. R0A-2005-000-10079-0 and Quantum Photonic Science Research Center). 1) S. Tiwari, F. Rana, H. Hanafi, A. Hartstein, E. F. Crabbe, and K. Chan: Appl. Phys. Lett. 68 (1996) 1377. 2) D. U. Lee, M. S. Lee, J.-H. Kim, E. K. Kim, H.-M. Koo, W.-J. Cho, and W. M. Kim: Appl. Phys. Lett. 90 (2007) 093514. 3) T. H. Lee, D. U. Lee, S. P. Kim, and E. K. Kim: Jpn. J. Appl. Phys. 47 (2008) 4992. 4) D. U. Lee, T. H. Lee, E. K. Kim, J.-W. Shin, and W.-J. Cho: Appl. Phys. Lett. 95 (2009) 063501. 5) J. H. Kim, J. Y. Yang, J. S. Lee, and J. P. Hong: Appl. Phys. Lett. 92
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