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Charge-Trap Memory Device Fabricated by Oxidation of Si1 xGex Ya-Chin King, Member, IEEE, Tsu-Jae King, Member, IEEE, and Chenming Hu, Fellow, IEEE
Abstract—In this work, we describe a novel technique of fabricating germanium nanocrystal quasinonvolatile memory device. The device consists of a metal-oxide-semiconductor field-effect transistor (MOSFET) with Ge charge-traps embedded within the gate dielectric. The trap formation method provides for precise control of the thicknesses of the top (control) and bottom (tunneling) oxide layers which sandwich the charge-traps, via thermal oxidation. This memory device exhibits write/erase speed/voltage and retention time superior to previously reported nano-crystal or charge-trap memory devices. A detailed description of the novel process for fabricating the Ge charge-trap MOS memory is given, along with the resultant memory-cell performance characteristics. Index Terms—Charge-trap memory, Ge nano-crystal.
I. INTRODUCTION
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HE demands of more powerful portable electronics and embedded systems heighten the need for low-power high-density memory in the future. The state-of-art high-density semiconductor memories are DRAM and flash. DRAM cell allows fast write and erase, in the range of 100 ns or less [1]. However, its data retention time is limited by junction and transistor leakage to less than a few seconds [2]. As a result, frequent refresh is required, which increases the power consumption of the memory array even with no change in its data content. The need for large storage capacitor in every DRAM cell makes it impossible to form high-density memory cell without complex cell structure and/or new dielectric materials [3], [4]. Flash memory cells designed for ten years of data retention requiring the use of relatively thick tunnel oxide that greatly compromise both its write and erase speed and endurance [5], [6]. It is well known that oxide tunneling current increases rapidly as the oxide thickness is reduced to below 35 Å, where the direct tunneling current mechanism dominates. Oxide reliability (charge-to-breakdown) has been found to improve dramatically also, due to minimal oxide damage by direct tunneling [7], [8]. These attributes of the very thin oxide suggest the possibility of fast write/erase speed and high endurance for a memory cell. However, significant charge leakage due to direct tunneling current at quiescent gate voltage shortens the data-retention time dramatically; this makes floating gate memory device with a Manuscript received March 30, 1999; revised June 12, 2000. The review of this paper was arranged by Editor C. Y. Yang. Y.-C. King is with the Department of Electrical Engineering, National Tsing-Hua University, Hsinchu, Taiwan, R.O.C. T.-J. King and C. Hu are with the Department of Electrical Engineering and Computer Science, University of California, Berkeley, CA 94720 USA (e-mail:
[email protected]). Publisher Item Identifier S 0018-9383(01)02347-4.
very thin tunnel oxide unattractive. One way to increase the retention time is to replace the floating gate with a silicon nitride layer for charge trapping [13]. Recently, a single-transistor memory-cell structure with nano-crystal charge-storage sites embedded within the gate dielectric has been proposed and demonstrated [11]. By using electrically isolated charge-storage nodules in the oxide, charge leakage through localized oxide defects is greatly reduced; hence, a much thinner tunneling oxide (for faster write/erase speed) can be employed. The possibility of the charge-storage memory device which exceeds the performance limits of a conventional floating-gate device has attracted a great deal of interest and is spurring rapid progress in this area [9], [10]. Quasinonvolatile MOS memory devices employing silicon, germanium or tin nanocrystal charge-storage sites produced by ion implantation into the gate oxide have been demonstrated in recent studies [11], [12]. These nanocrystal memory devices fabricated by ion implantation exhibited superior data-retention characteristics than that of the conventional floating-gate devices. Limitations of the ion implantation technique place a lower limit on the gate oxide thickness. In addition, ion implantation may compromise the integrity of the oxides. In this work, we describe a new, novel technique for creating germanium charge-trap sites within the gate dielectric of a MOSFET. The control oxide, charge-trap sites, and the tunneling oxide are formed through a sequence of thermal at various temperatures. The resulting oxidation of memory device exhibits fast WRITE/ERASE speed, long data retention time and superior endurance with nondestructive read. The process of forming this memory cell is compatible to the typical CMOS process, therefore can be easily adapted in the fabrication of embedded circuits. II. PROCESS FLOW The schematic cross-section of a new charge-trap-based quasinonvolatile memory device is shown in Fig. 1. The single-transistor memory structure can be fabricated using conventional wafer-processing techniques. A novel method of forming the gate-dielectric stack (consisting of a upper layer of control oxide, a middle oxide layer with embedded germanium nano-crystals and a lower layer of tunneling oxide) is illustrated in Fig. 2. This technique provides excellent thickness control for the top and bottom oxide layers that sandwich is first the nano-crystals. A thin epitaxial layer of formed on the surface of a Si wafer by ion implantation and subsequent high-temperature wet oxidation, which causes the interface. The implanted Ge atoms to pile up at the
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Fig. 1. Cross section of the Ge nanocrystal memory device. The control and tunnel oxide layers were grown by thermal oxidation.
Ge segregates out of the growing oxide under these oxidation conditions [14]. After the high temperature oxide film is etched off, the control oxide layer is grown at 800 C in dry . Under these conditions, Ge is not incorporated into the oxide, and is grown. Next, a layer is grown at 650 thus C in a wet ambient [15] in order to incorporate the Ge into the gate dielectric stack. Next, the tunneling oxide is grown at . Finally a high temperature (900 C) anneal 800 C in dry step is employed to cause the Ge within the oxide to precipitate and form nanocrystals. A cross-sectional transmission electron micrograph of a gate-dielectric stack formed by this new technique is shown in Fig. 3. Ge nanocrystals of size ranging from 50 to 100 Å in diameter are seen in this sample, which was fabricated with a relatively high Ge implant dose. Memory devices were fabricated with lower Ge implant doses, in order to form smaller Ge nanocrystals that are more compatible with thin dielectric stacks. The size to the Ge nanocrystals in the fabricated devices is estimated to be less than 25 Å. A small interface, creating inamount of Ge remains at the terface traps and thereby degrading the transistor performance [16]. Nitrogen implantation followed by high-temperature annealing was employed to passivate the Ge. This significantly improved the transistor’s capacitance–voltage (C–V) and current–voltage (I–V) characteristics. III. MEMORY DEVICE CHARACTERISTICS The subthreshold characteristics of the Ge nanocrystal memory device are shown in Fig. 4. It is found that the , 100 transistor threshold voltage shifts 0.4 V after a is given by the ns-write pulse. The threshold-voltage shift, following expression:
where is the distance between the trapped charge and the gate is the areal density of trapped charge (residing electrode, and on the Ge nanocrystals) in the gate dielectric. Using Å, , the number of electrons trapped in the Ge . Due to the nanocrystals was estimated to be Coulomb blockade effect, only one electron can be trapped in
Fig. 2. Forming Ge nanocrystals in the gate oxide stack as charge storage nodes for memory device application.
each Ge nanocrystals. Hence, the size of the nanocrystal was estimated to be about 20 Å in diameter with center to center spacing of 50 Å. The programming characteristics of the nanocrystal memory device are shown in Fig. 5 for several write/erase voltages. saturates as the write time increases and also as the write voltage increases. This is because there is a finite number of the chargestorage sites provided by the Ge nanocrystals. The device shows symmetrical write and erase characteristics. The erase time of less than 50 ns is the fastest speed ever reported for a nanocrystal memory device. The endurance of the Ge nanocrystals memory device cell is write and erase cycles with 100 ns tested using
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 4, APRIL 2001
Fig. 5. Programming and erase time of the Ge nanocrystal memory with various write voltages. The overall dielectric thickness of this memory device is 6 nm. Fig. 3. High resolution TEM micrograph of the stack gate dielectric layer with embedded Ge nanocrystals.
Fig. 4.
Threshold voltage shift after a 4 V-100 ns write pulse.
Fig. 6. Endurance of the cell is tested with The transistor shows no degradation before
+4 V=04 V write and erase pulse. 1 2 10 W/E cycles.
pulse width. As Fig. 6 shows, endurance is found to be better write/erase cycles, with negligible degradation in tranthan sistor current-versus-voltage characteristics. The data-retention characteristics at both the room temperature and 85 C of the dewrite/erase cycles are shown in Fig. 7. Less than vice after 5% reduction in the threshold voltage window was observed s. This memory device has a data-retention longer than after one day at room temperature and about 1 h at 85 C. IV. DISTRIBUTION OF THE PROGRAMMED STATES In order to serve in a large-scale memory array, the distribution of the threshold voltages of the memory cells must be investigated. The threshold voltage variation in the erased or uncharged state can be controlled with the usual production disciplines. The threshold voltage variation in the programmed or charged state warrants additional studies due the inherited properties of the Ge nanocrystals formed by the proposed method. The threshold voltages across the wafer were measured both in the erased and the programmed states. For high-density memory application, the memory devices have to be scaled to deep submicron size. The variation in the number of electrons captured, i.e., the number of nanocrystals in the memory cell, has to be within a certain tolerance determined by the design of the sense
Fig. 7. Data retention characteristics at room temperature and 85 C after write/erase cycles.
10
amplifier. The threshold voltage difference between the programmed and erased states of 30 memory cells with sizes of , respectively, were measured and shown in the 100, 10, box plot in Fig. 8. It is found that the variation of the threshold voltage at the programmed states increases, as the size of the transistor becomes smaller. The histograms in Fig. 9 further examine the variation of the nanocrystals in these memory devices.
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flexibility in oxide thickness control and has produced devices with write speed/voltage and retention time superior to previous nanocrystal devices. This fast write/erase quasinonvolatile device is potentially useful in low power, high-density memory products. It is also a candidate for embedded memory application since its fabrication process is very compatible with logic CMOS processes. REFERENCES [1] K. Kim, C.-G. Hwang, and J. G. Lee, “DRAM technology perspective for gigabit era,” IEEE Trans. Electron Devices, vol. 45, pp. 598–608, Mar. 1998. [2] B. El-Kareh, G. B. Bronner, and S. E. Schuster, “The evolution of DRAM cell technology,” Solid State Technol., vol. 40, p. 89, May 1997. [3] T. Horikawa, A. Yuuki, T. Shibano, and T. Kawahara, “Novel stacked thin films,” capacitor technology for 1-Gbit DRAM’s with (Ba,Sr) Electron. Commun. Jpn., pt. Part 2 (Electronics), vol. 80, pp. 70–8, May 1997. [4] S. Crowder, S. Stiffler, P. Parries, and G. Bronner, “Trade-offs in the integration of high performance devices with trench capacitor DRAM,” in IEDM Tech. Dig., 1997, pp. 45–8. [5] P. Pavan, R. Bez, P. Olivo, and E. Zanoni, “Flash memory cells-an overview,” Proc. IEEE, vol. 85, no. 8, pp. 1248–71, Aug. 1997. [6] L. Baldi, A. Cascella, and B. Vajana, “A scalable single poly EEPROM cell for embedded memory applications,” Microelectron. J., vol. 28, pp. 657–61, Aug.-Sept. 1997. [7] R. Moazzami and C. Hu, “Stress-Induced Current in Thin Silicon Dioxide Film,” in IEDM Tech. Dig., 1992, p. 139. breakdown model for [8] K. F. Schuegraf and C. Hu, “Hole injection very low voltage lifetime extrapolation,” IEEE Trans. Electron Devices, vol. 41, pp. 761–7, May 1994. [9] T. Futatsugi, A. Nakajima, and H. Nakao, “Silicon single-electron memory using ultra-small floating gate,” Fujitsu Sci. Tech. J., vol. 34, pp. 142–52, 1998. [10] A. C. Rastogi, “Properties and device applications of semiconductor nanocrystals sequestered in insulator thin films,” Physics of Semiconductor Devices, vol. 1, p. 55, 1998. [11] H. I. Hanafi, S. Tiwari, and I. Khan, “Fast and long retention-time nanocrystal memory,” IEEE Trans. Electron Devices, vol. 43, pp. 1553–8, Sept. 1996. [12] A. Nakajima, T. Futatsugi, N. Horiguchi, and H. Nakao, “Single electron charging of Sn Nano-crystals in thin film formed by low energy ion implantation,” in IEDM Tech. Dig., 1997, pp. 159–162. [13] H. C. Wann and C. Hu, “High-endurance ultra-thin tunneling oxide in MONOS device structure for dynamic memory application,” IEEE Electron Device Lett., vol. 16, pp. 491–3, Nov. 1995. [14] P.-E. Hellberg, S.-L. Zhang, F. M. D’Heurle, and C. S. Petersson, “Oxidation of silicon-germanium alloys. I. An experimental study,” J. Appl. Phys., vol. 82, p. 5773, 1997. [15] M.-A. Nicolet and W.-S. Liu, “Oxidation of GeSi,” Microelectron. Eng., vol. 28, p. 185, 1995. [16] D. K. Nayak, J. S. Park, J. C. S. Woo, and K. L. Wang, “Interface proplayer,” J. Appl. Phys., erties of thin oxides grown on strained vol. 76, p. 982, 1994.
TiO
Fig. 8. Threshold voltage shift distribution for memory cells of different sizes.
SiO
SiO
1
Fig. 9. Smaller devices exhibit a wider V spread as a result of their higher susceptibility to the nonuniformity in the density and size of the nanocrystals.
Due the nonuniformity of the size and density of the germanium nanocrystals, the variation of the threshold voltage in the programmed states increases as the size the memory cell decreases. This results suggests that the uniformity of the size and density of the nanocrystals must be well controlled for application in high density and large-scale memory arrays.
V. CONCLUSION A novel technique of fabricating Ge nanocrystal quasinonvolatile memory devices has been developed. It has excellent
Ge Si
Ya-Chin King )S’92–M’99) was born in Taiwan, R.O.C. She received the B.S. degree in electrical engineering from National Taiwan University, Taipei, in 1992, and the M.S. and Ph.D. degrees in electrical engineering from the University of California, Berkeley, in 1994 and 1999, respectively. Her dissertation was on thin oxide technology and novel quasinonvolatile memory. She joined National Tsing-Hua University, Hsinchu, Taiwan, in August 1999 as an Assistant Professor. Her research topics include: thin gate dielectric, CMOS image sensor and nonvolatile memory design.
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Tsu-Jae King (S’89–M’91) was born in Ithaca, NY, in 1963. She received the B.S., M.S., and Ph.D. degrees in electrical engineering from Stanford University, Stanford, CA, in 1984, 1986, and 1994, respectively. At Stanford University, her research involved the seminal study of polycrystalline silicon-germanium films and their applications in metal-oxide-semiconductor technologies. She joined the Xerox Palo Alto Research Center (PARC) as a Member of Research Staff in 1992 to research and develop polycrystalline-silicon thin-film transistor technologies for high-performance flat-panel display and imaging applications. During her tenure with Xerox PARC, she served as a Consulting Assistant Professor of electrical engineering at Stanford University. In August 1996, she joined the faculty of the University of California, Berkeley, where she is now an Associate Professor of Electrical Engineering and Computer Sciences, with a Guest Faculty appointment at the Lawrence Berkeley National Laboratory, and the Director of the UC Berkeley Microfabrication Laboratory. Her research activities are presently in sub-100 nm Si devices and technology, and thin-film materials and devices for integrated microsystems and large-area electronics. She has authored or co-authored over 100 publications and holds four U.S. patents. Dr. King is a member of the Electrochemical Society, the Society for Information Display, and the Materials Research Society. She has served on committees for many technical conferences including the Device Research Conference, the International Conference on Solid State Devices and Materials, and the International Electron Devices Meeting, and is presently a member of the IEEE Electron Devices Society VLSI Technology and Circuits Technical Committee. Since 1999, she has served as an Editor for the IEEE ELECTRON DEVICE LETTERS. She received the Ross M. Tucker AIME Electronics Materials Award for her work at Stanford University.
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 4, APRIL 2001
Chenming Hu (S’71–M’76–SM’83–F’90) received the B.S. degree from the National Taiwan University, Taipei, Taiwan, R.O.C., and the M.S. and Ph.D. degrees in electrical engineering from the University of California, Berkeley. He is Chancellor’s Professor of electrical engineering and computer sciences at UC Berkeley. He was an Assistant Professor at the Massachusetts Institute of Technology, Cambridge, before joining UC Berkeley. He is the board chairman of BTA Technology, Inc. His present research areas include microelectronic devices, thin dielectrics, circuit reliability simulation, and nonvolatile memories. He has authored or co-authored four books and over 600 research papers and supervised 60 doctoral students. Dr. Hu is a member of the U.S. National Academy of Engineering and a Life Honorary Professor of the Chinese Academy of Science. In 1991, he received the Excellence in Design Award from Design News and the inaugural Semiconductor Research Corporation Technical Excellence Award for leading the research of IC reliability simulator, BERT. He received the SRC Outstanding Inventor Award in 1993 and 1994. He leads the development of the MOSFET model BSIM3v3 that has been chosen as the first industry standard model for IC simulation by the Electronics Industry Alliance Compact Model Council and given an R&D 100 Award in 1996 as one of the 100 most technologically significant new products of the year. The IEEE awarded him the 1997 Jack A. Morton Award for his contributions to the physics and modeling of MOSFET reliability. Also in 1997, he received UC Berkeley’s highest honor for teaching – the Distinguished Teaching Award. In 1998, he received the Monie A. Ferst Award of Sigma Xi for encouragement of research through education. He received the Pan Wen Yuan Foundation Award for outstanding research in electronics in 1999.
