Electron Devices, IEEE Transactions on - Universidad de Granada

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 44, NO. 9, SEPTEMBER 1997

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Study of the Effects of a Stepped Doping Profile in Short-Channel MOSFET’s J. A. López-Villanueva, Member, IEEE, F. Gámiz, Member, IEEE, J. B. Roldán, Yassir Ghailan, J. E. Carceller, Member, IEEE, and Pedro Cartujo, Member, IEEE

Abstract— The performance of a stepped doping profile for improving the short-channel behavior of a submicrometer MOSFET has been analyzed in detail by using a quasi-two-dimensional (quasi-2-D) MOSFET simulator including inversion-layer quantization coupled with a one-electron Monte Carlo simulation. Several second-order effects, such as mobility degradation both by bulk-impurity and interface traps, carrier-velocity saturation, and channel-length modulation, have been included in the simulator. Very good agreement between experimental and simulated results are obtained for short-channel transistors. It has been shown that including a low-doped zone of convenient thickness next to the interface over a high-doping substrate improves both the electron mobility and the threshold voltage of the device, while avoiding short-channel effects. The use of simulation has allowed us to study certain kinds of devices without needing to make them.

I. INTRODUCTION

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URING the last few years, different implementations of MOSFET’s with gate lengths under 0.1 m have been reported [1]–[4]. Systematic investigations on the feasibility of devices with m have also been carried out [5]–[6]. These studies concluded that a new scaling method, different from Dennard’s [7], is necessary to obtain such gate lengths. Short-channel effects are usually controlled by increasing the channel-doping concentration, thus suppressing the spread of source and drain depletion layers. Therefore, as the channel length is scaled to 0.1 m and below, the doping concentration must be raised to values of cm . Such high bulk-impurity concentrations lead to an increase of threshold voltage and to an electron mobility decrease, which strongly degrades the electric properties of the device [8]–[10]. The threshold voltage can be reduced by appropriately decreasing the oxide thickness . Nevertheless, the limit for ˚ can be gate-oxide thickness imposed by direct tunneling (30 A) easily reached with the use of such high-doping concentrations. This makes the use of a higher doping than cm [6] unsuitable, thus imposing a low limitation to the threshold voltage. An alternative could be the use of insulator material with a higher permittivity than SiO , which would allow a thicker gate insulator. However, the use of such a dielectric would result in the loss of the advantages of the Si-SiO system, in addition to having a poor quality interface. Manuscript received October 26, 1996. The review of this paper was arranged by Editor B. Ricco. The authors are with the Departamento de Electrónica y Tecnolog´ıa de Computadores, Facultad de Ciencias, Universidad de Granada, 18071 Granada, Spain. Publisher Item Identifier S 0018-9383(97)06125-X.

On the other hand, the increase in bulk-impurity concentration involves a serious degradation of carrier mobility. This mobility reduction occurs in two ways: 1) the reduction of screening by mobile carriers for a given value of the effective electric field, and 2) an increase of Coulomb scattering due to the increase of the number of charged centers in the bulk [11]. To solve these problems, the use of nonuniform doping concentrations has recently been suggested: boron implant [10], indium-channel implant [12], silicon-epitaxial growth on heavily doped substrates [4], and delta-doped MOSFET’s [13]. As the scattering of electrons by charged centers quickly decreases when the charges are kept away from the interface [14], Coulomb scattering by bulk impurities could be drastically reduced by placing the bulk charges far enough away. In addition, a reduction of threshold voltage would also be provided. Nevertheless, the farther from the interface the charges are, the wider the depletion region, and thus, the stronger the short-channel effects. Therefore, according to the above, a consent solution is necessary. Shahidi et al. [12] suggested the use of an indium-channel implant for improved short-channel behavior of submicrometer NMOSFET’s. Such a doping profile provides low-channel doping and a high-doping concentration just below the inversion zone, which improves short-channel behavior of the device while decreasing the threshold voltage and raising carrier mobility. Aoki et al. [4] proposed another way of obtaining this effect through the use of a low-doped ultrathin epitaxial layer over a heavily doped substrate. With this stepped doping profile, the following two conditions can be fulfilled. On one hand, the depletion region width would be limited if the thickness of the low-doped zone is small enough (thus avoiding punchthrough). On the other hand, electron scattering by bulk impurities would be drastically reduced if the lowdoping zone thickness is thick enough. In addition, the lowdoped zone would provide a reduction in threshold voltage, which is essential in order to realize low-power CMOS. It is therefore very interesting to analyze in detail the effect of the low-doping-region width on the electron mobility and on the I–V characteristics. Many works have already been carried out along these lines, and thus this channel-doping profile has been the object of several experimental studies in recent years. Fiegna et al. [5] have studied the use of such a doping profile on very nm). They compared a short-channel MOSFET’s ( MOSFET with an epitaxial layer over a high substrate to a uniformly doped MOS and to different SOI-MOSFET’s, and

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found better behavior of the epitaxial MOSFET versus the other structures. The effect of an epitaxial channel on the threshold voltage has also been extensively studied by Andoh et al. [15]. These researchers showed by two-dimensional (2-D) simulation that an epitaxial channel is effective at reducing without increasing short-channel effects. In this paper, we have studied the influence of such a stepped doping profile on the electron mobility and the appropriate thickness of the epitaxial layer by simulation. Then, the I–V characteristics of short-channel devices were simulated by using a quasi-two-dimensional (quasi-2-D) Poisson–Schroedinger solver. We will show that a stepped doping profile, with the appropriate choice of the low-doped zone thickness, enhances the electron mobility and reduces the threshold voltage while maintaining good behavior versus short-channel effects. It is worth mentioning that ohmic mobility has been used here as the main magnitude to appreciate the advantages of the low-doped layer. Velocity overshoot, which is known to produce transconductance increase for channel lengths under 0.15 m, is not addressed here. Details of the simulation and results are provided in the sections below. Finally, some conclusions are drawn. II. DEVICE SIMULATION It is well known that when the channel dimensions in a MOSFET are reduced, 2-D and three-dimensional (3-D) effects become important. In addition, the classical approximation to electron behavior in the inversion layer is no longer valid, making a quantum study necessary. In accordance with these points, a physically based submicrometer MOSFET simulator should self-consistently solve the 2-D Poisson, Schroedinger, and drift-diffusion equations in the entire structure. The inversion layer has to be treated as a 2-D electron gas (2-DEG) contained in energy subbands. The minima of these subbands and the envelope function in each of them is given by the solution of the Schroedinger equation, but for this solution to be accurate, a very high mesh density has to be used near the interface. This makes the calculation very expensive in computation time and storage. Due to the above drawbacks, we have developed a simpler submicrometer MOSFET simulator which accurately reproduces the experimental behavior of very short (and long) channel MOSFET’s, and does not require high computational time nor complex equipment. As the inversion layer is treated as a 2-DEG with a transverse extension given by the envelope functions, a suitable description consists in describing the channel as a sheet layer of charge located inside the semiconductor bulk at a distance from the silicon-oxide interface. is the mean transverse position of the electron distribution [16]. The current in the channel is obtained by adding drift and diffusion contributions. If the voltage drop across the channel is very small, the following expression for the drain current is obtained [16]

(1)

where is the electrostatic potential in ; is the density of electrons in the channel extremes; is the average density of electrons in the channel; and the thermal voltage. The electron mobility depends on both the longitudinal and transverse electric fields. The effect of the transverse electric field is obtained by calculating the electron mobility by Monte Carlo simulation [17]–[19]. The effect of the longitudinal electric field is included in the simulation by the expression (2)

where is the low-field or ohmic mobility, which includes the dependence of the transverse electric field, and is the saturation electron velocity. has been obtained using a Monte Carlo simulation [20] (3) One advantage of (1), in addition to the use of an analytical approximation to the drift-diffusion equation, is that it requires only the one-dimensional (1-D) solution of the Poisson and Schroedinger equations along two lines perpendicular to the interface, right at the channel extremes. This numerical solution is necessary in order to obtain accurate values for and in both extremes, considering the actual doping profile in the silicon bulk and the actual pseudofermi-level separation as determined by the external applied voltage. Nevertheless, (1) has significant drawbacks. 1) the requirement of a very slow potential variation in the channel, which makes this procedure useless for almost all the operation conditions of a short-channel MOSFET; and 2) it does not include short-channel effects due to the depletion charge near the source and drain, which must be added a posteriori. The 1-D approximation is appropriate as far as the Schroedinger solution is concerned, since the length scale of interest in this case, the de Broglie wavelength, can actually be short for electrons in an inverted channel. As far as the Poisson equation is concerned, however, the Debye length can be quite long, and the longitudinal field can vary significantly. As a consequence, the 2-D Poisson equation solution could be required. To solve the 2-D problem, we have adopted a procedure similar to the idea proposed by Tsividis [21] to expand the application range of the quasistatic model, which is briefly described below. A. Starting Point The transistor is divided into a series of subtransistors, with its own imaginary source and drain points (as shown in Fig. 1), of very short length to make the voltage drop in each of them so small that (1) is applicable. In such a division, the following two conditions must be fulfilled: , , where and are the length and the

´ LOPEZ-VILLANUEVA et al.: STUDY OF THE EFFECTS OF A STEPPED DOPING PROFILE

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Fig. 1. Division of a MOS transistor in several subchannels.

drain-to-source voltage of the th subchannel. are fixed are by us as very small (and are therefore known), while initially unknown and are determined by the following iterative procedure. i) Starting from fixed values for the external biases, (voltage between drain and source), (voltage be(voltage between source tween gate and source), and between the different and substrate), the division of subchannels is carried out. To do so, we have assumed mV. According to this division, the difthat ference between the pseudo-fermi levels at the extremes of each subchannel is established. The 1-D Poisson and Schroedinger equations are then selfconsistently solved in the imaginary extremes of each subchannel taking into account the actual doping profile and the actual pseudo-fermi-level separation, and evaluating in each of these points the inversion and depletion charge, the , etc. electrostatic potential in the channel of the ii) An arbitrary current level MOSFET is assumed. This current level will also be the channel current in all the subchannels, and the length of each of them, , is obtained by applying the modified charge-sheet model given in (1), taking into account the results obtained by self-consistently solving the Poisson and Schroedinger equations in the extremes of each subtransistor. iii) The total channel length, , is compared with the sum of channel lengths, , of each subtransistor into which the MOSFET is divided. If the two magnitudes do not coincide, the current level is modified, and steps , within a ii) and iii) are repeated until convergence criterium. When the channel is saturated, and are substituted by and , is obtained from the difference respectively. between the pseudofermi levels for holes and electrons is reached in the drain end of when is evaluated from the solution of the 1the channel. D Poisson equation in the depletion region established between the drain and the channel point where pinchoff occurs [22]. This procedure allows us to obtain, in addition to the drain current, a first approximation to . the potential distribution along the channel, The use of an accurate expression for the low-field mobility and its dependencies with the transverse-electric field, the longitudinal electric field and the temperature, is crucial for

reproducing experimental results with accuracy. Furthermore, since the transverse-electric-field profile varies along the channel, this variation must be taken into account when the mobility in each subchannel is considered. In this work, we have used accurate results of mobility obtained by one-electron Monte Carlo simulation, taking into account the phonon and surfaceroughness scattering and the Coulomb scattering both from the doping impurities and the oxide and interface charges [17]–[19]. B. Quasi-2-D Solution The potential distribution resulting from the previous step is used as the starting point to iteratively solve the 2-D Poisson equation in the whole structure (4) where is the perpendicular and the parallel coordinates in the channel. An adaptive gride has been set in the whole structure. The 2-D problem considered in (4) has been broken down into 1-D problems (5) where (6) being the solution obtained in Section II-A, and is a grid column in the channel. With this effective-charge density, , we can use the procedure detailed in item i) of Section II-A to solve the Poisson and Schroedinger equations. We have thus been able to transform a 2-D complex problem into several much simpler 1-D problems. Once the 2-D Poisson equation is solved with this approach, the drain current and the lengths of each subchannel are calculated again by the procedure described in Section II-A and the solution of (4) is repeated until a convergence criterium is reached. In this way, the effect of the depletion charge near the source and drain, that reduces the substrate charge controlled by the gate voltage. Nevertheless, we have proved that the correction to the drain current obtained by the 2-D approach over the results obtained in Section II-A is not very important if the substrate doping is high enough (as actually occurs, p.e. cm

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Fig. 2. Experimental (solid lines) and simulated (solid squares) drain current versus drain-source voltage, for VGS = 2; 2:5; and 3 V. Also shown is the drain current obtained ignoring quantum effects. (L = 0:25 m, W = 10 ˚ NA = 4 1017 cm03 , VSB = 0 V). m, tox = 56 A,

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and m), but the corrections are significant when low-doped substrates are used. A comment is necessary here. In our simulation, drain current is evaluated using (1) instead of explicitly solving the continuity equation for electrons. This fact, although greatly simplifies the algebra, also introduces some limitations. One of these limitations is that the simulator can not account for the subthreshold leakage current due to the junction punchtrough in the subchannel region away from the interface, where the control of the distribution of electrostatic potential is not effective. The quasi-2-D procedure presented above allows us to reproduce experimental results with accuracy. Fig. 2 shows experimental I–V curves obtained for an N-MOS transistor ˚ and with m, m, A, cm (solid lines) [23]. The calculated data are also shown in squares. As can be seen, the simulated results agree very well with the experimental data in the whole and bias for the transistor. Similar results have been obtained for all the simulations we have faced. The results obtained neglecting quantization are also shown in Fig. 2 (dashed line). As can be observed, in such a case simulated and experimental curves do not coincide, and therefore it is absolutely necessary to solve the Schroedinger equation and take into account the quantization effects to reproduce the experimental behavior of short-channel devices. III. STEPPED DOPING PROFILE The simulator developed in Section II, coupled with a oneparticle Monte Carlo simulation, has been used to study the effect that a low-doped epitaxial layer grown on a high-doped substrate has, first, on the electron mobility and second on the electric characteristics of submicrometer devices. Fig. 3 shows the depletion region width in the center of the channel, , for a stepped doping profile as a function of the thickness of the low-doped zone, . The drain and source junction depths were assumed to be 0.03 m. has been obtained by self-consistently solving the Poisson and Schroedinger equations by the above procedure in a

Fig. 3. Depletion-region width, Wdep , for a stepped doping profile (inset) with Nlow = 1 1014 cm03 and Nhigh = 1 1018 cm03 , as a function of the thickness of the low-doped zone next to the interface (xi ).

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Fig. 4. Electron mobility versus the transverse-effective field for the stepped ˚ (3) doping profile in Fig. 3 with different values of xi : (1) ; (2) 300 A; ˚ and (4) 0 A. ˚ 100 A;

1

0.1 m-MOSFET, and then evaluating the expression (7) being the charge density in the semiconductor (ionized impurities and holes and electrons), the surface potential, and the coordinate in the direction perpendicular to the interface. remains fixed until As can be seen in Fig. 3, ˚ and then increases concomitantly with . Therefore, if we A, ˚ the depletionuse a stepped doping profile with A, region width will remain as small as in the case of a high uniform-doping concentration, thus blocking the spread of source/drain depletion layers. However, the electron mobility will greatly increase in the first case with regard to the second one. To illustrate this point, Fig. 4 shows electron mobility versus the transverse-effective field for the stepped doping profile of Fig. 3 with different values of . Mobility curves were evaluated by a one-electron Monte Carlo simulation


(a)

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(b)

˚ with a channel length of L = 0:1 m, channel width W = 1 m, and a stepped Fig. 5. (a) Simulated IDS -VGS curves for a MOSFET (tox = 50 A) ˚ (dashed line), and with a uniform bulk-doping concentration doping profile (Nlow = 1 1014 cm03 , Nhigh = 1 1018 cm03 ) with xi = 100 A ˚ (solid line). The curves correspond to VDS = 50 mV. (b) Electron mobility versus VGS xi = 0 A, VT for a stepped doping profile in Fig. 3 with ˚ and (solid line) 0 A. ˚ different values of xi : (dashed line) 100 A,

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detailed elsewhere [17]–[19], taking into account the actual doping profile both to solve the Poisson and Schroedinger equations, and to evaluate Coulomb scattering due to the doping impurities. A pronounced enhancement in the electron ˚ thick lowmobility can be observed when only a 300-A doped zone is added. Nevertheless, this mobility enhancement is quickly lost as the low-doped zone thickness decreases. The improvement of the carrier mobility with increasing the thickness of the low-doped zone is only obtained for lowtransverse electric field. Therefore, this indicates that the improvement of the mobility would be reduced for high gate voltages. Nevertheless, Fig. 5(b) shows electron mobility Curves (3) and (4) of Fig. 4 but versus instead of the transverse effective field, as done in Fig. 4. It can be seen that the separation of the mobility curves is still significant even at V, and therefore an increase of the drain current due to the low-doped zone will be expected at these gate voltages, as shown in Fig. 5(a). IV. SIMULATED I–V CURVES Other drawbacks inevitably related to the increase of substrate-impurity concentration is the increase in threshold voltage, which limits the low-voltage operation of the submicrometer devices. The stepped doping profile proposed above, also overcomes this disadvantage [15]. So, the threshold voltage for a MOSFET with a substrate doping concentration of cm , ( m, m, ˚ is reduced in V when a lowA) ˚ thick zone with a doping concentration of doped 300-A cm is added next to the interface [15]. The higher mobility and the lower threshold voltage provided by the low-doped zone near the interface greatly improve the electric behavior of submicrometer devices. Fig. 6 shows ˚ with simulated curves for a MOSFET ( A) a channel length of m, channel width m, ˚ (solid squares), A and a stepped doping profile with ˚ (dashed line), and a stepped doping profile with A ˚ (solid with a uniform bulk-doping concentration, A,

0

˚ with a Fig. 6. Simulated IDS -VDS curves for a MOSFET (tox = 50 A) channel length of L = 0:1 m, channel width W = 1 m, and a stepped doping profile (Nlow = 1 1014 cm03 ; Nhigh = 1 1018 cm03 ) with xi = 300 A˚ (solid squares), xi = 100 A˚ (dashed line), and with a uniform ˚ (solid line). The curves correspond to bulk-doping concentration xi = 0 A, VGS VT = 1:5 and 2 V.

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0

line) for a fixed value of , being the threshold voltage. Taking is done to illustrate the actual effect of the mobility increase on the I–V characteristics. To calculate these curves, the MOSFET simulator described in Section II and the low-field electron mobility of Fig. 4 have been used. As can be seen in the Fig. 4, the use of a stepped doping ˚ leads to a significant improvement in profile with A the electric characteristics of the device. We can also observed that an increase of the slope of the versus is produced with increasing the thickness of the lowdoped zone. This is due to a greater encroachment of the drain junction space charge layer into the channel at high applied drain voltages which decreases the electrical channel length when the low-doped zone thickness is increased. Therefore, some increase of short channel effects is the price we have to pay for the increase in the drain current and the reduction in threshold voltage. Another important short channel effect

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(a)

(b)

Fig. 7. (a) Mobility curves for the situations contemplated in Fig. 4 but with a typical interface-charge concentration of Nit = 4 1010 cm02 . (b) Simulated IDS -VDS curves for the same device as in Fig. 6, but with a typical interface-charge concentration of Nit = 4 1010 cm02 .

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that appears when dimensions are reduced is the subthreshold leakage due to junction punch-through in the subchannel region. As we said before, this effect cannot be taken into account in our simulator. Nevertheless, Aoki et al. [3] and Fiegna et al. [5] showed fairly good subthreshold behavior of these devices. We should note that in Figs. 4 and 6 only one of the negative effects produced by the increase in the bulk-doping concentration is considered: the growth of Coulomb scattering due to the increase of the bulk charge. However, the reduction of the screening by mobile carriers is still important, so the effect of the charge trapped in the oxide or right at the interface will play an important role that must be taken into account. Fig. 7(a) shows mobility curves for the situations contemplated in Fig. 4 but with a typical interface-charge concentration of cm . Fig. 7(b) shows the correction produced by the interface charge on the output curves of the transistor in Fig. 6. In this case the improvement produced by the lowdoped region is a little less important. Finally, we would like to emphasize that although the true advantages of using a low-doped-epitaxial layer on a heavily doped substrate are known, we have obtained them by simulation and therefore the use of simulation has allowed the study of a certain kind of devices without the necessity of manufacturing them and has also allowed us to understand a little more about the physics involved. V. CONCLUSION We have developed a quasi-2-D short-channel MOSFET simulator including inversion-layer quantization. The electron mobility in the channel has been obtained by one-electron Monte Carlo simulation that takes care of the actual doping profile, which has been shown to play a very important role. The effect of the longitudinal electric field on the electron mobility has been obtained by using an analytical expression, also obtained in a Monte Carlo simulation. Several effects, such as mobility degradation both by bulk impurities and interface traps, have also been included in the model. Very good agreement between empirical and simulated results have been observed for short-channel transistors. This simulator,

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coupled with a one-electron Monte Carlo simulation, has been used to analyze in detail the use of a stepped doping profile for improving the behavior of submicrometer MOSFET’s. It has been shown by simulation that by adding a low-doped zone of convenient thickness next to the interface over a highdoping substrate, both the electron mobility and the threshold voltage of the device are improved while avoiding shortchannel effects. The effect of the interface and oxide charge has also been analyzed. REFERENCES [1] G. A. Sai-Halasz, M. R. Wordeman, D. P. Kern, S. Rishton, and E. Ganin, “High transconductance and velocity overshoot in NMOS devices at the 0.1 m gate-length level,” IEEE Electron Device Lett., vol. 9, p. 464, 1988. [2] T. Hashimoto, Y. Sudoh, H. Kurino, A. Narai, S. Yokoyama, Y. Horiike, and M. Koyanagi, “3 V operation of 70 nm gate length MOSFET with double punchthrough stopped structure,” in Ext. Abst. Int. Conf. Solid State Devices Materials, Aug. 1992, pp. 490–492. [3] M. Aoki, T. Ishii, T. Yoshimura, Y. Kiyota, S. Iijima, T. Yamanaka, T. Kure, K. Ohyu, T. Nishida, S. Okasaki, K. Seki, and K. Shimohigashi, “Design and performance of 0.1 m CMOS devices using low-impuritychannel transistors (LICT),” IEEE Electron Device Lett., vol. 13, pp. 50–52, Jan. 1992. , “0.1 m CMOS devices using low-impurity-channel transistors [4] (LICT),” in IEDM-90, 1990, pp. 939–941. [5] C. Fiegna, H. Iwai, T. Wada, T. Saito, E. Sangiorgi, and B. Ricco, “A new scaling methodology for the 0.1–0.025 m MOSFET,” in 1993 Symp. VLSI Tech., p. 33. [6] M. Ono, M. Saito, T. Yoshitomi, C. Fiegna, T. Ohguro, and H. Iwai, “A 40 nm gate length n-MOSFET,” IEEE Trans. Electron Devices, vol. 42, pp. 1822–1830, 1995. [7] R. H. Dennard, F. H. Gaensslen, H. N. Yu, V. L. Rideout, E. Bassous, and A. R. Leblanc, “Design of ion-implanted MOSFET’s with very small physical dimensions,” IEEE J. Solid-State Circuits, vol. SC-9, pp. 256–268, 1974. [8] M. J. Van Dort, P. H. Woerlee, A. J. Walker, A. H. Casper, and H. Lifka, “Influence of high substrate doping levels on the threshold voltage and the mobility of deep-submicrometer MOSFET’s,” IEEE Trans. Electron Devices, vol. 39, pp. 932–938, 1992. [9] J. Tanaka, T. Toyabe, S. Ihara, S. Kimura, H. Noda, and K. Itoh, “Simulation of sub-0.1 m MOSFET’s with completely suppressed short channel effect,” IEEE Electron Device Lett., vol. 14, no. 396, 1993. [10] G. Shahidi, B. Davari, T. Bucelot, P. A. Ronsheim, P. J. Coane, S. Pollack, C. R. Blair, B. Clark, and H. H. Hansen, “Indium channel implant for improved short channel behavior of submicrometer NMOSFET’s,” IEEE Electron Device Lett., vol. 14, pp. 409–411, Aug. 1993. [11] F. Gamiz, J. Banqueri, J. E. Carceller, and J. A. Lopez-Villanueva, “Effects of bulk impurity and interface-charge on the electron mobility in MOSFET’s,” Solid-State Electron., vol. 38, pp. 611–614, 1995.


[12] G. G. Shahidi, D. A. Antoniadis, and H. I. Smith, “Electron velocity overshoot at room and liquid-nitrogen temperatures in silicon inversion layers,” IEEE Electron Device Lett., vol. 9, p. 94, 1988. [13] A. C. G. Wood, A. G. O’Neill, P. Phillips, F. G. Bisnas, T. E. Whall, and E. C. parker, “Transconductance and mobility of Si Delta MOSFET’s,” IEEE Trans. Electron Devices, vol. 40, p. 157, Jan. 1993. [14] F. Gamiz, J. A. Lopez-Villanueva, J. Banqueri, J. E. Carceller, and P. Cartujo, “Universality of electron mobility curves in MOSFETs: A Monte Carlo study,” IEEE Trans. Electron. Devices, vol. 42, p. 258, 1995. [15] T. Andoh, A. Furukawa, and T. Kunio, “Design methodology for lowvoltage MOSFET’s,” in IEDM-94, 1994, p. 79. [16] J. Banqueri, J. A. Lopez-Villanueva, F. Gamiz, J. E. Carceller, E. LoraTamayo, and M. Lozano, “A procedure for the determination of the effective mobility in a NMOSFET in the moderate inversion region,” Solid State Electron., vol. 39, pp. 875–883, 1996. [17] F. Gamiz, J. A. Lopez-Villanueva, J. A. Jimenez-Tejada, and A. Palma, “A comprehensive model for Coulomb scattering in inversion layers,” J. Appl. Phys., vol. 75, p. 924, 1994. [18] F. Gamiz, I. Melchor, A. Palma, P. Cartujo, and J. A. Lopez-Villanueva, “Effects of the oxide-charge space correlation on electron mobility in inversion layers,” Semicond. Sci. Technol., vol. 9, pp. 1102–1107, 1994. [19] F. Gamiz, J. A. Lopez-Villanueva, J. Banqueri, Y. Ghailan, and J. E. Carceller, “Oxide charge space correlation in inversion layers II. Threedimensional oxide charge distribution,” Semicond. Sci. Technol., vol. 10, pp. 592–600, 1994. [20] J. B. Roldan, F. Gamiz, J. A. Lopez-Villanueva, J. E. Carceller, and P. Cartujo, “Dependence of the electron mobility on the longitudinal electric field in MOSFET’s,” Semicond. Sci. Technol., vol. 12, p. 321, 1997. [21] Y. P. Tsividis, Operation and Modeling of the MOS Transistor. New York: McGraw-Hill, 1987. [22] M. Shur, Physics of Semiconductor Devices. Englewood Cliffs, NJ: Prentice-Hall, 1990. [23] J. E. Chung, M. Jeng, J. E. Moon, P. K. Ko, and C. Hu, “Performance and reliability design issues for deep-submicrometer MOSFET’s,” IEEE Trans. Electron Devices, vol. 38, pp. 545–554, 1991.

J. A. López-Villanueva (M’90), for a photograph and biography, see p. 846 of the May 1997 issue of this TRANSACTIONS.

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F. Gámiz (M’94), for a photograph and biography, see p. 846 of the May 1997 issue of this TRANSACTIONS.

J. B. Roldán, for a photograph and biography, see p. 846 of the May 1997 issue of this TRANSACTIONS.

Yassir Ghailan was born in Tetouan, Morocco, in 1969. He received the degree in physics in 1992 and the D.E.S degree in 1996, both from the University of Tetouan. Since 1992, he has been pursuing the Ph.D. degree in electronics at the University of Granada, Spain. His current research interests include simulation of semiconductor devices by means of the Monte Carlo method, with special application to MOSFET and MODFET.

J. E. Carceller (M’83), for a photograph and biography, see p. 846 of the May 1997 issue of this TRANSACTIONS.

Pedro Cartujo (M’82) was born in La Bañeza, León, Spain, in 1936. He graduated in physics in 1961, and received the Ph.D. degree in 1969 with a thesis on automatic control. He has been a Researcher at the Superior Council for the Scientific Research, Spain, and Professor at the Universities of Valladolid, Spain, Barcelona, Spain, and Granada, Spain. He is now Head of the Department of Electronics and Computer Technology at the University of Granada.