Energy-efficient hybrid capacitor switching scheme for SAR ADC Liangbo Xie, Guangjun Wen, Jiaxin Liu and Yao Wang A novel low-energy hybrid capacitor switching scheme for a lowpower successive approximation register (SAR) analogue-to-digital converter (ADC) is presented. The proposed switching scheme combines a new switch method and the monotonic technique. The new switch method can achieve no switching energy consumption in the first three comparison cycles. Furthermore, a low-energy monotonic procedure is performed for the rest of the comparisons. The average switching energy is reduced by 98.83% compared with the conventional architecture, resulting in the most energy-efficient switching scheme among the existing switching techniques. Besides the significant energy saving, the proposed switching scheme also achieves a 75% reduction of the capacitors over the conventional scheme.
technique, as shown in Fig. 1b. Accordingly, the proposed switching scheme achieves one more no energy consumption step than the other switching schemes in [3–5]. Hence, the overall switching energy can be significantly reduced. Then, the low-energy monotonic capacitor switching procedure is performed in the following operations [4]. Vcm
2C
Vip Vin
2C
+ –
C C Vcm Vcm
2C
C C Vcm Vcm
0
V2 V0 2C
C Vcm
V1
E=0 C
2C
C Vcm
2C
Vref
C
Vcm
Vref
Vref
E=0
Vcm E = 1/4 CVref2
2C
C
C
V1
E=0 2C
C Vcm
C
2C
a V0
C
Vcm
Vcm
2C
C
C Vcm Vcm V3
E = 1/4 CVref2 2C
b
Vref
C
A
0
B
0 0
C Vcm
C
D
A Vcm
C
Vcm
C
2C
+
Vip>Vin + 3/4Vref ? 2C
2C C C Vip>Vin + 7/8Vref ?
1/16Vref2
Vcm Vcm C Vip>Vin + 5/8Vref ? C C 2C Vref Vcm Vref
–
C C Vref Vref Vref
C C Vref Vref Vref
2C
3/16Vref2
C
Vcm
B Vcm 2C
C
Vcm
2C C C Vip>Vin + 3/8Vref ? C C 2C Vcm Vcm Vcm
1/16Vref2
C
Vip>Vin + 1/4Vref ? C C Vcm Vcm Vcm
2C
Vcm Vcm 2C C C Vip>Vin + 1/8Vref ?
3/16Vref2
2C
Vcm Vcm Vcm C C
3/16Vref2
2C
C
Vcm
C
C Vcm
Vip>Vin – 1/4Vref ? 2C
C
Vcm Vcm 2C C C Vip>Vin – 1/8Vref ?
C 2C
C Vcm
C Vcm Vcm
Vcm
Vcm Vcm Vcm 2C C C Vip>Vin – 3/8Vref ? C C 2C
1/16Vref2
Vcm Vref Vcm Vref 2C C C Vip>Vin – 5/8Vref ?
D Vref Vref 2C
C
Vref
3/16Vref2
C C Vcm Vcm Vref Vref Vref 2C C C Vip>Vin – 7/8Vref ? 2C
C
2C
C C Vcm Vcm
1/16Vref2
2C
C
C Vcm
Fig. 2 Hybrid switching scheme of 4 bit ADC
V2
C Vcm
Vcm
Vcm Vref
2C C C Vip>Vin – 1/2Vref ?
Vref V3 C
Vref
0
Vcm
C Vref
C Vref
Vcm
Vcm
Vip>Vin – 3/4Vref ?
E=0
C
2C
0
2C
2C
Introduction: In successive approximation register (SAR) analogue-todigital converters (ADCs), the digital-to-analogue converter (DAC) capacitor array dominates the overall power consumption compared with a comparator and a digital control circuit. Recently, several techniques have been developed to improve the power efficiency of DAC capacitor arrays [1–5]. The monotonic switching technique in [1] achieves an 81.26% reduction in switching energy compared with the conventional SAR ADC. The Vcm-based switching technique in [2] reduces the switching energy by 87.54% compared with the conventional technique, whereas a 96.89% reduction is achieved by the new tri-level switching scheme in [3]. The Vcm-based monotonic scheme (VMS) in [4] and the technique in [5] achieve 97.66 and 98.43% reduction in switching energy, respectively. However, the aforementioned schemes either utilise the energy-hungry operations (e.g. discharging capacitors from the Vref to the ground [1] or operating on both sides of the capacitor array during each comparison cycle [2]) or perform inefficient operation in the first few comparison cycles [1–5]. In this Letter, a new switching scheme is presented. In the proposed switching scheme, no switching energy consumption is achieved in the first three comparison cycles, and the low-energy monotonic technique is utilised for the rest of the operations, then the average switching energy of the proposed switching scheme is reduced by 98.83% compared with the conventional architecture.
Vcm Vcm 2C C C 0 Vip>Vin ?
Vcm Vcm C C
Vcm
2C C C Vip>Vin + 1/2Vref ?
C Vref
sample
1
2
3
sample
1
2
3
4
5
6
4
5
6
Vinp
C Vcm Vcm
Fig. 1 Switch sequences after MSB decision
Vinn
a
a Proposed switching scheme b Tri-level switching scheme Vinp
Hybrid capacitor switching scheme: Considerable energy saving can be achieved by improving the switch efficiency in the first few comparison cycles since that is when the bulk of the switching energy is consumed. Figs. 1a and b illustrate the first two switch sequences of the proposed scheme and the tri-level technique. In the proposed scheme, during the sampling phase, the bottom plates of the DAC capacitor array are set to [0, 0.5, 0.5…0.5], i.e. the bottom plate of the most-significant bit (MSB) capacitor is connected to the ground, and the bottom plates of the other capacitors are set to the common-mode voltage Vcm which is designed to be 0.5 Vref. The first comparison is performed directly after sampling with no switching energy consumption. Once the MSB is obtained, the sequence of the lower voltage potential side of the capacitor array is changed to [0.5, 1, 1…1]. No switching energy is consumed during this operation. After the second comparison, the sequence is set to [1, 1…1] or [0.5, 0.5…0.5] according to the second comparison result. Either of the operations consumes no switching energy, whereas 1/4 CV2refJ is required for the tri-level capacitor switching
Vinn
b
Fig. 3 Waveform of tri-level switching scheme, and waveform of hybrid switching scheme a Tri-level switching scheme b Hybrid switching scheme
Fig. 2 shows the proposed scheme for a 4-bit SAR ADC. First, in the sampling phase, the input is sampled onto the top plates of capacitors and the bottom plates of capacitors are set to [0, 0.5, 0.5…0.5]. Next, the sampling switches are turned off and the first comparison is carried out without energy consumption due to the top-plate sampling. Then, the second and the third comparisons are performed following
ELECTRONICS LETTERS 2nd January 2014 Vol. 50 No. 1 pp. 22–23
the principle shown in Fig. 1a and consume no switching energy as aforementioned. Then, the ADC performs the monotonic switching procedure for the subsequent comparisons. It is worth noting that during the monotonic switching procedure, only one capacitor switches for each comparison, and the corresponding voltage changes from Vref to Vcm or from Vcm to ground, resulting in less switching activity and lower energy. Figs. 3a and b provide an illustration of the waveform of the trilevel switching scheme and the proposed technique. As shown in Fig. 3b, the common-mode voltage variation of the proposed method is 25% less than that of the tri-level switching scheme. The commonmode voltage of the proposed switching scheme will gradually approach 1.5 Vcm. Switching energy analysis: The behavioural simulation of a 10-bit SAR ADC was performed in MATLAB to compare the proposed scheme with other recently published techniques. Table 1 shows comparison of the proposed scheme with existing ones. The proposed scheme consumes only 15.88 CV2refJ average switching energy and achieves a 98.83% energy saving compared with the conventional technique. The switching energy of the proposed scheme is 75% of the highest energy-efficiency technique reported in [5]. In the proposed switching scheme, the average switching energy for an N bit SAR ADC is given below Eavg =
N −3
2 2N −i−6 CVref
(1)
i=1
Fig. 4 illustrates a comparison of the switching energy for the several switching schemes against the output code. Benefiting from the new energy-efficient switch method, the proposed scheme achieves the best power efficiency. In addition, it is also worth noting that in the middle range of the output code, the switching energy of the scheme in [5] is nearly the same as the proposed one, whereas it is always larger on both sides. This is because at each output code in the middle range, the energy-saving method proposed in [5] takes effect with the maximum comparison cycles the scheme can achieve, whereas it always functions with less cycles on both sides and it coincides with Fig. 4.
Conclusion: A novel energy-efficient hybrid capacitor switching switching scheme, with an energy saving of 98.83% compared with the conventional technique, is presented. Compared with the existing schemes, the proposed scheme is more energy-efficient in the first three comparison cycles, benefiting from the new switch method. With the low-energy monotonic procedure for the rest of the operations, the proposed scheme achieves the lowest switching energy among the existing switching schemes. © The Institution of Engineering and Technology 2014 23 August 2013 doi: 10.1049/el.2013.2794 One or more of the Figures in this Letter are available in colour online. Liangbo Xie, Guangjun Wen, Jiaxin Liu and Yao Wang (School of Communication and Information Technology, University of Electronic Science and Technology of China, No. 2006, Xiyuan Avenue, West Hi-Tech Zone, Chengdu 611731, People’s Republic of China) E-mail:
[email protected] References 1 Liu, C.C., Chang, S.J., Huang, G.Y., and Lin, Y.Z.: ‘A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure’, IEEE J. Solid-State Circuits, 2010, 45, (4), pp. 731–740 2 Zhu, Y., Chan, C.H., Chio, U.F., Sin, S.W., U, S.P., Martins, R.P., and Maloberti, F.: ‘A 10-bit 100-MS/s reference-free SAR ADC in 90 nm CMOS’, IEEE J. Solid-State Circuits, 2010, 45, (6), pp. 1111–1121 3 Yuan, C., and Lam, Y.: ‘Low-energy and area-efficient tri-level switching scheme for SAR ADC’, Electron. Lett., 2012, 48, pp. 482–483 4 Zhu, Z., Xiao, Y., and Song, X.: ‘VCM-based monotonic capacitor switching scheme for SAR ADC’, Electron. Lett., 2013, 49, (5), pp. 327–329 5 Sanyal, A., and Sun, N.: ‘SAR ADC architecture with 98% reduction in switching energy over conventional scheme’, Electron. Lett., 2013, 49, (4), pp. 248–250
Table 1: Comparison of switching techniques for 10-bit SAR ADC
Conventional Vcm-based [2] Tri-level [3]
Average switching energies (CV2ref) 1363.3 170.17 42.42
Energy savings Reference 87.54% 96.89%
Area reductions Reference 50% 75%
VMS [4] Sanyal and Sun [5] This work
31.88 21.33 15.88
97.66% 98.43% 98.83%
75% 75% 75%
Switching schemes
220
switching energy, CV 2ref
200 180 160 Vcm-based [2]
140 120
tri-level [3] Vcm-based monotonic [4]
100
Sanyal and Sun [5] proposed
80 60 40 20 0 0
200
400 600 output code
800
1000
Fig. 4 Switching energy against output code
ELECTRONICS LETTERS 2nd January 2014 Vol. 50 No. 1 pp. 22–23
