Equipment Efficiency Improvement - Semantic Scholar

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David P. Busing, Tmg-Yun Liu, David Moore. University of Califomia. Berkeley, Califomia. Abstract - Lt has been determinedfiom the Competitive. Semiconductor ...
Equipment Efficiency Improvement: The Nt:w Frontier Robert C. Leachman David P. Busing, Tmg-Yun Liu, David Moore University of Califomia Berkeley, Califomia theoretical process times can be automatically updated using the models.

Abstract - Lt has been determinedfiom the Competitive Semiconductor Manufacturing (CSM) Survey that equipment fhroughput performance is highly divergent among competingf d s , and that even among leaah, there seems to be :rignificant improvement potential. ?%ispaper first presents a summary of new research being done at the University of California at Berhley to measure and monitor OEli and productivity losses. A summary of best practices fiom the CSMswvey is then presented

The other critical element of a strategy to measure and monitor equipment efficiency concems the means of data collection. We classify data collection techniques for OEE measurement and monitoring into four categories of increasing sophistication:

INTRODUCTION

Level 0 Machine availability and machine utilization determined from standard equipment tracking data collected in CAM systlems

Levels of OEE Measurement Systems

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Findings of the Competitive Semiconductor Manufacturing (CSM) Survey from the University of Califomia at Berkeley reveal a convergence to relatively high yields among leading world industry participants. However, equipment throughput performance remains very divergent a factor of two between the best performers and other participants in the survey. Even among the leaders, there seems to be significant potential for increasing equipment throughput.

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To better identify where productivity is being lost, we have developed ,techniques for rigorous measurement and monitoring of equipment efficiency losses. We also review best practices in equipment efficiency improvement observed in the CSM Survey. This paper summarizes our research and findings in each of these two areas. MEASUREMENTAND MONITORING OF OEE Accurate measurement and monitoring of OEE and efficiency losses are key drivers of efficiency improvement. At the heart of an OEE measurement system is the detenninatiaa of the theoretical process times or throughput rates of the machine asset under consideration. It is our impression that most companies are relatively weak in this regard. Theoretical process times that are not determined through rigorous measurement leave certain efficiency losses unchadlenged and distort the magnitude of others. The authors have developed detailed models of theoretical process times for many major types of semiconductor processing equipment. These models compute theoretical process t i m c ; as a function of machine tecipe s e t t h p , e.g.,

exposure energy, implant dose and energy, deposition thickness, etc., by analyzing the underlying critical path networks of machine operation and the physics of the machine. As recipes for process steps are changed, 0-1803-3752-2 /97/$10 01997 iEEE

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Level 1 OEE calculations based on application of theoretical formulae to standard WIP tracking and equipment tracking data collected in CAM systems

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Level 2 OEE calculations based on application of formulae to data obtained from periodic extractions of intemal machine event logs

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Level 3 On-lie efficiency monitoring Level 0 does not providle sufficient data to compute OEE, and the measurement of availability and idle time losses is not closed-loop. Levels 1, 2 and 3 afford closed-loop calculation of efficiency losses, and are numbered in order of increasing accuracy and increased detail in the explanation of effkiency losses. Levels 2 and 3 enable efficiency analysis of specific portions of the machine cycle, while Level 1 can only analyze the efficiency of the overall machine cycle. Level 3 enables continuous updating of OEE scores,,while Levels 1 and 2 only provide periodic updates.

Progress To Date We have fully implemented a Level 1 system for all major equipment types at a California wafer fab and, have also developed a preIiminary Level 2 system developed for Applied Materials PSOOO cluster tools in operation at the same fab. From these systems we observed that the combined general categories of speed losses and idle time are oftentimes more significant than downtime. We also determined that many productivity losses in newer more automated equipment are the result of logical defects in machine control systems; typical losses include triggering of unnecessary clean cycles and idle time forced on process chambers by transport systems.

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Results from Level 1-based systems are limited by the aggregated nature of the input data, and hence we are interested in the development of higher-ordered systems.

equipment that reduce down time losses andor increase machine speed. REFERENCES

Current Work In Progress

We are currently in the process of developing a prototype Level 3 system. We have found that the current industry practice, whereby equipment is classified into one, and only one, state at a time, is insufficient for characterizing all productivity losses. As part of our Level 3 prototype, we are testing a method that compares the effect of measurable losses associated with small portions of the machine cycle on the overall machine cycle time. BEST PRACTICES

The area of observed best practices to date for equipment efficiency is broad. We briefly describe the impact on equipment efficiency of efforts observed in the CSM survey in each the following areas: Eflective and accurate eflciency tracking systems. Many companies are now moving from Level 0 to Level 1; the leaders have implementedLevel 2. Effective process control and yield improvement techniques. Test rum and consequent enforced idle times waiting for inspection results may facilitate high yields and good process control, but at a cost of depressed wafer throughput. Means must be found to achieve high overall throughput (i.e., both high yield and high wafer throughput). Reductions in machine recipe overhe4 reticle change and setup times. Among the CSM participants, lost time per reticle change on 5X steppers used to process advanced submicron products ranges from 30 minutes down to 0. Lost time awaiting results of inspections of sample wafers is even more disparate. Communication between machines and operators/ /technicians to reduce time lost between consecutive machine cycles. Many small idle times can be mitigated through the use of audio and visual signals. Reducing the division of labor. Leading participants have instilled technician-level skills in their operators so that they can remedy many process and equipment problems without the down time of waiting for assistance. Production planning and factory scheduling methodr that increase utilization of a factory’s machine resources. Leaders plan their factory product mix so as to maximize factory revenue considering the detailed machine capacities. In the case of complex machine process step assignment constraints or significant setup times, intelligent floor scheduling installed by some participants has served to increase utilization. Equipment modifications that mitigate machine sofmare and hardware weaknesses. Leading participants have made effective modifications to

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[I]

R.C. Leachman, “Closed-Loop Measurement of Equipment Efficiency and Equipment Capacity,” IEEE Tram Semrconducr. Mum&&, vol. 10, w. 1, Feb. 1997.

p] R. C. Leachman, “Competitive Semiconductor Manufacturing

Survey: Third Report on the Results of the Main Phase,“ Competitive Semicon$uc.> Manufoct. (CSM) Program Research Reportr, CSM-31, AUg 1996

91 S.Nalrajima

lntroductron to

TPM Cambridge, MA. Productivity

Pres, 1988.

[4] Semiconductor Equipment and Materials International (SEMI),

“El&% Standard for Defmihon and Measurement of Equipment Reliability, Availability, and Maintainability (RAM),” in Book of SEMI Standards: Equipment Automairon/Hardware Volume. Mountain View, CA. Semiconductor Equipment and Materials International, 1996.

Robert C. Leachman received the A.B degree in physics and mathematics and the M.S. and Ph.D. degrees in operations research. all &om tbc University of Califomia, Berkeley He has been on the U.C. Berkeley faculty since 1979, where he is a Professor of Industrial Engineering and Operations Research, teaching factory management and productivity improvement courses in the College of Engineering. He is also &-Director of the Competitive Semiconductor Manuf-g Program. He has authored over 40 scientlfic and technical papers in the area- Since 1984, he has led Berkeley research efforts in production planning, scheduling and efficiency analysis of semiconductor manufacturing. He is the author of the Berkeley Planning System (BPS). a software for automating company-wide production planning and delivery quotation in semiconductor manufacturing that is now in use at several large semiconductor firms.

Dr. Leachman was the recipient of the Franz Edelman Award for outstanding practice of the management sciences from the Institute for Operations Research and the Management David P. Busing is a doctoral candidate at the University of California, Berkeley. He is currently working on his dissertation, “A Method for Identlfying Specific Productivity Losses In Semiconductor Manufactunng Equipenr.

Ting-Yun Liu is a doctoral candidate at the University of Caiifomra, Berkeley. He is currently working on his dissertation on capacity planning using rigorously d e f d theoretical processing models for equipment David Moore is a graduate student at the University of California, Berkeley. He is currently working on his dissertation on statistical analysis of factory throughput usmg rigorously defined theorettcal p m s m g models for equipment.