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Evolvable hardware is expected to have major impact on deployable systems for space ... opment of larger scale real-world systems addressing issues such as evolvability and ... posed solution was to have population members voting in committee style. ... The talk, entitled “Roving STARs: An Integrated Approach to.

IEEE TRANSACTIONS ON EVOLUTIONARY COMPUTATION, VOL. 5, NO. 6, DECEMBER 2001

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Book Reviews___________________________________________________________________________ The Third NASA/DoD Workshop on Evolvable Hardware Didier Keymeulen, Adrian Stoica, Jason Lohn, and Ricardo Zebulum (Los Alamitos, CA: IEEE Comput. Soc. Press, 2001, 288 pp.) Reviewed by Andy M. Tyrrell The Third NASA/DoD Workshop on Evolvable Hardware (EH-2001) was held between July 12–14, 2001, in Long Beach, CA, and cohosted by the Jet Propulsion Laboratory (JPL) and the National Aeronautics and Space Administration (NASA) Ames Information Sciences and Technology Directorate. The workshop was sponsored again by NASA and the Defense Advanced Research Projects Agency (DARPA). Evolvable hardware is an emerging field that applies evolution to automate design and adaptation of physical structures such as electronic systems, antennas, microelectromechanical systems, and robots. The purpose of this workshop was to bring together leading researchers from the evolvable hardware community, representatives of the automated design and programmable/reconfigurable hardware communities, technology developers, and end users from the aerospace, military, and commercial sectors. Evolvable hardware techniques enable self-reconfigurability and adaptability of programmable devices and, thus, have the potential to significantly increase the functionality of deployed hardware systems. Evolvable hardware is expected to have major impact on deployable systems for space missions and defense applications that need to survive and perform at optimal functionality during long duration in unknown, harsh, and/or changing environments. Evolvable hardware is also expected to greatly enrich the area of commercial applications in which adaptive information processing is needed; such applications range from human-oriented hardware interfaces and internet adaptive hardware to automotive applications. The focus of this year’s workshop was to provide a roadmap from the current proof-of-concept stage of evolvable hardware to the development of larger scale real-world systems addressing issues such as evolvability and scalability. The workshop attendees had the opportunity to discuss the fundamental issues and state of the art of evolvable hardware technology, plans for development of future devices and hardware systems suitable for evolution, and needs related to space applications. General Workshop Details The workshop was held over three days and comprised some 11 sessions with 35 presentations and six invited talks and covered many areas of evolvable hardware and associated activities. Around 95 people attended this year’s workshop, an increase from last year’s event. Around 60 of these people were from the USA, 17 from Europe, and majority of the rest from the Far East. The sessions can be divided rather crudely into the following six broad headings: 1) from biology to robotics; 2) bio-inspired systems; 3) reconfigurable architectures and devices;

Manuscript received September 7, 2001. The reviewer is with the Department of Electronics, University of York, Heslington, York YO10 5DD, U.K. Publisher Item Identifier S 1089-778X(01)10424-8.

4) survivable and flexible hardware; 5) evolution and evolvability; 6) applications. The Invited Talks There were six invited talks from respected scientists in both academia and “industry.” These were the following: 1) Richard Terrile (JPL): “Rise of the Machines: Evolvable Hardware and Space Exploration”; 2) Stephen Trimberger (Xilinx): “Reconfigurable Devices in the 21st Century”; 3) Xin Yao (University of Birmingham): “What Evolvable Hardware Still Can’t Do”; 4) Tetsuga Higuchi (Electrotechnical Laboratory): “Evolvable Hardware for Industrial Applications”; 5) Meyya Meyyappan (NASA AMES): “Nanotechnology in Information Processing: Opportunities and Challenges”; 6) Rob Rutenbar (Carnegie Mellon): “Synthesis for Industrial-Scale Analog Intellectual Property.” These were an excellent set of invited talks ranging from the speculative, such as Terrile’s thoughts on evolvable hardware and space exploration and its evolution to “thinking machines”—will we ever get to the Terminator film scenario? Very possibly, was the conclusion from this talk. At the other end of the spectrum, Higuchi talked about and gave video presentations on his work in the current application areas of evolvable hardware. These areas included his groundbreaking work on evolutionary hardware for the control of myoelectric artificial hand and the evolution of microwave circuits for use in the mass market of mobile phones. Rutenbar’s and Yao’s talks were based on current technologies and applications and discussed, respectively, work involved in synthesis of analog circuits for real industrial applications, including some of the problems encountered with IP, and where current evolvable hardware falls over and possible solutions to these problems, of which one proposed solution was to have population members voting in committee style. Trimberger and Meyyappan concentrated on the technological aspects of the area, where we are now, and where we might be going in the next few years. Trimberger discussed the environmental pressure of VLSI devices, in particular FPGAs, including time to market, process technology, volume production, and dominant applications. He showed how these pressures had inputs into the evolution of current devices on the market. It is clear that technological advances in manufacturing will be producing devices of 50 million system gates by the year 2005 allowing greater interconnect, processor on-chip, and/or mixed-signal devices. He mentioned that reconfigurability had been driven by process technology and manufacturability, not by applications. However, the good news for this community is that through technological and manufacturing advances, reconfiguration is not only a possibility, it is in fact required for new models of delivery of functionality. Meyyappan discussed the possibilities of alternative technologies from complementary metal–oxide–semiconductor (CMOS) devices. He commented that for such new technologies, one would expect them to be easier and cheaper to manufacture than CMOS, that there is a need for high current drive for interconnects, there should be a high level of integration (109 transistors/circuit), it should have high reproducibility and high reliability, and should

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be low cost. He then suggested four possible avenues of exploration: semiconducting single-wall carbon nanotubes, organic molecular wires, nanowires, and biomolecules (DNA). He showed that basic device demonstrations and simple logic functions are encouraging and keep optimism in these areas alive. However, one of the real targets is in low-cost self-assembly or bottom–up manufacturing and failure here will doom nanotechnology in nanoelectronics. Methods of system architecture design are key and will demand revolutionary approaches. The Workshop A comprehensive discussion on all of the papers in the workshop is out of the scope of this paper. Any selective summary is, therefore, going to be a personal view and what follows is no different from other similar reports. I, therefore, apologize now to those people I do not mention below. Their omission is my failing, not theirs. I will concentrate on six of the papers in the workshop. “An In-System Routing Strategy for Evolvable Hardware Programming Platforms,” presented by Moreno, considered the limiting factor of dynamic routing strategies in the support for evolvable hardware, an important and critical aspect of evolvable hardware if we are to build large machines. Moreno presented a programmable hardware architecture whose internal organization permits dynamic routing. The architecture is based on a regular bidimensional array of functional cells. A hierarchical layered organization has been provided for these cells. Specific routing resources have been included in one of these layers, so that they permit the construction in an incremental way of routing paths among the functional cells. The dynamic routing strategy is based on a replication process that is able to connect a source cell with various target cells. Moreno argues that one of the major advantages of the proposed routing strategy lies in the fact that its complexity grows only linearly with the array size, an important factor when considering large arrays of cells. Furthermore, it is scalable, accommodating without performance degradation to any array size. Behavioral hardware descriptions have been created for the functional cells that constitute the array. As the simulation and synthesis results show, the proposed routing strategy will permit the implementation of actual evolvable hardware principles. Such basic work is of great importance if we are to be able to successfully build large arrays of evolvable hardware devices and move the subject away from research projects into industry. An excellent system was discussed by Abramovici on ways of improving the reliability of field-programmable gate array (FPGA) systems. The talk, entitled “Roving STARs: An Integrated Approach to Online Testing, Diagnosis, and Fault Tolerance for FPGAs in Adaptive Computing Systems,” presented an integrated approach to online FPGA testing, diagnosis, and fault-tolerance to be used in high-reliability and high-availability hardware. This strategy makes use of dynamic reconfigurability both to perform error detection and to provide error recovery. The testing and diagnosis process takes place in self-testing areas (STARs) of the FPGA, without disturbing the normal system operation. The entire chip is tested by roving the STARs across the FPGA. The approach guarantees complete testing of both logic cells and interconnect with maximum diagnostic resolution. The multilevel fault-tolerant technique allows using partially defective logic and routing resources for normal operation, providing longer mission life in the presence of faults. In addition, the dynamic fault-tolerant method ensures that spare resources are always present in the neighborhood of the located faults, thus, simplifying fault bypassing. The complete method was successfully implemented and demonstrated on the ORCA 2CA series FPGAs from Lucent Technologies. Stoica presented for the JPL team the paper “Evolvable Hardware Solutions for Extreme Temperature Electronics.” Temperature and radiation tolerant electronics as well as long-life survivability are key

capabilities required for future NASA missions. Current approaches to electronics for extreme environments focus on component-level robustness and hardening. Compensation techniques such as bias cancellation circuitry have also been employed. However, current technology can only ensure very limited lifetime in extreme environments. Stoica presented a novel approach based on evolvable hardware technology, which allowed adaptive in-situ circuit redesign/reconfiguration during operation in extreme environments. This technology would complement material/device advancements and increase the mission capability to survive harsh environments. The approach has been demonstrated on a prototype chip, which recovers functionality at 250  C. Besides the applications that provide adaptive reconfiguration, evolutionary algorithms can be used to automatically design (fixed) circuits for high temperatures. While simulations shows that conventional AND gate design fails at high temperatures such as 320  C, evolution is able to synthesize AND gate circuits operating accurately at this temperature. Two papers in the session on Brain-Inspired Architecture considered different aspects of Embryonics, i.e., arrays of electronic processing elements inspired by molecular biology. The paper presented by Stuffer, “BioWatch: A Giant Electronic Bio-Inspired Watch,” considered some of the basic processes of molecular biology, such as the embryonic development of living beings. Stuffer argued that by transposing these processes into electronic integrated circuits, the artificial organizms produced will be endowed with properties typical of the living world, such as self-repair and self-healing. In order to illustrate the original features of the Embryonics project, a cellular and molecular architecture of a giant artificial organizm is defined, the BioWatch. The hardware implementation of the watch exploits a new reconfigurable tissue, the bio-inspired electronic wall or “BioWall.” A current implementation of the BioWall is under construction in Switzerland, which will consist of 3200 molecules, the largest Embryonic structure ever built. One possible limitation of the Embryonics project is scalability, due not in the least because of clock propagation problems. Jackson presented a paper “Asynchronous Embryonics,” which addresses this problem. As embryonic arrays take inspiration from nature they display biological properties, namely, complex structure and fault tolerance. However, Jackson argued that they have yet to take advantage of a further biological feature at a fundamental level—asynchronous operation. In addition to the benefits normally associated with asynchronous digital design, such as intrinsic power management, two areas in which embryonic arrays could benefit are scalability and reliability. He gave an overview of embryonic systems and a pertinent asynchronous methodology, that of macromodules. He illustrated his ideas by showing that a macromodule approach allows the implementation of asynchronous circuits on Xilinx Virtex FPGAs using only the standard design tools. A preliminary VHDL simulation illustrated the operation of an asynchronous embryonic array. Although mentioned, little detail of the reconfiguration scheme is given. The whole Embryonics field brings an exciting dimension to evolvable hardware and could provide an excellent platform for intrinsic evolution in the future. Asynchronous Embryonics is an important avenue to investigate and Jackson’s paper and the simulation he presented brings truly asynchronous embryonic circuits a step closer. The final paper I wish to highlight is “The Architecture for a Hardware Immune System,” presented by Bradley. Since the advent of fault tolerance in the 1960s, numerous techniques have been developed to increase the reliability of safety-critical and space-borne missions. In the last decade, novel approaches to this field have sought inspiration from nature in the form of evolutionary and developmental forms of fault tolerance. In nature, an additional inspiration axis exists in the form of learning. The body’s own immune system uses a form of learning to maintain reliable operation in the body even in the presence of invaders.

IEEE TRANSACTIONS ON EVOLUTIONARY COMPUTATION, VOL. 5, NO. 6, DECEMBER 2001

This has only recently been applied as a computational technique in the form of artificial immune systems (AISs). Bradley demonstrated a new application of AISs with an immunologically inspired approach to fault tolerance. He showed that a finite state machine can be provided with a hardware immune system to provide a novel form of fault detection giving the ability to detect every faulty state during a normal operating cycle. This is call immunotronics. The immune system in nature has some excellent fault-tolerant properties, much better than the best electronic system. The big question is can we, with the limited resources available to us in an electronic system, make use of immunotronics to build successful and useful fault-tolerant hardware? I believe the “court is still out” on this question. However, Bradley’s work goes someway to giving us some answers. The Future? First, I would say that EH-2001 follows the previous two workshops in that it consisted of a number of high-quality, interesting, and

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thought-provoking papers. The team at NASA has now established one of the major activities in the evolvable hardware calendar. What topics might we consider important for next year’s workshop in Washington, DC? I would say that the field is still developing, evolving, and that many of the “hot” topics this year will be seen again next year. These will I am sure include: evolutionary hardware design, coevolution of hybrid systems, evolving hardware systems, intrinsic and online evolution, hardware/software coevolution, self-repairing hardware, self-reconfiguring hardware, embryonic hardware, morphogenesis, novel devices, and. adaptive computing. Of course, we are always looking for, and interested in, real-world applications of evolvable hardware. Will we see more relating to nanotechnology, new reconfigurable FPGAs, new models of reliability for long space mission? Only time will tell—as with all evolution.

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