FPGA-based Optical Network Function Programmable Node

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over WDM transport and switching, and also the intra network service ... For instance, 3 node slices are demonstrated in Fig.1.b, where hardware slice 1.
FPGA-based Optical Network Function Programmable Node Yan Yan, Georgios Zervas, Bijan Rahimzadeh Rofoee, and Dimitra Simeonidou High Performance Networks Group, Merchant Venturers’ Building, University of Bristol, Clifton, Bristol BS8 1UB, UK. [email protected]

Abstract: The paper presents architecture, implementation and evaluation of optical network function programmable node with hitless inter-function and intra-function switch-over. It supports multiple network functions on opto-electronic programmable hardware providing function-based virtualization and high network performance. OCIS codes: (060.4250) Networks; (060.4510) Optical Communications.

1. Introduction Adapting to the spatial and temporal nature of cloud traffic in access/metropolitan network areas, multi-functional networks with flexible operations are highly desirable. Architecture on demand (AoD) nodes [1][2] with modular and pluggable structures, and Optical sub-wavelength switching, such as Time Shared Optical Network (TSON) [3][4] with bandwidth adjustable platforms are hence suitable options for networks with variable/uncertain traffic behavior. However networks are going through fundamental changes with new approaches such as Network Functions Virtualization (NFV)[5]. NFV nodes have restricted scalability and flexibility limited by the commodity hardware (e.g. CPU) its running upon. In this regard, networking systems hardware needs to provide a degree of flexibility and programmability to allow enhanced control over the network wide operations. In this paper, we take a next step in network/node programmability, and report on the design and implementation of the first FPGA-based optical network function programmable node, which is capable of using electronic systems (e.g. FPGA/SoC) and optical devices (AOD) to deliver various network functions on demand. The implemented functions in the node can operate in aggregation as well as in isolated groups, which enables the node to fully support hardware virtualization and creating slices of the node associating them with arbitrary traffic types. The functions are categorized as intra and inter functions, and the node is capable to switch over between any of them hitless. The results shows hitless network function switch-over, guaranteed transport of parallel virtual slices, capable of 9.18Gbps out of 10Gbps throughput, flexible link granularity (6.85Mbps to 9.18Gbps) and single timeslice granularity (6.85Mbps to 2.4Gbps), variable latency (1.747 µs to 118.233 µs) and jitter (10 µs to 30 µs).

Fig. 1. Network Function Programmable System: a) Opto-electronic node architecture; b) Programmable and isolated node slices.

2. Optical Network Function Programmable Node Architecture The node architecture (Fig.1a) consists of FPGA-based electronic programmable system and optical programmable system. Different classes of network functions are displayed with different colors. The blue box on top contains the global node control functions. Red box includes the network functions services such as optical TDM or Ethernet over WDM transport and switching, and also the intra network service operations as the frame and time-slice lengths, aggregation mechanism, overhead management for achieving certain quality of transmission etc. The green box represents functions in the node which correspond with the optical components and their control. Underneath

the FPGA node, the programmable optical architecture on demand is located which holds on to the optical components such as switches, amplifiers, Mux and Demux, etc. 3. Node work flow When the user (e.g. operator, service provider) requests to setup a network service, after evaluating its requirements such as bit-rate, connectivity type, QoS, and QoT by network controller, the necessary on-chip network function blocks and optical components that fulfill such requests are identified and programmed to compose a dedicated network function slice of the node. For instance, 3 node slices are demonstrated in Fig.1.b, where hardware slice 1 performs as Ethernet node with functional blocks of central controller(network function block), the Ethernet switch (node function block) and wavelength MUX/DEMUX (optical device) to realize Ethernet over WDM. If a network service demands 2Gbps, with point to multi-point long distance connectivity and no latency requirement, a slice 2 can be programmed and isolated from the first slice, supporting incoming Ethernet flow aggregation to large timesliced bursts, and allocation of necessary programmable QoT preamble overhead. Slice 3 can be provisioned to handle network services such as Virtual Machines from distributed Data Center to end users where traffic is latency sensitive but have no QoT requirements. As such, its network function is programmed to support frame size with short time-slices (no aggregation) for low latency, and no use of QoT overhead block. . . .

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Fig. 2. FPGA-based Optical Network Function Programmable node: a) High-level functional blocks; b) Elastic TDM -Ethernet switchover; c) Programmable parameters; d) Elaborated Isolated data storage functional block.

4. Implementation The data flow follows the direction of arrows. The control/management blocks, shown in brown, set the link between server and FPGA, which updates its Look-up-table (LUT) that can control the programmable functions in the FPGA. Different categories of implemented function blocks are visualized with different colors (Fig 2.a): data parsing(blue), LUT for control (brown), Intra function switch over such as varying frame size of TDM in yellow, inter function switch for changing TSON to Ethernet for instance in pink, and external drivers in grey. Fig.2b shows the hitless transmission after switchover, when switch from Elastic TDM to Ethernet, the interfunction switch blocks wait for the current aggregated time-slice finished, then starts to transmit the Ethernet. In opposite, while switching from Ethernet to Elastic TDM, the FPGA waits finishing processing current Ethernet Frame, and then starts to transmit as time-sliced. The programmable parameters for intra-function switchover are demonstrated in Fig.2c, such as QoT overhead (programmable from 0 to 39KB), time-slice size (programmable from 80B to 31.25KB), time-slice numbers in a frame (programmable from 4 to 100), and time-slice allocation. To allow for isolating the traffic with different function requirement and virtually having 4 parallel nodes on the same programmable hardware, the green block schedule and isolate is employed and elaborated in Fig.2d. Based on the destination MAC address, source MAC address and VLAN tag, the incoming Ethernet traffic can be scheduled and isolated to different buffers and supported with purpose-made network functions i.e. aggregated on specific timeslice durations with particular throughput, QoS (latency, jitter) and QoT (bit-error rate) guarantees. For example, the

burst can be aggregated with single VLAN tag or a group of VLAN tags according to the requirement. For the interfunction and intra-function switchovers, all the nodes in the network are synchronized. Oscilliscope Server

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Fig.3. Optical Network Function Programmable node Experiment Setup and Results: a) Back-to-Back Testbed setup; b) Oscilloscope captured time-slice and transport preamble signals; c) Oscilloscope captured transport preamble signals; d) Hitless switchover Received Bit-rate; e) BitRate; f) 5Gbps traffic’s Latency; g) 1500B Ethernet Frame 5Gbps traffic’s Jitter; h) 40% Transmitted Rate’s Latency.

5. Experiment Setup and Results The test bed, shown in Fig.3a, is setup for generating and receiving data as well as measuring the results. The server deploys virtual machines, in which higher layer control is placed to dynamically update the programmable parameters in the FPGA over 10 Gigabit Ethernet. The traffic is generated by Anritsu MD1230B, a 10Gbps Ethernet/IP network data analyser, which is also used to analyse the latency and jitter. The measurement results are shown in Fig.3b-h. Fig.3b displays the changes of envelop signals of time-slice size (upper signal) and transport overhead (middle signal) when LUT updated (bottom signal, point A) with decreased time-slice size and transport overhead. In Fig.3c and d, Point A is intra-function switchover to less transport overhead and time-slice size, and Point B is inter-function switchover from Elastic TDM to Ethernet. Fig.3c shows the envelop of transport overhead decreases after point A, and turns to zero after point B. Fig.3d reveals hitless intrafunction and inter-function switchover with bit-rate changes. The time-slice size affects the bit-rate when time-slice size is comparable to the transport overhead (minimum 1.07KB). Fig.3e-g are measured with fixed time-slice numbers (100) and variable time-slice size. The minimum time-slice size for 64B is 80B, for 1500B is 1.5KB, and the maximum for both is 31.25KB. Fig.3e gives information of the maximum bit-rate with increased time-slice size. The link granularity ranges from 6.85Mbps to 9.18Gbps, and single time-slice granularity is from 6.85Mbps to 2.4Gbps. From Fig.3f, the latency increases with time-slice size increases. When the node is in Ethernet mode, the minimum latency is 1.747µs, while in Elastic TDM mode, the latency ranges from 13.115µs to 118.233µs. As can be seen from Fig.3g, when the time-slice size gets bigger, the percentage of traffic not received in 2µs goes lower, but the percentage of traffic with more latency goes higher. When the node setup is with fixed time-slice size (12.2KB, 10μs) , variable time-slice numbers, and time-slice allocation grouping as many allocated time-slice as possible, like “0000011111”(‘0’ means unallocated time-slice, and ‘1’ means allocated time-slice), Fig.3h shows the latency becomes worse when frame length gets longer. 6. Conclusion This paper reports on the design and implementation aspects of the FPGA-based optical network function programmable Node architecture with focus on hardware L2 functionalities implemented using high performance FPGA platform. The measurement results show the system is network function programmable, and able to achieve high QoS and throughput performance and hitless switchover. 7. Acknowledgement This work is supported by CONTENT, LIGHTNESS and IDEALIST project, funded by European Commission. References [1] B. Rofoee, et al, “Programmable on-chip and off-chip network architecture on demand for flexible optical intra-datacenters”, J.OpEx.13, v21 [2] N. Amaya, et al,“Introducing Node Architecture Flexibility for Elastic Optical Networks,” J. Optical Communications and Networking, 13, v5 [3] G. Zervas, et al "Time Shared Optical Network (TSON): a novel metro architecture for flexible multi-granular services" J.OpEx.11, v19 [4] Y. Yan, et al, "High performance and flexible FPGA-based time shared optical network (TSON) metro node", J.OpEx.13, v21 [5] White paper “Network Functions Virtualisation”,2012