FPGA Implementation of Image Enhancement

FPGA Implementation of Image Enhancement Techniques Karan Kumar, Aditya Jain, and Atul Kumar Srivastava* * Department of Electronics & Communication, Jaypee Institute of Information Technology University, Noida

ABSTRACT The objective of this paper is designing, modeling, simulation and synthesis of four Image Enhancement techniques on FPGA. Image Enhancement Algorithms can be classified as point processing Techniques, in which operation is done on pixel level and Spatial Filtering Technique, in which operation is performed within neighborhood of a pixel. Algorithms of all the techniques are studied and hardware circuits are realized for them. Then hardware logic is modeled in Matlab Simulink using Xilinx System Generator Block set and synthesized onto Virtex4 xc4vsx35-10ff668 FPGA chip. Using hardware co-simulation feature of FPGA kit, the algorithms developed are validated. Key words: Image Enhancement, Image Enhancement using FPGA

I.

Introduction

Image Enhancement is a wide area with its applications in different domains. Image Enhancement is a computational intensive task [1]; in which processing involves applying a specific function repetitively. One solution to carry out these computational intensive tasks is to use a general-purpose microprocessor or Digital Signal processors. But these implementations are sequential, with less on chip memory for buffering, so we require external memory for buffering. Fetching data from this external memory require certain clock cycles which effects system performance. Also these systems require glue logic for their operations [2]. We can reduce this glue logic and speed up our operations using Application Specific Integrated Circuits (ASICs). But main problem with ASICs are they require large time to market and initial investments are high. Before developing an ASIC we require to prototype our design. Field programmable Gate Arrays (FPGAs) prove to be a better solution for rapid prototyping. FPGAs are reprogrammable, have large number of logic cells suitable for implementing image enhancement applications. We can explore the parallelism and pipelining feature of FPGA to speed up our techniques. Modern FPGA chips include dedicated DSP functions, PowerPC, Micro blaze, etc which motivate designers to choose FPGA as a platform. With the increasing features of Synthesis tools it is easy to verify our design. Xilinx System Generator is an add-on in Matlab Simulink. Using this Xilinx blockset is added to Simulink, with this blocks we can model any of our hardware design easily, simulate it to verify its functionality and using hardware co-simulation feature we can validate our design on hardware. In section-2, the brief architectures suitable for modelling four Image Enhancement Techniques have been described, Section-3 explains about implementation details and Section-4 & 5 gives results and concluding remarks.

II. Hardware Realizations for four of the Image Enhancement Techniques. Image Enhancement Algorithms can be classified as point processing Techniques, in which operation is done on pixel level and Spatial Filtering Technique, in which operation is performed within neighborhood of a pixel [3]. Amongst the

Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2009, edited by Ryszard S. Romaniuk, Krzysztof S. Kulpa, Proc. of SPIE Vol. 7502, 750208 · © 2009 SPIE · CCC code: 0277-786X/09/$18 · doi: 10.1117/12.837179 Proc. of SPIE Vol. 7502 750208-1

various algorithms of Image Enhancement Techniques; we shall discuss hardware realization of four algorithms in this section.

1. Point Processing Techniques Power Law Transformation The power-law curves with fractional values of Ȗ map a narrow range of dark input values into a wider range of output values, with the opposite being true for higher values of input levels [3]. The expression for power law transformation is s = c.rȖ………….. (1) [3]

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Fig 1.

Implementation of Power-Law Transformation

We have implemented power-law transform for c=0.225 and Ȗ=3. Image Negatives Image Negatives is just reversing the intensity of each pixel. The logic used is taking difference between maximum gray scale value i.e. 255 and input image pixel’s value.

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Fig 2.Implementation of Image Negatives

2.

Spatial Filtering Technique

We use coefficients for different algorithms depending on operation we want to perform on the image. We are using only three 1-D filters [4] for implementing different spatial filtering techniques. Consider the mask shown in Fig 3.

Fig3. A 3×3 Filter Mask

Gradien (Sobel) Filter We assign different mask values for p1 to p3 for Sobel filtering technique.

Proc. of SPIE Vol. 7502 750208-2

The masks are shown in APPENDIX-A Technique

Coefficients

Sobel

sa, s’a, s’’a

Table1. Coefficients for Sobel filtering technique

In Fig 4&5. Values are assigned to p1, p2 and p3 with Sobel filtering coefficients.

p1

sa s’a

coefficients

s’’a

p2 p3

Fig4.Block Diagram of Implementation of

Fig 5.Implementation of Coefficients p1, p2, and p3

Coefficients p1, p2, and p3

These coefficients obtained are used as taps to three tap 1-D FIR [4] Direct Form 1 filters. The output of this filters are summed and scaled, represents the pixel value of center pixel in window. The overall circuit is shown in Fig 6.

Fig 6.Overall Sobel Filtering Technique


Laplacian Filter We assign different mask values for p1 to p3 for laplacian filtering technique. The masks are shown in APPENDIX-B Technique

Coefficients

laplacian

la, l’a, l’’a

Table2. Coefficients for laplacian filtering technique

In Fig 7&8. Values are assigned to p1, p2 and p3 with laplacian filtering coefficients.

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Fig7.Block Diagram of Implementation of

Fig 8.Implementation of Coefficients p1, p2, and p3

Coefficients p1, p2, and p3

These coefficients obtained are used as taps to three tap 1-D FIR [4] Direct Form 1 filters. The output of this filters are summed and scaled, represents the pixel value of center pixel in window. The overall circuit is shown in Fig 9.

Fig 9.Overall Laplacian Filtering Technique


III. IMPLEMENTATION DETAILS The technique discussed above is implemented on Virtex 4 kit, and tested for different images.

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Fig10.A prototype Image Enhancement Processor

The input image is in the form of matrix must be converted to a single column matrix; this is done using Raster scanning the input image. The mask image, which is used for logical operation is also raster scanned [6]. The ROM is initialized. Now the Algorithms are verified by simulation with an image. Then Virtex 4kit is enabled for hardware-in-Loop verification with JTAG co-simulation via the USB configuration port [5].The hardware co-simulation block is generated for prototype image Enhancement processor and design is tested with standard image.

IV. Results INPUT IMAGE [3]

ENHANCED IMAGE PROCESSED USING FPGA CHIP

A) Power Law Transformation

Fig 11 (a)

Fig 11 (b)


B)

Image Negative

Fig 12 (a)

Fig 12 (b)

Fig 13 (a)

Fig 13 (b)

C) Sobel Filtering

D) Laplacian Filtering

Fig 14 (a)

Fig 14 (b)


V) Conclusion The main aim of the paper is to show FPGA Implement Image Enhancement Techniques. Different point processing and Spatial Filtering techniques have been implemented successfully. The simulation and synthesis results were obtained and designs are successfully validated using hardware co-simulation feature of Virtex 4 kit.

Appendix A

Appendix B

Gradient (Sobel) Filter[3]

Laplacian Filter Mask[3]

Appendix C 1) Power law Design Summary:

Number of errors:0; Number of warnings: 20

Number of Slice Flip Flops: 419 out of 30,720 1%

Number of 4 input LUTs: 468 out of 30,720 1%

Number of occupied Slices: 500 out of 15,360

Number of Slices containing only related logic: 500 out of

3%

500 100% Number of Slices containing unrelated logic: 0 out of

Total Number of 4 input LUTs: 621 out of 30,720 2%

500 0% Number used as logic: 468

Peak Memory Usage: 313 MB

Total REAL time to MAP completion: 23 secs

Total CPU time to MAP completion: 21 secs

2) Image Negative Design Summary:

Number of errors:0; Number of warnings: 23

Number of Slice Flip Flops: 365 out of 30,720 1%


Number of occupied Slices: 385 out of 15,360 2%

Number of Slices containing only related logic: 385 out of

Number of Slices containing unrelated logic: 0 out of 385

385 100%


0% Peak Memory Usage: 309 MB


Total CPU time to MAP completion: 19 sec 3) Sobel Filtering Design Summary:

Number of errors: 0; Number of warnings: 20

Number of Slice Flip Flops: 868 out of 30,720

2%




Number of Slices containing only related logic: 782 out of 782 100%

Number of Slices containing unrelated logic: 0 out of






4) Laplacian Filtering Design Summary:

Number of errors: 0; Number of warnings: 20

Number of Slice Flip Flops: 529 out of 30,720

1%



Number of Slices containing related logic: 697 / 697 100%

Number of Slices containing unrelated logic: 0 out of






References 1. Article

on,

“Using

FPGAs

for

DSP

Image

Processing”,

available

at:

http://www.fpgajournal.com/articles/imaging_hunt.htm 2. U. Meyer–Baese, “Digital Signal Processing with Field Programmable Gate Arrays,”Springer– Verilag, New Delhi, 2003. 3. Rafel C Gonzalez, Richard E.Woods, ”Digital Image Processing”,2nd Edition, Prentice Hall 2001. 4. Shewring, I.W.; Wahab, M.A.;” An integrated approach to the design and implementation of image filters”, IEE 15th SARAGA Colloquium on Digital and Analogue Filters and Filtering Systems, IEEE 1995,pp 13/1 - 13/7,. 5. System Generator for DSP performing Hardware-in-the-Loop with Virtex 4kit, available at: www.xilinx.com. 6. Xilinx Application Note, “Developing Image Processing Algorithms with System Generator”2005. 7. Image databases,” Images from Digital Image Processing, 2nd edition, by Gonzalez and Woods” available at: http://www.imageprocessingplace.com/root_files_V3/image_databases.htm.
