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Game Theory and its Application to VLSI Physical Design Parthasarathi Dasgupta1 Abstract VLSI Physical design problems typically involve solving some of the hardest problems of combinatorial optimization. Complex process technologies in the deep submicron regime and rapidly reducing feature sizes have augmented the hardness with increasing number of objectives and constraints. Most of these objectives appear to be conflicting in nature. Game theoretic modeling plays a useful role in solving such multi-objective problems. It relies on features of rationality, coalition formation, competition, and equilibrium. The outcome is typically a solution that is the best for a player with respect to every other player’s objectives and decisions. Each player has an associated payoff function, measuring its expected utility in the game. The goal is to find a solution that is the best (or optimum) for all the players. A game is said to reach equilibrium when the combination of strategies of all the players has the best possible payoff for all the players. Introduced by Von Neumann in early twentieth century, Game Theory was originally a subject of economists, social scientists, and mathematicians. It has recently found applications in Electronic markets, Computer networking and other fields of Computer Science including formulation and solving the hard problems of the VLSI Physical Design. Keywords: VLSI Physical design, Interconnect routing, Game Theory

1. Introduction The general idea of a game between several players is to start from a given point and to proceed with a sequence of moves by the different players. At each instance of the game, a player has to choose a possible action from a set of several possibilities depending on the previous actions by different players. A player may even apply a random move, such as throwing a die or shuffling a deck of cards. Formally, a game is a structured or semi-structured activity, usually done for enjoyment. Key components of games are goals, rules, challenge, and interactivity. In game theory, the word game, used in the metaphoric sense, typically refers to a sequence of interactions between several players. The outcome of a game depends on the sequence of actions or moves by the players. The pioneering works by von Neumann in 1928 [Neumann 1928] and Nash in 1950 [Nash 1950] form the basis of Game Theory. Game Theory 1

Indian Institute of Management Calcutta, email – [email protected] This work is sponsored by a Research Project funding from Ministry of Comm & IT, GoI

has been extensively studied in the past from the viewpoint of mathematics and economics, and several applications proposed [Osborne and Rubinstein 1994]. However, very recently, it has found enormous applications in several other areas such as the design of electronic markets, computer networking, collaborative computing and VLSI design. This paper focuses on specifically on the problems of Physical Design of VLSI circuits, and elucidates some of the recent works on Game Theoretic modeling of such problems, and the associated solution methodologies. The rest of paper is organized in the following manner. Section 2 introduces the different concepts related to Game Theory in a brief manner. Section 3 discusses the various issues of VLSI Physical Design, and concentrates on the complexities related to the problems of deep submicron regime. Section 4 provides a survey of some of the recent works in Game Theoretic modeling of VLSI Physical Design problems and associated algorithms. Finally, Section 5 highlights some of the future possibilities of related applications.

2. Basics of Game Theory Game Theory is a means of analyzing the interaction of decision makers with multiple and often conflicting objectives. The essential elements of a game are the players, actions, payoffs, and information. Collectively, these elements form the rules of the game. Games may be cooperative or non-cooperative. Games are said to be cooperative when the rules can be previously stated or agreed upon by the players for use in deducing common strategies. On the other hand, a game without any such agreements among the players, is called a non-cooperative game [Nash 1950]. Non-cooperative games are typically played between rational players who know the complete details of the game, including each other’s preferences and outcomes. Some of the salient features of game theory include (i) Rationality: Each player is always selfishly trying to optimize its gain; (ii) Coalition: when a subset of players have the same agenda in terms of strategies in order to achieve a common optimization goal; (iii) Competition: multiple decision makers control a specified set of system variables and seek to optimize their conflicting objectives. (iv) Equilibrium: when all the players’ objectives have been optimized with respect to one another. Ordinarily, the set of players of a game are assumed to be rational decision makers. Each player or decision maker attempts to maximize his own utility by a set of actions in the presence of other decision makers. An action or a move by a player is a choice at an instant of the game. The strategy of a player is a rule or set of rules to decide upon an action at every instant of the game. For a set of players in a game, a strategy combination is an ordered set of strategies, having one strategy for each of the players in the game. Payoff of a player is the utility obtained by that player after the players have chosen their strategies and the game has been played. The information set of a player is the knowledge of actions previously chosen by the players at a given instant of the game, and changes with as the game proceeds. A game, when completed, is said to reach an equilibrium, if the corresponding combination of strategies comprises the

best strategy for each of the players in the game. This combination of strategies chosen by the different players tends to maximize their individual payoffs among the possible strategy combinations for these players. The equilibrium outcome is the set of payoff values of the players corresponding to their equilibrium strategies. In non-cooperative games, players choose their strategies independently and the rules of the game do not allow finding commitments among the players. Thus, such games are played with exclusively rational players. Each player focuses on his own choice of strategies and the corresponding payoff. In cooperative games, on the other hand, coalitions are formed amongst a subset of players and players of a coalition apply their joint actions according to some prior agreements. These games focus on coalition formation and the distribution of benefits gained through cooperation. A special type of non-cooperative games is the normal form game, in which the players move simultaneously to choose their strategies. The normal form shows what payoff results from each possible strategy combination. As the players make their moves simultaneously, they cannot learn each other’s private information by observing each other. Thus, in normal form games the information set of each player about the other players is null. A normal form game involves the list of players, their possible sets of strategies, and the payoff functions. A simple example of a normal game is the game of matching pennies. In this game, a player P1 chooses “heads” (H) or “tails” (T). Player P2, without any knowledge of player P1’s choice, also chooses “heads” or “tails”. According to the rule of the game, if the two players choose alike, then P2 wins a cent from P1, otherwise P1 wins a cent from P2. Thus, the normal form of the game is the following matrix.

H T

H (-1, +1) (+1, -1)

T (+1, -1) (-1, +1)

Another formulation is extensive form games, also known as sequential move games. The players in this game move sequentially and choose their strategies according to an order. The order of the play is important and affects the final outcome of the game. The extensive form game is represented by a list of players, their sets of actions, information sets, and payoff functions. The strategies of the players are a series of actions. The information sets represent the various states each player can take at any given point in the game. The important difference between simultaneous and sequential move games is that in sequential move games, a player acquires information on how its predecessor player moved before making his own decision. To identify best responses of the players, the concept of Nash Equilibrium was introduced by John Nash [Nash 1950]. In Nash equilibrium, none of the users can unilaterally change their strategy to increase their utility. For noncooperative finite games, Nash equilibrium can be defined in terms of normal form games. The concept can be extended to extensive form games as well. Let

G = {S1, . . . , SN; P1, . . . , PN} be a non-cooperative finite game in normal form with N players. The set Si contains all the strategies and the set Pi contains the corresponding payoff values for a player i. The N-tuple of strategies ŝ = (ŝ1, . . . , ŝN ), where ŝ1 Є S1, . . . , ŝ N Є SN, is defined as a Nash equilibrium (NE) point of G if Pi(ŝ1, . . . , ŝi , . . . , ŝ N ) ≥ Pi(ŝ1, . . . , ŝi-1, ŝi , ŝi + 1, . . . , ŝ N ) holds ∀ ŝi Є Si and i = 1, . . . , N. In other words, once in the state represented by the strategy choices s , the player’s payoff does not improve if he unilaterally deviates from the NE strategy. The Nash equilibrium point defines the payoff values for all the players in the game. Thus, qualitatively, the Nash equilibrium for an N-player finite game is an N-tuple set of strategies ŝ = (ŝ1, . . . , ŝN ), given by N inequalities such that no single player can gain by changing only his own strategy. An interesting result from [Papadimitriou 2001] shows that for a player having conflicting interests, the Nash equilibrium solution always exists and tends to achieve global optimal solutions. Moreover it is known from [Papadimitriou 1994] that the complexity of determining the Nash equilibrium is between P and NP, depending on the formulation of the problem.

3. Physical design of VLSI: Some Recent Trends Physical Design of VLSI circuits involve a sequence of phases [Sherwani 1999]. Some significant phases include partitioning, floorplanning and placement, interconnect planning, interconnect routing and buffer block placement. Traditional objectives of physical design primarily included area minimization [Cong, Nataneli, Romesis and Shennerl 2006]. However, with the drastically reducing feature sizes, several critical issues are coming up which affect the performance of the chip. Recent researches in these areas concentrate on the improvement of the performance of the chip. The remaining part of this Section discusses on some of these. It is known that in the deep submicron (DSM) regime, the circuit delay is primarily dominated by the delay of interconnects due to the drastic reduction in gate delay. As a result, several new performance-related issues have gained importance. Thus, we need to consider these new factors in the floorplanning phase as well. Recent works [Chen et al 1999, Sham and Young 2002] consider the integration of interconnect planning and buffer block planning with floorplanning. While [Chen et al 1999] integrates interconnect planning with floorplanning, [Sham and Young 2002] proposes a routability-driven floorplanning method which takes into account congestion estimation and buffer planning. Partitioning and placement: Design of a complex system, comprising a large number of components is difficult without decomposing it into smaller subsystems. On decomposition, each subsystem can be designed independently. The process can be continued recursively until each subsystem contains only a single basic component. This process is widely applicable in hierarchical design strategies for a VLSI circuit, and is commonly referred to as partitioning. Partitioning of an electrical circuit depends on certain parameters like (a) interconnection between the partitions, (b) delay due to partitioning, (c) number

of terminals, (c) area of each partition, and (d) the number of partitions. A complete survey of the different partitioning schemes appears in [C. J. Alpert and A. B. Kahng 1995]. The partitioning of a VLSI circuit yields a number of slots to be assigned to logical modules subject to certain constraints such that certain objective functions are optimized. This leads to the placement problem. Several placement methods have been reported in literature [Cong et al 1996]. These can be broadly classified into constructive methods (build up a placement starting with the slots and the logic modules), and move-based iterative methods. Placement in a DSM flow, however, must be aware of all the design variables. This requires an open cost function, which can analyze timing, area, power, congestion and signal integrity [Morteza 2006, Brenner and Rohe 2002]. Interconnect planning As already stated above, interconnect has become a dominant factor in determining overall system performance and reliability. Inevitably, it impacts all the stages of the design flow. A three-phase interconnect-centric design flow has been proposed by Cong et al, which includes (i) interconnect planning, (ii) interconnect synthesis, and (iii) interconnect layout. Interconnect planning is important because it provides early assessments on the system performance, thereby enabling performance optimization. Additionally, it tends to reduce design uncertainty, and ensure that the planned results can actually be implemented in later design flow. Interconnects become much more difficult to model and optimize for DSM chips, typically when the feature size is less than 180 nm, as the distributed nature of the interconnect need to be considered. Interconnect delay is roughly determined by the driver or gate resistance, the interconnect and loading capacitance, and the interconnect resistance [Cong et al 1996]. Interconnection of a net comprises a set of wire segments connecting all the pins of the net. Interconnects are often modeled as graphs, with the pins denoting the vertices, and a wire segment corresponding to an edge. Major objective of an interconnection of pins is the minimization of delay, or even minimizing the slack at the sink terminals that are driven by a source terminal. Thus, mere construction of Steiner trees may not be enough. In fact, construction of Steiner trees and achieving routability of all the nets itself is a problem. The most preferred delay estimator is the Elmore delay estimator, though linear and other estimators have also been used. One of the well-known problems in interconnect delay optimization for a net is the delay minimization for critical sinks [Boese et al 1995]. A recent work on interconnect planning appears in [R. Lu and C K Koh 2003] which considers global routing, repeater insertion and flip-flop relocation for early interconnect planning. One of the major concerns is the lack of a useful metric for measuring the performance of an interconnect architecture vis-à-vis electrical and material parameters. This has been addressed in [Dasgupta 2003], which proposes a compact and simple metric for measuring the interconnect performance. Global routing: The placement phase determines the exact locations of the circuit blocks and pins. Outcome of placement phase is a netlist, which defines the required interconnections. Space unoccupied by the blocks is a collection of regions to be used for routing. Global routing generates an approximate route for each net. On the other hand, detailed routing involves the actual assignment of the routing regions. The classical objective function used for global routing

algorithms is the total wire-length using the Manhattan metric. In the context of DSM regime, several new objectives that are often conflicting in nature, have to be considered. For instance, the minimization of routing length is often conflicting with the amount of congestion of the wires in a given area available for interconnection. Moreover, another important point of concern in such cases is the amount of crosstalk among adjacent wires. Post-placement optimization: Buffer insertion is widely recognized technology for improving VLSI interconnect performance. A recent prediction states that more than 800,000 buffers will be required designs in the 50 nm technology. Buffers used in the interconnect topology of VLSI designs increase the driving capability for long wires, and also serve for shielding the load capacitance of non-critical sinks from the critical source-sink paths. Buffers are placed in the device layers, thereby occupying some of the spaces available for the functional modules. Buffers can be placed in a distributed manner or as clusters. As design complexity increases, designers now make use of more and more IP cores, large memory arrays, and hierarchical components. These are imposing constraints or blockages to buffer insertions. This leads to new problems of blockage avoidance for buffer insertion [Cong et. al. 1996]. The interesting and critical aspect of the new issues in the DSM regime is that they are mostly conflicting in nature, and as such, no single objective function is capable of obtaining a design that is optimum in respect of all of them. One way to handle problems of this nature is to consider multi-objective functions. However, a problem with it is the generation of a large pareto-optimal front, i.e. a large set of non-dominating solutions. Moreover, the existing algorithms for multi-objective optimization are highly cumbersome. As such, in very recent times, some successful attempts have been made to apply Game Theoretic modeling to solve such problems in a lucid manner. The following Section briefly outlines these recent results, and highlights on the relative merits of such modeling.

4. Application of Game Theory to VLSI Physical Design From the above discussions, it appears that Game Theoretic modeling substantiated by the Nash equilibrium functions, may help in framing effective methodologies for solving problems with multiple objective functions. Recent problems in VLSI Design in general, and VLSI Physical Design in particular handle multiple and often conflicting issues, and attempt to arrive at a solution that is optimum for all the objectives considered. A natural way of handling such problems is the use of multi-objective solution methods, yielding pareto-optimal solution fronts. Problem with such methods is the generation of a large number of possible non-dominating solutions. In game theory, on the other hand, there can be at most one Nash equilibrium point that is optimum considering all of the objectives. Game Theory allows to provide alternative and effective methodologies in such cases. Only a few significant works reported in [Ranganathan and Murugavel 2003] and [Hanchate and Ranganathan 2006] are worth mentioning.

In [Ranganathan and Murugavel 2003], the authors propose a game theory based method for minimizing the average power of a circuit during scheduling in behavioral synthesis. The problem of scheduling in data-path synthesis is formulated as an auction-based non-cooperative finite game, for which solutions are developed on the basis of Nash equilibrium function. Each operation in the data-path is considered to be a player bidding for executing an operation in the given control cycle, with the estimated power consumption as the bid. A combined scheduling and binding algorithm is also developed using a similar approach in which the two tasks are modeled together such that the Nash equilibrium function needs to be applied only once to accomplish both the scheduling and binding tasks together. The combined algorithm yields further power reduction due to additional savings during binding. The work reported in [Hanchate and Ranganathan 2006] considers simultaneous optimization of multiple issues related to interconnect in the deep submicron (DSM) circuits. These issues include interconnect delay, power, and crosstalk noise, which are usually non-commensurate in nature. In this work, the authors develop a game-theoretic framework and multimetric optimization algorithms for the simultaneous optimization during wire sizing of (i) interconnect delay and crosstalk noise, and (ii) interconnect delay, power, and crosstalk noise. The wire sizing optimization problem is formulated as a normal form game model and the solution is obtained using Nash equilibrium. The nets connecting the driving cell and the driven cell are divided into net segments. The net segments within a channel are modeled as players and the range of possible wire sizes formed the set of strategies. The payoff function is modeled (i) as the geometric mean of interconnect delay and crosstalk noise in the case of first formulation, and (ii) as the weighted sum of interconnect delay, power, and crosstalk noise in the second formulation. The net segments are optimized from the ones closest to the driven cell towards the ones at the driving cell. The time and space complexities of the proposed wire sizing formulations are linear in terms of the number of net segments. Experimental results indicated that the algorithm performed significantly better than simulated annealing and genetic search. For the given problems, the paper also mathematically proves the existence of the Nash equilibrium solution. Since most of the recent problems of VLSI physical design inherently have to take care of multiple issues, these suggest the tremendous scope in applying game theoretic modeling and techniques to such multimetric design problems.

5. Conclusions and Future possibilities Game theoretic modeling takes into account what is best for a player with respect to every other player’s objectives and decisions. Goal is to find a solution that is fair and the best for all the players considering the various constraints of a problem. However, this requires some condition to be preserved among the strategies adopted by the different players and their payoff functions, as stated in Section 2.

The VLSI physical design problems are typically multi-objective optimization problems. The objectives are such that minimization of one, for instance, might tend to increase the value of the other and vice-versa. Thus, traditionally these problems are often solved considering multi-objective criteria, or by optimizing one of the objectives, and the others as constraints of the problem. According to ITRS 2004, feature size will scale down continually at the rate of 0.7 x per generation and reach 22 nm by 2008. As such, newer issues would pop up behaving in various different ways. In the current scenario, the several issues of wire delay, congestion, power generation and dissipation, crosstalk among the wires and noise, buffer placement, white space allocation in placement phase are some of the critical issues that need to be addressed in physical design of VLSI chips. Traditional techniques of application of meta-heuristic techniques for solving these design problems are well known, but are often quite cumbersome, and tend to give a large set of feasible solutions. On the other hand, the Game Theoretic modeling provides a compact modeling, and tends to provide the single best solution. Application of Game Theory to VLSI Physical Design problems have just begun, and is expected to gain a tremendous momentum in the near future. This paper tries to introduce some of the basic concepts of Game Theory, and how it can be used in solving the hard multi-objective problems of a well –known application area.

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