GaN HFET with p-type GaN Gate ... - IEEE Xplore

0 downloads 0 Views 567KB Size Report
A 1.5 A normally-off GaN transistor for power applications in p-type GaN gate technology with a modified epitaxial concept is presented. A higher threshold ...
CIPS 2010, March, 16 – 18, 2010, Nuremberg/Germany

Poster P 9

Normally-off AlGaN/GaN HFET with p-type GaN Gate and AlGaN Buffer Oliver Hilt, Arne Knauer, Frank Brunner, Eldad Bahat-Treidel and Joachim Würfl, Ferdinand-Braun-Institut, Leibniz-Institut fuer Hoechstfrequenztechnik, Gustav-Kirchhoff-Strasse 4, 12489 Berlin, Germany

Abstract A 1.5 A normally-off GaN transistor for power applications in p-type GaN gate technology with a modified epitaxial concept is presented. A higher threshold voltage is achieved while keeping the on-state resistance low by using an AlGaN buffer instead of a GaN buffer. Additionally, the AlGaN buffer acts as a back-barrier and suppresses source-drain punch-through currents in the off-state. P-GaN gate GaN transistors with AlGaN buffer will therefore yield higher breakdown voltages as compared to standard GaN buffer versions which results in an excellent VBr-to-RON ratio. The proposed normally-off technology shows save operation under elevated ambient temperature up to 200 °C without thermal runaway. In contrast to standard normally-on AlGaN/GaN HEMTs, a reverse diode operation is possible for offstate conditions which may enable improved inverter circuits.

1

Introduction

AlGaN/GaN HEMTs are generally promising candidates for switching power transistors due to their high breakdown strength and the high current density in the transistor channel giving a low on-state resistance, RON [1]. However, their inherent normally-on behavior would exclude them from most power-electronic applications. Recent attempts to convert AlGaN/GaN HEMTs into normally-off devices, using gate recess [2] or fluorine incorporation [3] showed limited applicability for power electronics due to their low threshold voltages Vth < +1 V, and their low gate swing of ~ 2 V. While a Schottky-type metal on the AlGaN barrier acts as gate for normally-on HEMTs, a p-type doped semiconductor as gate is able to deplete the transistor channel when unbiased, thus yielding a normally-off device. In the pGaN gate transistors presented here, the gate is of Mgdoped GaN with an ohmic contact for biasing. P-GaN gate GaN transistors combine the low on-state resistances, RON, known from AlGaN/GaN HEMTs with secure normallyoff operation, as required for applications in power electronics [4]. However, the required Vth > +1 V is often achieved by a low Al-concentration in the AlGaN barrier, giving a reduced electron density in the 2DEG of the transistor channel and compromising RON. Here, a low Al-concentration AlGaN buffer beneath the GaN channel is introduced to gain both, a high electron concentration in the 2DEG and a high Vth. Figure 1 sketches the basic transistor epitaxial design (inset) and shows the conduction band diagram for a p-GaN transistor

with a standard GaN buffer and with the Al0.05Ga0.95N buffer used here. The polarization charges at the interface between the AlGaN buffer and the GaN channel act as virtual p-type doping and support the p-GaN gate to drag the potential well of the transistor channel out of the Fermi level. Additionally, a back-barrier is created to suppress the electron punch-through for the closed transistor [5].

G S

p-GaN AlGaN (23% Al, 15 nm) GaN (10 nm)

D

AlGaN (5% Al)

Figure 1 Simulated band structure at the gate position for a device with GaN buffer (thin, blue) and a device with Al0.05Ga0.95N buffer (bold, red). Insert: schematic cross section of the p-GaN gate GaN transistor.

ISBN 978-3-8007-3212-8 © VDE VERLAG GMBH ∙ Berlin ∙ Offenbach

CIPS 2010, March, 16 – 18, 2010, Nuremberg/Germany

Poster P 9

0.5 +5 V

Median(Id) (A/mm)

0.4

0.3 +3 V

0.2

0.1 +1 V

0 0

Figure 2 Transfer characteristic (bold, red) and gate current (thin, blue) (median and 25%/75% percentiles for both) for 3.82 mm wide devices with lGD = 6 µm on a 3” wafer. The black dotted line represents 60°C ambient temperature condition.

2

Experimental

The devices have been processed on 3” SiC wafers. The MOCVD-grown p-GaN/AlGaN/GaN heterostructures consist of a nucleation layer, a 2 µm Al0.05Ga0.95N buffer, a 35 nm thick GaN channel and a 15 nm Al0.23Ga0.77N barrier. The Mg doped p-GaN was 110 nm thick with an effective doping of 3e17 cm-3. The gate is 1.4 µm long and 3.8 mm wide and processed with optical lithography. The sourcegate distance is 1 μm and the gate-drain distance lGD = 6 μm for the 3.8 mm wide device. Corresponding smaller devices with wG = 0.25 mm and gate-drain spacings between 2 and 18 µm have been processed for the breakdown voltage scaling tests. Ohmic source and drain contacts consists of a Ti/Al/Mo/Au metallization, annealed at 830 °C. The pGaN gate was metallized with a Ni/Au ohmic contact. The p-GaN epi layer was selectively plasma-etched, except for the gates. RTP annealing of any etch damage has been done at 450 °C. The devices were isolated by nitrogen implantation and are passivated with PECVD-deposited SiN.

3

5

10 Vds (V)

15

20

Figure 3 Output characteristic (median and 25%/75% percentiles) for 3.82 mm wide devices with lGD = 6 µm. VGS is indicated.

ambient as shown by the dotted line in Figure 2. The gate current in the on-state (defined as VGS = +5 V) is 0.4 µA/mm and thus 6 orders of magnitude below the drain current. A gate bias > +5 V still gives a higher drain current (and lower RON) but on the expense of an increased gate current. Figure 3 shows the median output characteristics. For VGS = +5 V, Idsmax is 0.41 A/mm or 1.5 A absolute. RON is 10.9 Ωmm. The breakdown strength, VBr, of the devices is determined with the drain leakage current reaching 1 mA/mm. VBr for different gate-drain spacings is displayed in Figure 4, showing a strong scaling of VBr between 65 V and 870 V with the gate-drain distance. Drain current punch-through through the buffer of the device is thus efficiently suppressed [5]. The median VBr of 195 V at lGD = 6 μm for the wG = 0.25 mm devices is the same as has been determined for the 1.5 A transistor with wG = 3.82 mm.

Results

To underline a certain maturity of the process technology, most presented results are median data over several 10 devices across the 3” wafer. Figure 2 shows the median of the transfer characteristics and of the gate current over the 3” wafer for devices with 3.82 mm gate width. The threshold voltage is Vth = +1.25 V and the sub-threshold leakage current at VGS = 0 V is 4 µA/mm. The magnitude of the sub-threshold leakage current is still determined by shallow traps. It gets reduced to 0.2 µA/mm at 60 °C

Figure 4 Breakdown voltage (median and 25%/75% percentiles) scaling for different gate-drain spacings. wG = 0.25 mm and VGS = 0 V.

ISBN 978-3-8007-3212-8 © VDE VERLAG GMBH ∙ Berlin ∙ Offenbach

CIPS 2010, March, 16 – 18, 2010, Nuremberg/Germany

Poster P 9

0.5

Median(Id) (A/mm)

(a) 0.4 VDS = 10 V

° 25

0.3

C

0.2

°C 200

0.1 0 0

1

2

3 Vgs (V)

4

5

6

0.5

Figure 5 Off-state drain (bold, red) and gate (thin, blue) leakage currents for a device with lGD = 18 µm and wG = 0.25 mm. VGS = 0 V. Figure 5 shows the off-state leakage current characteristic for a device with the largest gate-drain spacing of lGD = 18 µm. This device with RON (VGS = 5 V) = 17.6 Ωmm has a breakdown voltage of 870 V. Devices with lGD = 6, 8, 10, 12, 15 and 18 µm are benchmarked in the RON-vs.-VBr graph (Figure 6) against other reported normally-off GaN transistors. Top performance is demonstrated with RONA = 3.52 mΩcm2 and VBr = 870 V. The temperature dependence of the drain current Idsmax and of Vth is important for the thermal stability of the device as thermal runaway can be avoided by a negative temperature coefficient of the drain current. Figure 7 shows the transfer and output characteristics for ambients between 25 °C and 200 °C. The transistor size (0.25 mm gate width) was

Figure 6 Specific on-state resistance versus breakdown voltage for normally-off and normally-on GaN transistors. Si- and SiC-based devices are also included. The stars represent transistors of this work with wG = 0.25 mm. The gate lengths were 6, 8, 10, 12, 15 and 18 µm with increasing VBr.

Median(Id) (A/mm)

(b) 0.4

25

VGS = +5 V

°C

0.3 0.2

200 °C

0.1 0 0

2

4

6

8

10

Vds (V)

Figure 7 (a) Transfer characteristics and (b) on-state output characteristics (median and 25%/75% percentiles) at different ambient temperatures of 25°C, 60°C, 95°C, 130°C, 165°C and 200°C. The gate width of the transistors is 0.25 mm and lGD = 6 µm.

kept small to avoid strong self heating in the on-state. The threshold voltage with a temperature coefficient of -0.2 mV/K is essentially independent on temperature. The drain current reduces with temperature for the open transistor (1.3 mA/(mmK) temperature coefficient) and also for only partially opened conditions. The temperature coefficient for the on-state resistance is positive with 43 mΩmm/K. Current focusing and hot spots on limited sub cells of the transistor get thus avoided for all operating conditions. The devices can thus easily get assembled in parallel arrays for switching of larger currents. Operation under ambient- (and junction-) temperatures of 200 °C have been realized without any degradation, emphasizing the specific advantages of wide-bandgap GaN devices. The proposed p-GaN gate GaN transistor can be operated at reverse bias conditions without excessive gate current, see Figure 8. In contrast to the Schottky gate contact of normally-on GaN HEMTs, the current through the gate diode is limited due to the resistive nature of the used gate contact. The device has thus a diode-like characteristic at VGS = 0 V. This is of particular benefit when using the devices for high-side and low-side switches in inverter circuits where the current gets commutated between the

ISBN 978-3-8007-3212-8 © VDE VERLAG GMBH ∙ Berlin ∙ Offenbach

CIPS 2010, March, 16 – 18, 2010, Nuremberg/Germany

Poster P 9

5

0.5

+5 V

(a)

0.4

Median(Id) (A/mm)

0.3 0.2 0.1 0

0 V , +1 V

-0.1 -0.2 -0.3

0

V

-0.4 +5

V

-0.5 -0.6 -10

-5

0

5

10

15

Vds (V)

Median(Ig) (A/mm)

1e-3

(b)

8e-4 6e-4

+5

4e-4

V

2e-4 0e+0 -2e-4

0V

-10

-5

0 Vds (V)

5

10

15

Figure 8 (a) Output characteristic (median and 25%/75% percentiles) under forward and reverse drain bias conditions. VGS from 0 V to +5 V in 1 V steps. The corresponding gate currents are shown in (b).

[1] Y. Dora; A. Chakraborty, L. McCarthy, S. Keller, S. P. DenBaars, and U. K. Mishra, “High Breakdown Voltage Achieved on AlGaN/GaN HEMTs with Integrated Slant Field Plates”, IEEE Electron Device Lett. 27(9), pp. 713-715, 2006. [2] W. Saito, Y. Takada, M. Kuraguchi, K. Tsuda and I. Omura, “Recessed-Gate Structure Approach Towards Normally Off High-Voltage AlGaN/GaN HEMT for Power Electronics Applications”, IEEE Trans. on Electron Devices 53(2), pp. 356-362, 2006. [3] Y. Cai, Y. Zhou, K.J. Chen and K.M. Lau, “High Performance Enhancement-Mode AlGaN/GaN HEMTs Using Fluoride-Based Plasma Treatment”, IEEE Electron Device Lett. 26(7), pp. 435-437, 2005. [4] Y. Uemoto, M. Hikita, H. Ueno, H. Matsuo, H. Ishida, M. Yanagihara, T. Ueda, T. Tanaka and D. Ueda, „Gate Injection Transistor (GIT) - A Normally-Off AlGaN/GaN Power Transistor Using Conductivity Modulation“, IEEE Trans. on Electron Devices 54(12), p. 3393, 2007. [5] E. Bahat-Treidel, O. Hilt, F. Brunner, J. Würfl, and G. Tränkle "Punchthrough-Voltage Enhancement of AlGaN/GaN HEMTs Using AlGaN DoubleHeterojunction Confinement" IEEE Trans. on Electron Devices, vol. 55(12), pp. 3354-3359, 2008. [6] Y. Uemoto, T. Morita, A. Ikoshi, H. Umeda, H. Matsuo, J. Shimizu, M. Hikita, M. Yanagihara, T. Ueda, T. Tanaka and Daisuke Ueda, ”GaN Monolithic Inverter IC Using Normally-off Gate Injection Transistors with Planar Isolation on Si Substrate“, IEDM 2009 Tech. Digest., pp. 165-168, 2009.

two switches [6]. The freewheeling current of an inductive load may pass the closed switch due to its reverse diodelike characteristic. Adding an additional fast recovery diode (as needed for Si IGBTs) or using an internal body diode (as in Si MOSFETs) is not needed and switching losses may get reduced.

4

Literature

Conclusion

A normally-off GaN transistor for power applications with a low on-state resistance and high breakdown strength was presented. The combination of a p-type GaN gate with an AlGaN back-barrier yields in a sufficiently high threshold voltage for power electronic applications by maintaining the low on-state resistances known from AlGaN/GaN HEMT devices. A breakdown voltage of 870 V for 18 µm gate-drain spacing has been achieved. The VBr-to-RON ratio surpass the performance of silicon-based devices and belongs to the best normally-off GaN devices. The device is resistant against thermal runaway and can thus be used for parallel arrays for larger current handling devices. It can be operated at temperatures up to at least 200 °C. Due to its special gate module, the transistor can handle reverse-bias conditions as they may appear in switching operation.

ISBN 978-3-8007-3212-8 © VDE VERLAG GMBH ∙ Berlin ∙ Offenbach