Gate-All-Around Junctionless Nanowire MOSFET With ... - IEEE Xplore

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Nov 23, 2011 - Woo-Tae Park, Member, IEEE, and Dim-Lee Kwong, Fellow, IEEE. Abstract—We present n-type gate-all-around (GAA) junction- less nanowire ...



Gate-All-Around Junctionless Nanowire MOSFET With Improved Low-Frequency Noise Behavior Pushpapraj Singh, Navab Singh, Senior Member, IEEE, Jianmin Miao, Member, IEEE, Woo-Tae Park, Member, IEEE, and Dim-Lee Kwong, Fellow, IEEE

Abstract—We present n-type gate-all-around (GAA) junctionless nanowire field-effect transistor (JL-NWFET) along with low-frequency noise (LFN) with respect to channel doping and the gate bias voltage. Irrespective of doping level in the channel, which is the same as that of source/drain, the JL-NWFET shows approximately five orders of magnitude lower spectral noise than the inversion-mode counterpart. LFN in JL-NWFET is also found less sensitive to gate bias voltage and to the frequency. The superior LFN behavior in GAA JL-NWFET is attributed to the conduction of carriers inside the uniformly doped nanowire channel. JL-NWFET-based sensing elements can thus be suitable in physical transducers to maximize the detection limits. Index Terms—Gate-all-around (GAA), junctionless (JL), low-frequency noise (LFN), nanowire field-effect transistor (NWFET).



ANOWIRE field-effect transistors (NWFETs) in gate-allaround (GAA) architecture are a promising candidate for future CMOS electronics due to their ideal gate controllability, low leakage, and enhanced carrier transport property [1]–[4]. Nanowires and back-gated NWFETs have been studied as chemical and biochemical sensor elements [5], [6]. They have also been reported to have high piezoresistivity, offering their application as sensing element for physical sensors [7]. However, the high surface-to-volume ratio in nanowires, which improves sensitivity to any changes, makes them prone to noise, leading to reduced signal-to-noise ratios [8]. Recently, the junctionless (JL) FETs are proposed to overcome the challenges of forming junctions and to eliminate

Manuscript received July 29, 2011; accepted September 18, 2011. Date of publication October 26, 2011; date of current version November 23, 2011. This work was supported by the A*STAR Science and Research Council under Grant 0921480069. The review of this letter was arranged by Editor B.-G. Park. P. Singh is with the Institute of Microelectronics, Agency for Science, Technology and Research, Singapore 117685, and also with the Division of Engineering Mechanics, School of Mechanical and Aerospace Engineering, Nanyang Technological University, Singapore 639798 (e-mail: [email protected] N. Singh, W.-T. Park, and D.-L. Kwong are with the Institute of Microelectronics, Agency for Science, Technology and Research, Singapore 117685 (e-mail: [email protected]; [email protected]; [email protected] J. Miao is with the Division of Engineering Mechanics, School of Mechanical and Aerospace Engineering, Nanyang Technological University, Singapore 639798 (e-mail: [email protected]). Color versions of one or more of the figures in this letter are available online at Digital Object Identifier 10.1109/LED.2011.2169645

Fig. 1. (a) Schematic view of the n-type JL-NWFET. Nanowire channels have same doping type and concentration as source/drain. (b) Tilted-view SEM image of GAA JL-NWFET after the gate patterning.

the junction-related performance degradations [9], [10]. GAA architecture, in which the gate surrounds the channel body, is extremely suitable for fabricating JL devices as the gate will create/remove depletion from all sides to turn off/on the device. The full carrier depletion is possible even in highly doped nanowire. This letter concerns the n-type GAA JL-NWFETs and their low-frequency noise (LFN) characterization. LFN is found extremely low and nearly insensitive to gate bias voltage (full depletion to no depletion), doping levels, and operating frequency. Ultralow noise behavior makes JL-NWFET a potential candidate to maximize the signal-to-noise ratio for applications in physical transducers. II. D EVICE FABRICATION The JL-NWFETs were fabricated on 8-in p-type (100) silicon-on-insulator wafers with a top device layer of 117- and 145-nm buried oxide. Top Si was doped with arsenic (As) using ion implantation to make it n-type. The implant doses were chosen to yield uniform silicon doping concentrations ranging from 1.3 × 1018 to 6.7 × 1019 atoms · cm−3 in four different quadrants of the wafer. Silicon fins of a width of 60 nm (±10%) were defined through deep ultraviolet patterning and dry etch and then oxidized at 875 ◦ C for 5 h, which results in twin nanowires of diameter of ∼15 nm (variability up to ±3 nm), shown schematically in Fig. 1(a). After the nanowire formation, 4-nm SiO2 was thermally grown (reducing nanowire diameter to ∼10 nm), followed by 130-nm amorphous silicon (α-Si) by low-pressure CVD and BF2 doping at a dose of 1 × 1016 cm−2 . The gate electrodes were then patterned, and a standard metallization process completed the fabrication of JL-NWFET. Fig. 1(b) shows the tilted-view SEM image of the JL-NWFET after the gate definition. Inversion-mode GAA NWFETs were fabricated on separate wafers with the process flow described in previous work [11].

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Fig. 2. IDS –VGS characteristics of n-type GAA NWFET and JL-NWFET (doping in the fin is 6.7 × 1018 cm−3 ).

Fig. 3. Output (IDS –VDS ) characteristics of n-type GAA (a) NWFET and (b) JL-NWFET.

III. R ESULTS AND D ISCUSSION We characterized both the inversion-mode NWFET and JL-NWFET having 160-nm gate length and nanowire diameter d ∼ 10 nm. DC I–V characteristics were measured using a semiconductor parameter analyzer HP4156B. The LFN measurements were performed with a battery-powered SR570 low-noise current preamplifier and an HP35670A dynamic signal analyzer. Fig. 2 shows the transfer characteristics for both devices. They exhibit excellent electrostatic control with high ON/OFF ratio (> 107 ), low subthreshold slope (SS < 80 mV/dec), and ultrasmall drain-induced barrier lowering. JL-NWFET has more appropriate threshold voltage (VTH ) due to p++ doping in polysilicon gate.


Fig. 4. Threshold voltage of JL-NWFET as a function of fin doping concentration at VDS = 0.1 V.

Shown in Fig. 3(a) and (b) are the output characteristics of the NWFET and JL-NWFET devices, respectively. The JL device showed improved (1.76 versus 1.7) velocity saturation index (value of α in IDsat α(VGS − VTH )α ) as a result of reduced surface scattering due to the bulk conduction and lower vertical electric field. Fig. 4 shows the threshold voltage of JL-NWFET devices as a function of fin doping corresponding to implant doses of 1 × 1014 , 5 × 1014 , 1 × 1015 , and 5 × 1015 atoms · cm−2 , named as A, B, C, and D, respectively. As expected, the threshold voltage has decreased linearly with an increase in doping concentration. It is worth mentioning here that actual doping concentrations inside the nanowires may be slightly different from the fin as a result of segregation effect during the oxidation of ultrathin fin. Fig. 5 shows the frequency dependence of the measured drain-current noise spectral density (SID ) at different operating regimes (subthreshold to ON state) for the NWFET and JL-NWFET, both biased in linear regime VDS = 0.1 V. In NWFET [Fig. 5(a)], the noise spectral density shows about two-orders-of-magnitude change within a span of 0.4-V gate bias around VTH . It shows 1/f -like trend for inversion regime (VGS > VTH ), but less 1/f -like dependence in subthreshold (VGS < VTH ). The low noise in subthreshold is attributed to the electron conduction at the core of the wire, limiting the LFN to be caused mainly by mobility fluctuations [12]. With increasing gate voltage, the carriers move close to the silicon oxide interface, which adds the number fluctuation component to the mobility fluctuation and thus increases the LFN [8]. Fig. 5(b) shows the spectral noise in JL-NWFETs. As compared to NWFET, it showed about five orders of magnitude lower spectral noise. The 1/f and gate bias dependence are also weaker. Reduced LFN in GAA JL-NWFET is attributed to the favorable vertical electric field magnitude and orientation, and bulk conduction. Indeed, the vertical electric field changes sign—passes through zero—while switching the device from OFF to ON or vice versa [inset of Fig. 5(b)]. In subthreshold, the carriers travel at the core of the wire, and vertical field assists them to remain away from the channel oxide interface. Thus, the LFN in this case is expected to be limited by mobility fluctuations attributable to lattice scattering [13], similar to NWFET discussed previously. The similar LFN behavior for devices with different channel dopings [inset of Fig. 5(b)] infers that the dopants inside the channel do not contribute to the LFN



due to change in gate bias voltage. It provides opportunity to obtain higher signal-to-noise ratio even with higher drain current (VGS > VTH ). Channel doping showed wide tunability of threshold voltage without any influence on the LFN. This would allow further optimization of not only threshold voltage and noise but also the channel doping effects on the piezoresistive sensitivity to achieve higher resolution in strain sensing applications. ACKNOWLEDGMENT The authors would like to thank Dr. Y. Z. Xiong of IME, Agency for Science, Technology and Research, for the fruitful discussions. R EFERENCES

Fig. 5. Drain-current noise power spectral density (SID ) versus frequency at VDS = 0.1 V. (a) n-type NWFET. (b) n- type JL-NWFET. The left inset shows the electric field directions inside the channel with VGS < VTH and VGS > VTH . The right inset shows the effect of channel doping on the LFN.

[13]. Beyond threshold, the carriers conduct throughout the channel body with very little (much lower than the inversionmode device) vertical field, keeping the LFN low. Although such low LFN values have been reported earlier in buried channel devices [14], extremely weak 1/f dependence deserves further investigation. Furthermore, it is worth discussing here that the LFN behavior presented here for GAA JL-NWFET is different from the recently reported for trigate JL n-FET in [15]. In a JL trigate, channel starts to form at the bottom surface of the fin. Therefore, carriers always remain at the bottom interface (even in subthreshold) and thus get to see the interface scattering and the trapping and detrapping from that interface. On the other hand, the channel formation in a GAA device starts from the nanowire core and then expands toward the interface keeping the LFN limited to mobility fluctuations before the device is biased in strong accumulation. IV. C ONCLUSION A GAA JL nanowire n-type FET has been presented along with LFN performance. The verification of lower noise confirmed the feasibility of JL-NWFET as a promising sensing element. The carriers travel through the whole silicon channel body, having less interaction with the interface, resulting in much lower LFN compared to the inversion-mode counterpart. Unlike in NWFET, LFN in JL-NWFET varied less

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