Gate Oxide Evaluation by Characterisation of Oxide

Gate Oxide Evaluation by Characterisation of Oxide Breakdown

Twan Bearda

Gate Oxide Evaluation by Characterisation of Oxide Breakdown

Twan Bearda

CIP-GEGEVENS KONINKLIJKE BIBLIOTHEEK, DEN HAAG Bearda, Twan Gate Oxide Evaluation by Characterisation of Oxide Breakdown ISBN 90-365-1656-0 Universiteit Twente, Enschede, The Netherlands, 2001.

GATE OXIDE EVALUATION BY CHARACTERISATION OF OXIDE BREAKDOWN PROEFSCHRIFT

ter verkrijging van de graad van doctor aan de Universiteit Twente, op gezag van de rector magnificus, prof.dr. F. A. van Vught, volgens besluit van het College voor Promoties in het openbaar te verdedigen op vrijdag 16 november 2001 te 13.15 uur. door Twan Reinold Bearda geboren op 3 februari 1973 te Nijmegen

Dit proefschrift is goedgekeurd door: de eerste promotor: Prof.dr. P. H. Woerlee de tweede promotor: Prof.dr. H.Wallinga

Samenstelling van de promotiecommissie: Voorzitter en secretaris: Prof.dr. D. Feil Promotoren: Prof.dr. P. H. Woerlee

Universiteit Twente

Prof.dr. H. Wallinga

Universiteit Twente Philips Research Laboratories Eindhoven Universiteit Twente

Referenten: Dr. R. Schmolke Dr. M. M. Heyns

Wacker Siltronic AG Interuniversitair Micro-Elektronica Centrum vzw.

Leden: Prof. dr. ir. F. G. Kuper Prof. dr. J. C. Lodder Prof. dr. H. E. Maes

Universiteit Twente Philips Semiconductors Nijmegen Universiteit Twente Interuniversitair Micro-Elektronica Centrum vzw. Katholieke Universiteit Leuven

All the work described in this thesis was carried out at, and made possible by IMEC vzw., Leuven, Belgium.

Contents 1 Introduction 1.1 Failure of micro-electronic devices . . . . . . . . . . . . . . . . 1.2 Outline of the thesis . . . . . . . . . . . . . . . . . . . . . . . . 2 Definitions and methodology 2.1 Intrinsic tunnel current . . . . . . . . . 2.2 Oxide degradation . . . . . . . . . . . . 2.3 Oxide breakdown . . . . . . . . . . . . 2.3.1 Detection of breakdown . . . . 2.3.2 Hard Breakdown . . . . . . . . 2.3.3 Soft Breakdown . . . . . . . . 2.4 Experimental procedures . . . . . . . . 2.5 Accuracy of defect density calculations 2.5.1 Random defect distribution . . . 2.5.2 Defect clustering . . . . . . . .

. . . . . . . . . .

. . . . . . . . . .

. . . . . . . . . .

. . . . . . . . . .

3 Characterisation of breakdown phenomena 3.1 Influence of measurement system on breakdown 3.1.1 Experimental . . . . . . . . . . . . . . 3.1.2 Results . . . . . . . . . . . . . . . . . 3.1.3 Discussion . . . . . . . . . . . . . . . 3.1.4 Conclusions . . . . . . . . . . . . . . . 3.2 Charge transport after hard breakdown . . . . . 3.2.1 Experimental details . . . . . . . . . . 3.2.2 Experimental results . . . . . . . . . . 3.2.3 Device simulations . . . . . . . . . . . 3.2.4 Discussion . . . . . . . . . . . . . . . 3.2.5 Conclusions . . . . . . . . . . . . . . . 3.3 Comparison of Soft and Hard Breakdown . . . 3.4 Conclusions . . . . . . . . . . . . . . . . . . .

1

. . . . . . . . . .

. . . . . . . . . . . . .

. . . . . . . . . .

. . . . . . . . . . . . .

. . . . . . . . . .

. . . . . . . . . . . . .

. . . . . . . . . .

. . . . . . . . . . . . .

. . . . . . . . . .

. . . . . . . . . . . . .

. . . . . . . . . .

. . . . . . . . . . . . .

. . . . . . . . . .

. . . . . . . . . . . . .

. . . . . . . . . .

. . . . . . . . . . . . .

5 5 6

. . . . . . . . . .

9 9 11 12 13 14 14 15 17 17 19

. . . . . . . . . . . . .

23 24 24 24 26 29 30 30 31 34 39 40 40 41

4 Breakdown caused by metallic contamination 4.1 Experimental . . . . . . . . . . . . . . . 4.1.1 Contamination procedure . . . . . 4.1.2 Capacitor fabrication . . . . . . . 4.1.3 Analysis . . . . . . . . . . . . . 4.2 Results . . . . . . . . . . . . . . . . . . . 4.2.1 TXRF/AAS analysis . . . . . . . 4.2.2 SIMS analysis . . . . . . . . . . 4.2.3 Oxide morphology . . . . . . . . 4.2.4 Poly-silicon morphology . . . . . 4.2.5 Electrical measurements . . . . . 4.3 Discussion . . . . . . . . . . . . . . . . . 4.4 Conclusions . . . . . . . . . . . . . . . .

. . . . . . . . . . . .

5 Breakdown caused by substrate defects 5.1 Origin of void-related defects . . . . . . . . 5.2 Voids versus COP . . . . . . . . . . . . . . 5.3 Correlation between COP and oxide failure 5.3.1 Experimental . . . . . . . . . . . . 5.3.2 Results . . . . . . . . . . . . . . . 5.4 Oxide thickness dependence . . . . . . . . 5.4.1 Experimental . . . . . . . . . . . . 5.4.2 Results . . . . . . . . . . . . . . . 5.5 Conclusions . . . . . . . . . . . . . . . . . 6 Simulation of Crystal Originated Particles 6.1 Artificial COP . . . . . . . . . . . . . . 6.1.1 Fabrication . . . . . . . . . . . 6.1.2 As-etched ArtCOPs . . . . . . . 6.1.3 ArtCOPs and wafer treatments . 6.1.4 Deposited dielectrics . . . . . . 6.2 Computer simulations . . . . . . . . . . 6.2.1 Simulation of oxide growth . . 6.2.2 Simulation of field distortion . . 6.2.3 Results and discussion . . . . . 6.3 Conclusions . . . . . . . . . . . . . . .

. . . . . . . . . . . .

. . . . . . . . .

. . . . . . . . . . . .

. . . . . . . . .

. . . . . . . . . . . .

. . . . . . . . .

. . . . . . . . . . . .

. . . . . . . . .

. . . . . . . . . . . .

. . . . . . . . .

. . . . . . . . . . . .

. . . . . . . . .

. . . . . . . . . . . .

. . . . . . . . .

. . . . . . . . . . . .

. . . . . . . . .

. . . . . . . . . . . .

. . . . . . . . .

. . . . . . . . . . . .

. . . . . . . . .

. . . . . . . . . . . .

45 46 46 46 47 48 48 52 52 54 54 59 66

. . . . . . . . .

71 72 72 73 74 74 75 75 76 80

. . . . . . . . . .

. . . . . . . . . .

. . . . . . . . . .

. . . . . . . . . .

. . . . . . . . . .

. . . . . . . . . .

. . . . . . . . . .

. . . . . . . . . .

. . . . . . . . . .

. . . . . . . . . .

. . . . . . . . . .

. . . . . . . . . .

. . . . . . . . . .

85 86 86 87 93 95 96 97 99 99 107

7 Summary and conclusions 7.1 Characterisation of breakdown phenomena 7.1.1 Detection of breakdown . . . . . 7.1.2 Charge transport after breakdown 7.2 Extrinsic causes of breakdown . . . . . . 7.2.1 Metallic contamination . . . . . .

. . . . .

. . . . .

. . . . .

. . . . .

. . . . .

. . . . .

. . . . .

. . . . .

. . . . .

. . . . .

. . . . .

. . . . .

111 111 111 112 113 113

2

7.2.2

Void-related substrate defects . . . . . . . . . . . . . . 115

A Properties of metallic impurities

119

B List of publications

127

Nederlandse samenvatting 1 Karakterisatie van doorslag . . . . . 1.1 Detectie van doorslag . . . . 1.2 Ladingstransport na doorslag 2 Extrinsieke oorzaken van doorslag . 2.1 Metaal contaminatie . . . . 2.2 Kristalfouten in het substraat Thank you...

. . . . . .

. . . . . .

. . . . . .

. . . . . .

. . . . . .

. . . . . .

. . . . . .

. . . . . .

. . . . . .

. . . . . .

. . . . . .

. . . . . .

. . . . . .

. . . . . .

. . . . . .

131 131 131 132 132 132 133 135

3

4

Chapter 1 Introduction 1.1 Failure of micro-electronic devices Micro-electronic devices have become indispensable in everyday life. While the devices become more and more transparent and easier to use, they also become much more complex. This complexity is made possible by many improvements in design and technology. A consequence of this is an increased susceptibility of the devices to uncontrolled variations during the fabrication process. A chemical impurity or a dust particle can prevent a device from functioning correctly. For this reason, testing of devices has become an important part of the manufacturing process. Some test procedures screen devices before they leave the manufacturing plant. Often these tests are performed after artificial ageing of the device, e.g. by subjecting it to high electrical stress or high temperatures. Other tests provide an estimation for the period that a device can be used before it fails (device lifetime); these require either a reliable extrapolation model, or an experiencebased lifetime database. Device failures are usually classified in different categories. A standardised approach is lacking in this area, but a general classification scheme includes: package failures, due to faults in the device encapsulation; dielectric failures, or breakdown, when a dielectric loses its insulating properties; interconnect failures (e.g. corrosion of metal lines); design faults, relating to either mechanical or electrical aspects of the device; failures due to excessive environmental conditions: high temperatures, moisture... Which failure mechanism dominates depends on many factors such as the conditions of use and the fabrication process. A failure mechanism that is dominant in

5

one device may be insignificant in another [1, 2]. In MOS devices1 , one known failure mechanism is breakdown of the gate oxide. The occurrence of oxide breakdown has been studied since the 1960s, when MOS devices were first fabricated on a large scale. Breakdown can be caused by degradation of the oxide, or by defects already present in the oxide. In presentday devices, the number of defect-induced gate oxide breakdowns is required to be less than one per 10 cm2 [3]. The requirement does not specify which types of defects cause breakdown. While obviously every defect should be avoided, a more efficient approach is to investigate which defects are most harmful. The purpose of this thesis is to obtain such knowledge by deliberately introducing defects in the gate oxide in a systematic and controlled way. The philosophy behind this is to use oxide breakdown as a tool to monitor the gate oxide quality. The properties of the device after breakdown, and the conditions under which breakdown occurs, contain information about the cause of breakdown.

1.2 Outline of the thesis Chapter 2 starts with a short overview of charge conduction and degradation processes in gate oxides before breakdown. The differences between different modes of breakdown, Soft Breakdown and Hard Breakdown, are defined. Both the measurement methods for gate oxide characterisation and the procedures that are followed to analyse the results are described. It appears that Soft Breakdown can be described as a succession of events (chapter 3): after the initial breakdown, high stress levels may trigger a partial recovery of the gate oxide. The occurrence of this phenomenon depends on the measurement system, which includes the MOS device itself. An important aspect of post-breakdown conductance is the localised injection of charge carriers. This is considered in the latter part of this chapter, where we develop a model for charge transport after Hard Breakdown. A possible reason for early oxide failure is the presence of metallic contamination in the immediate neighbourhood of the oxide. When exposed to an oxidising atmosphere at high temperatures, contaminants at the substrate surface may form a chemical compound, diffuse into the bulk or evaporate. In chapter 4 we study a wide range of contaminants that may be present under normal processing conditions. Their behaviour during processing is investigated and compared to the gate oxide degradation. Crystalline defects, present in silicon substrates, have always been a source of concern for the gate oxide integrity. After a short review of different types of defects, it is demonstrated that mainly defects appearing at the substrate surface 1 These

devices are based on a layered Metal-Oxide-Semiconductor structure (hence the acronym). The conducting metal layer is called the ’gate’; the insulating oxide layer is the ’gate oxide’. Well-known examples of MOS devices are microprocessors and memory chips.

6

lead to gate oxide degradation (chapter 5). Experimental results show that the oxide degradation, in terms of breakdown field reduction, is a function of the oxide thickness; no degradation was observed for oxide thicknesses below 5 nm. One of the problems in studying substrate defects, is their uncontrolled shape and position. Chapter 6 presents a method to imitate such defects. The behaviour of these artificial defects during various treatments is investigated. MOS devices containing artificial defects appear to behave like devices that contain real-world defects. Using computer programs, oxide growth profiles and electric field distributions within the defect are simulated. The results agree well with the experimental findings and offer an explanation for defect-induced oxide breakdown. One of the trends in the micro-electronic industry is the introduction every two–three years of a new generation of devices [3]. New insights and new techniques are introduced continuously. Chapter 7 summarises the main results of this thesis, and briefly discusses the implications for future devices. Also some topics for further research are suggested.

References [1] M. Pecht and V. Ramappan. Are components still the major problem: a review of electronic system and device field failure systems. IEEE Trans. Components, Hybrids, and Manufacturing Technology, 15:1160–1164, 1992. [2] S.-M. Tang. New burn-in methodology based on IC attributes, family IC burn-in data, and failure mechanism analysis. In Proc. Ann. Reliability and Maintainability Symp., pages 185–190, Las Vegas, Nevada, USA, 1996. IEEE. [3] International technology roadmap for semiconductors, 1999.

7

8

Chapter 2 Definitions and methodology Silicon dioxide, SiO2 , is chemically stable and can be grown on silicon in a well controlled manner with a high quality interface. Its large bandgap of approximately 9 eV makes it a nearly perfect insulator. These are unique properties that are heavily relied upon in Metal-Oxide-Semiconductor (MOS) devices. Irregularities in the oxide film will cause a degradation of these properties; examples are surface roughness, interface charges and contamination of the surface with e.g. particles. These irregularities may result in ’weak spots’ or defects in the oxide and thus to oxide failure. This chapter discusses one type of failure, termed oxide breakdown. It is the result of a wear-out process that is briefly described in sections 2.1 and 2.2. In section 2.3 definitions and examples of different breakdown modes are given. Sections 2.4 and 2.5 describe the analysis methods that are used in this thesis.

2.1 Intrinsic tunnel current In ideal MOS devices, the gate oxide is a perfect insulator. In modern technologies, thin gate oxides are used with thicknesses down to 1 nm. Such oxides are no longer perfect insulators: when a voltage Vgate is applied to the gate, electrons have a finite probability of tunnelling through the oxide. Figure 2.1 shows two energy band diagrams for MOS structures, illustrating the two main tunneling mechanisms. Vox and φs are the potential drops in the oxide and the substrate, respectively, which are determined by Vgate and by material properties. EC ox is the oxide conduction band. If EC ox varies linearly with position x in the oxide, the electric field is uniform and given by

Eox x

1 dEC ox x q dx

Vox tox

(2.1)

ECB and EVB are the conduction and valence band in the substrate, and the dotted lines represent the fermi levels. 9

;

@BA C1D

E KBL M1N FHGJI

/1032415

m%npo y{z

|{} uv

O1P3QR1SHTVU

6173891:

q%rts

jdkBl

wx

W1X3YZ1[H\V]

g`hBi ^`_a

bdcfe

!"#%$

+(,-%.

&(')*

Figure 2.1: Energy band structure of an MOS structure. Left: FowlerNordheim Tunnelling; Right: Direct Tunnelling. Typical values for Φ B and mox are ΦB 3 ~ 15 eV, mox 0 ~ 3 m0 with m0 the free electron mass. The general relation between electron energy density and tunnel current is given by [1] ∞ ∞ q ∂E J dkl dkt f E f E T T (2.2) 2 2π h 0 ∂ kt 0 with kt and kl the transverse and longitudinal electron wave-vectors, E and E the energies of the incident and transmitted electrons, f E the Fermi distribution function and T the transmission probability. Following the method described in [2], applying the Wentzel-Kramers-Brillouin approximation, the latter can be written as

T t E E t exp

4π h

∆x

2mt E t 2mox E EC ox x dx

(2.3)

In the case of a homogeneous electric field, the position of the oxide conduction band EC ox varies linearly with x, so that expressions for the tunnel distance ∆x can be derived and the transmission probability calculated. If ∆x t ox (trapezoidal tunnel barrier) the current is termed Direct Tunnel (DT) current; if ∆x t ox (triangular barrier) Fowler-Nordheim Tunnelling (FNT) is said to occur [3]. Both situations are illustrated in figure 2.1. Using a first-order approximation yields expressions for the tunnel current densities JDT and JFNT :

10

JFNT

JDT

A Vox tox

1

1

qVox φB

2

exp

1 2

A Vox tox 2 exp

B

Vox tox

B

Vox tox

1

1

qVox φB

3 2

(2.4)

with q3 8π hφB

A B

4 2π 2mox 3 qh

φ

(2.5)

1 2

3 2 B

(2.6)

These expressions show that JFNT is independent of oxide thickness for a given electric field, but JDT is not. Figure 2.2 shows experimental I V curves with a clear transition between the two tunnelling regimes for various oxide thicknesses. In the figure, JDT increases by roughly a factor 2.5 for every Ångstrom decrease in oxide thickness. This illustrates the need for good control over oxide growth. In the preceding analysis it was assumed that the oxide conduction band E C ox varies linearly with x. In chapter 6 we will consider the case of non-planar electrodes, where the electric field is distorted and EC ox varies non-linearly with x.

2.2 Oxide degradation During high field stress, electrons tunnel through the gate oxide. Some of the electrons may be trapped in the oxide, especially in thicker oxides (t ox 5 nm). Other electrons release their energy in the substrate, resulting in the generation of carriers with a large kinetic energy. Hot holes, drifting back into the oxide, will be captured in the oxide and create electron traps [4, 5]. This model, illustrated in figure 2.3, is called the Anode Hole Injection model. In an alternative model, electron traps are created by hydrogen that is released from the Si/SiO 2 interface by injected electrons [6, 7, 8]. A third model considers that trap generation is only controlled by the high electric field in the oxide [9]. The traps and trapped charges in the oxide and at the interface have an effect on the oxide leakage. Trapping and detrapping of charges will locally alter the oxide electric field and, depending on the trap rate, introduce stochastic fluctuations in the oxide leakage. Similarly, neutral electron traps facilitate trap assisted tunnelling [10, 11, 12, 13]. This increase of the oxide leakage is termed Stress Induced Leakage Current (SILC).

11

/021

0

10

t (nm):

2

current density (A/mm )

ox

-3

10

3.7

3.4

3.2

2.8

354

2.5

+(,.-

!#"%$

-6

10

&('*) -9

10

4.0 4.3, 4.6

67

-12

10

0

5 10 oxide field (MV/cm)

15

Figure 2.3: Electron (e 8 ) injection and hole (h 9 ) generation, and their capture in the gate oxide according to the Anode Hole Injection model.

Figure 2.2: Experimental tunnel current densities as a function of the electric field for oxide thicknesses between 2.5 nm and 4.6 nm (as measured by ellipsometry). Clearly recognised are FNT, which is independent of tox , and DT, which strongly depends on tox . Experimental details are discussed in chapter 5.

It has been proposed [14] that, at the moment of breakdown, the density of neutral electron traps in the oxide has reached a critical value which depends on tox but not on the oxide electric field. This critical trap density has been interpreted as the condition where a so-called percolation network, consisting of traps, constitutes a conducting link between cathode and anode [14]. The subsequent breakdown event and its consequences are the subject of this thesis.

2.3 Oxide breakdown Breakdown is a ’sudden’ decrease of the oxide impedance, caused by the formation of localised, highly conductive spot. Breakdown may occur due to generation of defects during electrical operation of the device, or due to defects already present in the oxide. The first case is termed intrinsic breakdown, the latter extrinsic breakdown [15]. ’Defect’ in our definition is a local feature in the oxide that facilitates the formation of the conduction path. In chapters 4 and 5 we will consider two types of extrinsic defects. In the next sections we will discuss the detection of breakdown and define the characteristics of different types of breakdown. 12

+

Figure 2.4: Thévenin equivalent circuit of a measurement setup for device testing.

_ _

2.3.1 Detection of breakdown The investigation of oxide breakdown under normal operating conditions would introduce unreasonably long measurement times. Common practice is therefore to accelerate the degradation process by applying high stress levels. Meanwhile the current through the device under test, IDUT , or the voltage VDUT , is monitored. Figure 2.4 shows a simple Thévenin equivalent circuit of an experimental setup. ZDUT is the impedance of the device. Zi and V0 are the internal impedance and the voltage source of the measurement system, respectively. Depending on Z i , two situations are distinguished:

ZDUT : The stress level is determined by the voltage over the device, which is VDUT V0 . Changes in ZDUT are observed as a variation in the current IDUT . This is a Voltage Stress; breakdown is detected as an increase of IDUT .

Zi

Zi

ZDUT : The stress level is given as the current IDUT and is determined by Zi and V0 . Changes in ZDUT appear as a variation in VDUT . This is a Current Stress; breakdown is detected as a decrease of VDUT .

The stress level can be constant, or change as a function of time. We thus distinguish constant stress measurements and ramped stress measurements: Constant Voltage Stress (CVS) Ramped Voltage Stress (RVS)

Constant Current Stress (CCS) Ramped Current Stress (RCS)

In RVS/RCS measurements one obtains the current IBD and voltage VBD that cause breakdown in a device. This is particularly useful in situations where breakdown occurs over a wide range of stress conditions, for example if defects are present. The distribution of IBD or VBD allows to calculate the defect density, and to study the origin of the extrinsic oxide failure. In CVS/CCS measurements, the stress level is fixed. The parameter of interest is the time to breakdown t BD . The evaluation of tBD data is discussed in section 2.4. Depending on the magnitude of the change in IDUT or VDUT at the moment of breakdown, different types of breakdown are distinguished. These will be defined in the next sections.

13

CVS

10-12 0

gate voltage (V) 0 0

20

time (s) RVS

current (A)

100

area: 7.85 10-5 cm 2

Igate= -80 µA

-6 gate voltage (V)

10-6 0

CCS

5

Vgate= -4.7 V

current (A)

100

area: 1.27 10-3 cm 2

gate voltage (V)

area: 3.14 10-4 cm 2

time (s) RCS

20

area:

0 10-8

-6

-60 µA

1.27 10-3 cm 2

current (A)

100

Figure 2.5: Examples of Hard Breakdown observed in different measurement setups. Top: Constant Voltage Stress, Constant Current Stress; bottom: Ramped Voltage Stress, Ramped Current Stress. Oxide thickness was 3.2 nm.

2.3.2 Hard Breakdown Hard Breakdown (HBD) is the most severe breakdown event in thin oxides. It is generally assumed that, during HBD, excessive heat generation locally damages the gate oxide [16, 17, 18]. The barrier for electron tunneling is removed, and the breakdown spot essentially behaves as a contact between the gate electrode and the underlying substrate. As a result, the charge carrier transport through the breakdown spot is no longer determined by the tunnelling probability, but by factors such as series resistance, system compliance etc. Examples of HBD events in different measurement systems are shown in figure 2.5. In chapter 3 we will propose a model for charge carrier transport after HBD.

2.3.3 Soft Breakdown Compared to HBD, the conductivity increase after Soft Breakdown (SBD) is much smaller. For this reason, SBD is not easy to detect in RVS or RCS measurements, which typically require a scaling over a wide range of stress levels. Perhaps the most characteristic feature of SBD is the increase in noise in the leakage current (in case of CVS measurements) or gate voltage (for CCS measurements). The noise can actually be used as an SBD detection criterion [19]. 14

10 0

4.7

time (s)

10

4.6 0

CCS

5

area: 7.85 10-5 cm 2

voltage (V)

CVS area: 7.85 10-5 cm 2 Vgate= -4.7 V

voltage (V)

current (µA)

15

SBD1 Igate= -40 µA time (s)

20

CCS

SBD2 Igate= -40 µA

0 0

area: 7.85 10-5 cm 2

time (s)

20

Figure 2.6: Examples of Soft Breakdown during Constant Voltage Stress and Constant Current Stress. For CCS two breakdown modes are shown that were observed during the same measurement. Oxide thickness was 3.2 nm. Examples of SBD are shown in figure 2.6. It should be noted that during CCS we observe two SBD modes with different characteristics. As shown in figure 2.6, the conductivity increase is much larger in the SBD2 mode than in the SBD1 mode, while the noise strongly resembles random telegraph noise. SBD1 and SBD2 have also been called ’analog’ and ’digital’ mode SBD [20]. The noise behaviour is usually attributed to trapping-detrapping phenomena. The I V characteristics have been explained by three different models. The oxide thinning model assumes an effective oxide thickness reduction due to the creation of a ’physically damaged region’ [21]. It does not well describe the temperature dependence of the current. The variable range hopping model [22] has a better fit to the temperature dependence, but not to the I V characteristics. The best description is offered by the percolation model [23]; it assumes tunnelling of electrons through percolation paths, consisting of electron traps. The variable range hopping model and the percolation model describe the leakage current in terms of the degradation mechanism that precedes the breakdown; consequently, the implicit assumption is that during breakdown the local structure of the degraded oxide is not affected. However, in chapter 3 we will present experimental evidence of significant material restructuring after SBD1, which is in agreement with the suggestions in Ref. [20]. Therefore, the above models for post-SBD charge transport should be used with care.

2.4 Experimental procedures Capacitor fabrication In the experiments presented in this thesis, we used MOS capacitors with areas of roughly 10 8 5 – 10 8 1 cm2 . The gate oxides were grown in an ASM A400 cluster furnace, followed by deposition of a poly-silicon gate. The gate was doped using 15

B 9 or As 9 implantation, or P solid source diffusion. Electric contacts were formed by aluminium sputtering on the front- and backside of the wafer. Electrical measurements Manual measurements were done on Cascade Summit Probe Stations with an HP4156A or HP4145B parameter analyser. The gate voltage or current was monitored at a time interval of 100 ms, allowing 100 ms for charging of the capacitor at the start of the measurement. The first measurement point was used to compare with other measurements in order to check for oxide homogeneity. Automated measurements for yield evaluation on large sets of devices were done on HP4062/HP4063 measurement systems. At the start of each RCS measurement, the current was kept constant for several seconds to allow charging of the capacitor. The typical ramp rate used in our measurements (1 V/s) induces a displacement current density associated with the oxide capacitance of several µ A/cm2 . The additional displacement current due to parasitic cable and chuck capacitance (approx. 30 pF) is estimated to be less than 10 8 10 A. These values are insignificant at the stress levels used in this work. Reliability analysis For the analysis of the tBD data obtained in CCS and CVS measurements, we i plotted the cumulative failure probability Pi N 1 as a function of log tBD in a 9 Weibull distribution plot [15] using

1

ln ln

~ (2.7) 1 Pi In these expressions, N is the total number of data points and i is the rank number. This procedure results in a straight line with a slope β and tBD tBD0 at z 0 (corresponding with a failure probability of approximately 63%). In order to obtain accurate values for tBD0 and β , a straight line was fitted through the data points using least square error minimisation and a weight function [24]

zi

Wi

1 Pi ln 1 Pi

2

~

(2.8)

Yield analysis Automated ramped stress measurements were used to determine the yield for a set of devices. The VBD or IBD data points corresponding to oxide failure are plotted in a cumulative distribution plot. Each portion of the distribution showing a different failure rate corresponds to a different failure mechanism. From the fraction of extrinsic failures it is possible to calculate the corresponding defect density. For this, we developed the procedure that is presented in section 2.5. 16

Table 2.1: Notation k N λ pf x , ∆x

number of defective devices total number of tested devices number of defects per device failure probability expectancy, standard deviation

2.5 Accuracy of defect density calculations Most models for yield analysis apply to large samples. In most practical experimental work, such as presented in this thesis, small sample sizes introduce statistical sample-to-sample variation. In this section we derive expressions for the accuracy of the yield test under these conditions. First we consider the case of randomly distributed defects; next we use the experimentally determined distribution to estimate whether significant defect clustering occurs. Table 2.1 lists the used symbols.

2.5.1 Random defect distribution Yield is defined as the fraction of devices that does not fail under certain stress conditions. In our analysis, we assume that the defects, leading to device failure, are randomly distributed over the sample area, and that they are infinitely small compared to the device size. According to Poisson statistics, the failure probability p f of a device is then pf

1 e8

λ

(2.9)

with λ the number of defects per device (defect density). Our purpose is to find p f from the results of a yield test. From p f we will then calculate λ . In principle, the yield test is a binomial experiment. For a given p f , the probability of finding k failures in a set of N devices is given by

PB k p f

N k

pf k 1 pf N8

k

(2.10)

Using Bayes’ theorem, one can find the probability density function f p f k for p f . Figure 2.7 shows this function for two experiments where the yield is 30%. In both cases, a maximum appears at p f k N. However, both the spread and the asymmetry of the distribution vary with N. The mean value p f and variance ∆p f 2 are

17

Figure 2.7: Distribution function of the failure probability for finding 70% failures.

probability density f(p | k)

10 number of devices N=10 N=100

5

k/N=0.70

0

0

0.2 0.4 0.6 0.8 failure probability p

1

f

pf

∆p f 2 pf

k 1 N 2 k 2 k 1 N 3 N 2

(2.11) (2.12)

Equation 2.12 shows that the approximation p f k N only applies when k and N are sufficiently large. Combining equation 2.9 and f p f k , we find λ :

λk

1

0 k

1 1 i

∑N

i 0 1

∆λk2

ln 1 p f f p f k d p f

(2.13)

ln2 1 p f f p f k d p

0 k

∑N

i 0

2 λi 1 i

λk

λk

2

2

(2.14)

Figure 2.8 shows the variation of ∆λ λ as a function of λ . Clearly, for accurate defect density calculations, the yield should be around 30% (or λ 1). From figure 2.9 we derive a practical guideline for yield tests: the sample area should cover at least 100 defects to obtain a standard deviation below 10% on the calculated defect density.

18

1 ± ∆λ /

relative standard deviation ∆λ /

yield 1-k/N N=1000 N=100

98% 90% 70% 40% 5% 0%

1.5 1.0 0.5

number of devices: N=100 N=1000

0.0 0.01 0.1 1 10 mean number of defects per device

1.00

0.10

k/N=0.1 0.9

0.3 0.5

0.01 0 10

1

10

2

10

0.7

3

10

4

10

mean total number of defects N ·

Figure 2.8: Standard deviation of the defect density as a function of the defect density.

Figure 2.9: Relative standard deviation of the defect density as a function of the total number of defects in the sample area.

2.5.2 Defect clustering Equation 2.10, which describes the statistical spread in the failure count, can be used to detect defect clustering. In order to do this, the number of failures in the immediate vicinity of each device is counted, and the results are plotted in a histogram. If the defects are randomly distributed, this histogram fits equation 2.10 with appropriate values for N and p f . Defect clustering shows up as a deviation from this distribution. If two distribution functions are used in the fit, two different failure probabilities will be obtained, each relating to a different fraction of the sample area. Using the analysis in Section 2.5.1, the significance of the differences can be checked. The method does not evaluate the clustering probability for devices at the wafer edge; however it gets more accurate with increasing number of devices, it is independent of device structure and it is easily implemented in a computer program. Figures 2.10 and 2.11 give an example of the procedure. On the wafer in figure 2.10, no defect clustering was found, and the failure count histogram fits one single distribution function. On the wafer in figure 2.11, one region has a low yield due to a processing problem. Using two distribution functions, a fraction of 33% of the wafer is identified as having a low yield. The yield of the remaining part is comparable to the yield on wafer the wafer in figure 2.10. The values of the fit parameters are shown in table 2.2.

19

100%

frequency

75% 50% 25% 0%

0 1 2 3 4 5 6 7 failure count

Figure 2.10: Wafer without defect clustering. Left: failure bitmap; middle: clustering probability. The size of the circles indicates the relative probability of defect clustering. Right: failure count histogram with a fit to equation 2.10.

100%

frequency

75% 50% 25% 0% 0 1 2 3 4 5 6 7 failure count

Figure 2.11: Wafer with defect clustering. Left: failure bitmap; middle: clustering probability; right: failure count histogram with a fit to equation 2.10.

Table 2.2: Values of the parameters used to fit the histograms in figures 2.10 and 2.11.

area fraction

failure probability p f

defect density λ

figure 2.10

100%

0 ~ 04

0 ~ 02

0 ~ 03

0 ~ 02

figure 2.11

67% 33%

0 ~ 12 0 ~ 77

0 ~ 03 0 ~ 06

0 ~ 11 1 ~ 47

0 ~ 04 0 ~ 28

20

References [1] R. Tsu and L. Esaki. Tunneling in a finite superlattice. Appl. Phys. Lett., 22:562–564, 1973. [2] M. Depas, B. Vermeire, P. W. Mertens, R. L. van Meirhaeghe, and M. M. Heyns. Determination of tunneling parameters in ultra-thin oxide layer poly-Si/SiO2 /Si structures. Solid State Electronics, 38:1465–1471, 1995. [3] R. H. Fowler and L. Nordheim. Electron emission in intense electric fields. In Proc. Roy. Soc. Lond., volume 119, pages 173–181, 1928. copy from S. M. Sze (ed.), Semiconductor devices: pioneering papers, Singapore/New Jersey/London/Hong Kong (World Scientific) 1991. [4] I. C. Chen, S. Holland, K. K. Young, C. Chang, and C. Hu. Substrate hole current and oxide breakdown. Appl. Phys. Lett., 49:669–671, 1986. [5] K. F. Schuegraf and C. Hu. Metal-oxide-semiconductor field-effecttransistor substrate current during Fowler-Nordheim tunneling stress and silicon dioxide reliability. J. Appl. Phys., 76:3695–3700, 1994. [6] D. J. DiMaria and E. Cartier. Mechanism for stress-induced leakage currents in thin silicon dioxide films. J. Appl. Phys., 78:3883–3894, 1995. [7] D. Ziane, A. El-Hdiy, and G. Salace. Bidirectional stress on a p-metaloxide-silicon capacitor. J. Appl. Phys., 85:6593–6597, 1999. [8] J. Wu, E. Rosenbaum, B. MacDonald, E. Li, J. Tao, B. Tracy, and P. Fang. Anode hole injection versus hydrogen release: the mechanism for gate oxide breakdown. In Proc. Int. Rel. Phys. Symp., volume 38, pages 27–32, New York, NY, USA, 2000. IEEE. [9] L. Chen, C.-S. Kang, O. Oralkan, and D. J. Dumin. The search for cathode and anode traps in high-voltage stressed silicon oxides. J. Electrochem. Soc., 145:1292–1296, 1998. [10] B. Riccó, G. Gozzi, and M. Lanzoni. Modeling and simulation of stressinduced leakage current in ultrathin SiO2 films. IEEE Trans. El. Dev., 45: 1554–1560, 1998. [11] S. Takagi, N. Yasuda, and A. Toriumi. Experimental evidence of inelastic utnneling and new i-v model for stress-induced leakage current. In Tech. Dig. IEDM, pages 323–326, Piscataway, NJ, USA, 1996. IEEE. [12] E. Rosenbaum and L. F. Register. Mechanism of stress-induced leakage current in MOS capacitors. IEEE Trans. El. Dev., 44:317–323, 1997.

21

[13] J. Wu, L. F. Register, and E. Rosenbaum. Trap-assisted tunneling current through ultra-thin oxide. In Proc. Int. Rel. Phys. Symp., volume 37, pages 389–395, New York, NY, USA, 1999. IEEE. [14] R. Degraeve, G. Groeseneken, R. Bellens, J. L. Ogier, M. Depas, P. J. Roussel, and H. E. Maes. New insights in the relation between electron trap generation and the statistical properties of oxide breakdown. IEEE Trans. El. Dev., 45:904–911, 1998. [15] D. R. Wolters and J. J. van der Schoot. Dielectric breakdown in MOS devices part I: defect-related and intrinsic breakdown. Philips Journal of Research, 40:115–136, 1985. [16] K. Yamabe, K. Taniguchi, and Y. Matsushita. Thickness dependence of dielectric breakdown failure of thermal SiO2 films. In Proc. Int. Rel. Phys. Symp., volume 21, pages 184–190, New York, NY, USA, 1983. IEEE. [17] D. R. Wolters and J. J. van der Schoot. Dielectric breakdown in MOS devices part III: the damage leading to breakdown. Philips Journal of Research, 40:164–192, 1985. [18] R. Sugino, T. Nakanishi, K. Takasaki, and T. Ito. Identification of MOS gate dielectric breakdown spot using high selectivity Cl radical etching technique. J. Electrochem. Soc., 143:2691–2694, 1996. [19] G. B. Alers, B. E. Weir, M. R. Frei, and D. Monroe. J-ramp on sub-3nm dielectrics: noise as a breakdown criterion. In Proc. Int. Rel. Phys. Symp., volume 37, pages 410–413, New York, NY, USA, 1999. IEEE. [20] T. Sakura, H. Utsunomiya, Y. Kamakura, and K. Taniguchi. A detailed study of soft- and pre-soft-breakdowns in small geometry MOS structures. In Tech. Dig. IEDM, pages 183–186, Piscataway, NJ, USA, 1998. IEEE. [21] S. H. Lee, B. J. Cho, J. C. Kim, and S. H. Choi. Quasi-breakdown of ultrathin gate oxide under high field stress. In Tech. Dig. IEDM, pages 605–608, Piscataway, NJ, USA, 1994. IEEE. [22] K. Okada and K. Taniguchi. Electrical stress-induced variable range hopping conduction in ultrathin silicon dioxides. Appl. Phys. Lett., 70:351– 353, 1997. [23] M. Houssa, T. Nigam, P. W. Mertens, and M. M. Heyns. Model for the current-voltage characteristics of ultrathin gate oxides after soft breakdown. J. Appl. Phys., 84:4351–4355, 1998. [24] B. K. Chandrasekhar. Estimation of weibull parameter with a modified weight function. J. Mater. Res., 12:2638–2642, 1997. 22

Chapter 3 Characterisation of breakdown phenomena The results in this chapter have partly been published in: T. Bearda, P. W. Mertens, M. M. Heyns, H. Wallinga, P. Woerlee: Breakdown and recovery of thin gate oxides. Japanese Journal of Applied Physics 39 (2000) L582–L854. T. Bearda, P.W. Woerlee, H. Wallinga, M.M. Heyns: Charge transport after hard breakdown in gate oxides. submitted to: Solid State Electronics. T. Bearda, P. H. Woerlee, H. Wallinga, P. W. Mertens, M. M. Heyns: Current-Voltage characteristics of gate oxides after Hard Breakdown. 2001 International Conference on Solid State Devices and Materials (SSDM 2001).

Oxide breakdown is considered one of the most important types of failures of Metal-Oxide-Semiconductor (MOS) devices. For this reason, it has been studied under varying conditions and as a function of numerous parameters [1, 2, 3, 4]. These studies aim at accurate lifetime predictions, a better understanding of the degradation mechanism, or insight in the consequences for device operation. Different stress conditions or different processing conditions may result in different times to breakdown. Also, the post-breakdown conduction properties are not necessarily the same. As a result, the consequences for device operation may vary as well. The test conditions partly account for the occurrence of different breakdown modes, but a clear understanding is still lacking. Also, a consistent model for charge transport after breakdown is not available. Section 2.3 we have defined several breakdown modes. The present chapter discusses Soft Breakdown (SBD) and Hard Breakdown (HBD) in more detail. Section 3.1 describes how the measurement system can affect the detection of a breakdown event. Section 3.2 presents a model for charge transport after HBD. 23

3.1 Influence of measurement system on breakdown The occurrence of breakdown events was systematically investigated with different measurement setups and a high time resolution. The occurrence of different breakdown modes is found to depend on system impedance, stress level and device area. As a possible interpretation we suggest the presence of a highly conductive breakdown path at the moment of breakdown. By maintaining a sufficiently high voltage over the breakdown path, it can be partly annihilated, thus providing a recovery mechanism.

3.1.1 Experimental We fabricated Metal-Oxide-Semiconductor (MOS) capacitors on p p 9 epi wafers with 3 nm gate oxides grown at 800 C in dry oxygen. A poly-silicon gate was deposited and doped using P solid source diffusion. The gate areas were between 10 8 5 cm2 and 10 8 1 cm2 . Electric contacts were formed by aluminium sputtering on the front- and backside of the wafer. Processing was terminated by a forming gas anneal. Constant Current Stress (CCS) and Constant Voltage Stress (CVS) measurements were done manually on Cascade Summit Probe Stations with an HP4156A or HP4145B parameter analyser. Both instruments gave identical results. In some cases, the measurement setup was modified by adding an external series resistance or parallel capacitance. When comparing different measurement setups, care was taken to stress devices at identical stress levels, i.e. identical gate voltages and -currents. The gate voltage or current was monitored at time intervals of typically 100 ms. For monitoring at µ s time intervals, a Tektronix TDS 420 digital oscilloscope was connected in parallel over the device (CCS) or in series with the device with a shunting resistor of 100 Ω. All devices are stressed until the oxide voltage can no longer be maintained. During this time, several breakdown events can occur. We thus distinguish the first breakdown event (either HBD or SBD), termed firstBD, and the last breakdown event lastBD. The latter may be HBD, or SBD causing a significant gate voltage decrease (such as the SBD2 mode in figure 2.6). For the analysis of the tBD data obtained in CCS and CVS measurements we followed the procedure described in section 2.4.

3.1.2 Results In CVS measurements, short current peaks preceding SBD were detected with a digital oscilloscope. With parameter analysers, these peaks were not always observed due to the limited time resolution (figure 3.1). A similar phenomenon was seen in high time resolution CCS measurements, showing a significant voltage decrease and recovery during SBD1 events that were hardly detected with a 24

HP4156A ∆t=10ms

TDS420

TDS420

HP4145B -4.75

∆t=10µs

gate voltage (V)

current (µA)

-15

-10

-5

∆t=10ms

∆t=20µs

-4.50 SBD

SBD 0 50

-4.25 20

0 50 75 100 -50 time (s) time (ms)

Figure 3.1: SBD detected during CVS with a parameter analyser (left) and the same event detected simultaneously with a digital oscilloscope (right). The device area was 7.85 10 8 5 cm2 , Vgate 4 ~ 5 V. Note the different time scales.

25 time (s)

0

5 10 time (ms)

Figure 3.2: SBD detected during CCS with a parameter analyser (left) and the same event detected simultaneously with a digital oscilloscope (right). The device area was 7.85 10 8 5 cm2 , Igate 5 ~ 5 µ A. Note the different time scales.

lower time resolution (figure 3.2). The distribution of firstBD and lastBD in CCS and CVS are shown in figure 3.3. The distributions for firstBD are almost identical. This implies that the oxide degradation is not significantly different for both measurement methods. However, CCS measurements were always terminated by an SBD2 mode breakdown, resulting in significantly shorter measurement times compared to CVS measurements. Application of a voltage ramp after SBD2 often triggers a recovery mechanism, as shown in figure 3.4. This recovery always occurs at a gate voltage that lies between the pre-breakdown and post-breakdown gate voltages in the CCS measurement. The current-voltage characteristics after recovery are shown as well, along with those of devices that suffered SBD in a CVS measurement. Clearly, the I V characteristics after recovery exhibit a reduced leakage current compared to the situation before recovery, and they are very comparable to the case of SBD in CVS. Figure 3.4 shows that the dominating failure mode may be different for CVS and CCS measurements, even though the stress level is almost identical. One of the main differences between CVS and CCS measurement setups is the different internal impedance of the power source. In order to test the importance of this, we connected a series resistance RS to the device in CVS. Figure 3.5 clearly shows that, as RS increases to values above a few kΩ, the measurement 25

firstBD lastBD

1

initial SBD (CVS) SBD (CCS)

-3

-10

st

1 sweep -10 current (A)

ln( - ln(1-F))

nd

2 sweep

-6

0

-1

recovery

-9

-10

-12

-2

-10

device area: -5

SBD

-3 0 10

7.85 10 cm

HBD

101 102 time to breakdown (s)

2

-15

-10

103

0

-1

-2 -3 -4 gate voltage (V)

-5

Figure 3.4: I V curves of devices after SBD in CVS and CCS, and the intrinsic curve. The two curves after CCS were measured on the same device. Stress conditions: Vgate = 4 ~ 5 V (CVS), Igate = 5 ~ 5 µ A (CCS).

Figure 3.3: Weibull distributions of firstBD and lastBD. Device area: 3.14 10 8 4 cm2 ; stress conditions: Vgate = 4 ~ 5 V (CVS), Igate = 22 µ A (CCS).

time for the occurrence of lastBD is reduced to the limit for CCS measurements. Similarly, if a large 1 µ F capacitance is connected parallel over the device (i.e. a reduction of the system impedance), CCS measurement time is prolonged to values comparable with CVS. The statistical distribution of tBD values should scale with the device area [2]. To check this, the tBD values obtained on different device areas were plotted in a normalised Weibull plot (figure 3.6). The area scaling is correct for all lastBD events in CVS. In CCS however, large area devices systematically perform (relatively) better than small devices. This effect was also frequently observed in other experiments. Also, more SBD1 than SBD2 events occur at high CCS stress levels (figure 3.7). This dependency agrees well with the results of T. Tomita et al. [3].

3.1.3 Discussion Figures 3.1, 3.2 and 3.4 indicate that during soft breakdown a highly conductive breakdown path is created, that can be partly blocked or annihilated. The other results indicate that this ’repair mechanism’ is promoted by high stress levels. To explain this, we use the equivalent circuit of the measurement system shown in figure 3.8. The voltage Vox over the oxide immediately after breakdown depends 26

-2

2

-3

2

1.20 10 cm 1.26 10 cm

CVS

103

CCS

102

1

10

0

1kΩ 4.7kΩ 10kΩ S

BD count

SBD without recovery

4 2

101 102 time to lastBD (s)

6 4 2 SBD with recovery -90

CVS

103

Figure 3.7: Counts of SBD with and without recovery as a function of stress current. No HBD were observed. Ten capacitors (area 1.3 10 8 3 cm2 ) per condition were measured.

10

-80

CCS 6

Figure 3.6: Weibull distribution of lastBD for different areas in CCS and CVS. The distributions have been scaled to an area of 1 cm2 . Stress conditions: Vgate = 4 ~ 5 V (CVS), Igate Area= 70 mA/cm2 .

Figure 3.5: Effect of series resistance RS in CVS and parallel capacitance Cpar in CCS on 63% time to lastBD. Device area: 3.14 10 8 4 cm2 ; stress conditions: Vgate = 4 ~ 5 V (CVS), Igate = 22 µ A (CCS).

0 -70

8

0 100

0µF 0.1 µF 1µF

series resistance R parallel cap. Cpar

8

3.14 10-4 cm 2

B ln( - ln(1 - F)) - ln (Area)

63% time to lastBD

A

10

-100 -110 -120

stress current (µA)

27

power source

I

DUT

V +

R or C

C

R

R -

Figure 3.8: Equivalent circuit of the measurement system during breakdown. on the system impedance, including the internal resistance of the power source, the resistance RBD of the breakdown path, as well as the intrinsic oxide resistance Rox and capacitance Cox of the capacitor. The latter are functions of the device area and the stress level. In a CVS measurement setup, Vox after breakdown is determined by RBD RBD ); if RS is large compared to RBD (high system and RS (assuming Rox impedance) the decrease of Vox is significant. The same obviously holds for CCS measurements. However, if Rox RBD (large area devices), Vox will remain relatively high, even after breakdown. Stressing at higher stress levels has the same effect, because Rox decreases with stress level. The effect of a large capacitance Cpar is to maintain the gate voltage long enough to induce recovery. All these factors are consistent with our observations of a higher recovery probability at high stress levels. Figures 3.1 and 3.2 indicate that the duration of the high-conductivity state is several ms. This is long compared to the discharge time of the device, which is of the order of 100 ns for the devices in figures 3.1 and 3.2. When applying a voltage sweep after an SBD2 mode breakdown, recovery occurs at voltages above the post-breakdown voltage. The fact that recovery requires a certain stress time and stress level, suggests that the recovery is a wear out of the breakdown path. The wear out results in a ’failure’ due to open-circuit formation. This mechanism resembles switch-off behaviour of the conductive link in antifuse devices [5]. The latter originates from melting and contraction of the conductive link, resulting in an open-circuit. Such a process depends on the stress level as well as material properties. To test our hypothesis, capacitors were stressed in CVS or CCS mode until SBD occurred. The poly-silicon gate was subsequently etched off in a 85% TMAH solution at 85 C. Only in the case of SBD followed by recovery did the etching result in an etch pit as shown in figure 3.9; if no recovery occurred, no pit was observed. This means that recovery results in a region which is relatively easy to etch compared to the surrounding gate oxide. 28

Figure 3.9: Etch pit in the silicon substrate after removal of the poly-silicon gate. The capacitor has suffered only one SBD event in CVS mode and no HBD occurred.

3.1.4 Conclusions Breakdown events have been studied in a high time resolution measurement system and in systems with varying system impedances. The results show the existence of a highly conductive link at the moment of breakdown. If the conductive link is stressed at high enough levels, it may wear out within a few milliseconds. This is detected as an incomplete recovery of the gate oxide to a lower conductivity level. It means that high time resolution systems are more sensitive to breakdown events followed by recovery. The stress level of the conductive link depends on the stress level prior to breakdown, and on the system impedance. The latter includes includes parameters such as series resistance, power compliance, gate- and substrate doping and parasitic capacitance. It is therefore expected that the breakdown mode of a device depends on its function in a circuit as well as on the technology used.

29

3.2 Charge transport after hard breakdown HBD is a severe failure mode in gate oxides oxides. However it does not necessarily have a disastrous impact on the device performance [6]. Important factors are the position of the breakdown spot in the device, and the ’severity’ of the breakdown event. Being not well defined, no clear method exists to measure this ’severity’. It is often expressed in terms of a post-HBD resistance [4, 7, 8], measured at an arbitrarily fixed gate voltage. The post-HBD resistance is usually associated with the breakdown spot size. Recent publications also report a dependence on the position of the breakdown spot in the Metal-Oxide-Semiconductor (MOS) transistor [9]. Apparently, to understand the effect of HBD in MOS transistors, the complete device structure needs to be considered. As a preliminary to modelling HBD in transistors, we considered MOS capacitors. Current-voltage (I V ) characteristics after HBD were measured on devices with n 9 doped gate with different gate areas. The breakdown spot size was varied by applying a stress current to the device after breakdown. The I V characteristics depend on the gate area and the maximum current through the breakdown spot. We propose a simple model which allows to reproduce the results using a device simulator. The model explains why devices after HBD exhibit diode- or point contact behaviour, depending on electrode characteristics.

3.2.1 Experimental details The results described here were obtained on circular MOS capacitors with 3– 7 nm gate oxides grown at 800 C. The poly-Si gates were n 9 doped, the substrates were 100 n-Si or p-Si doped to a level of 1015 cm 8 3 . After etching of the gate area, boron was implanted (1011 cm 8 2 ) to prevent the formation of a permanent inversion layer adjacent to the device. All measurements were done with an HP4156A parameter analyser on a Cascade probe station. For each condition we show three I V curves to give an indication of the reproducibility of the results. Similar results were obtained with different gate oxide thicknesses. To produce HBD, a procedure was used that derives from detailed studies of antifuse devices [10]. A ramped current stress is applied as shown in figure3.10. After HBD, the gate voltage has decreased sufficiently to prevent multiple occurrences of HBD. With continued current ramping, the gate voltage follows a regular curve until fluctuations occur at stress current IP . In analogy with antifuse devices, we consider IP the discharge current that flowed through the breakdown spot during breakdown, and thus determined the breakdown spot size. Stress currents exceeding IP will widen the breakdown spot by melting silicon and silicon dioxide. To produce different breakdown spot sizes, the ramp is terminated at different current levels Imax .

30

100

-5

Figure 3.10: Example of Ramped Current Stress procedure to produce hard breakdown. The gate oxide thickness was 4.5 nm.

2

area: 1.96 10 cm -1

current (A)

10

10-2

Imax IP

10-3 HBD

10-4 10-5 10-6 0

-1

-2 -3 -4 -5 gate voltage (V)

-6

-7

3.2.2 Experimental results n 9 poly-Si / oxide / p-Si The I V characteristics of n 9 p capacitors after HBD are reproducible and show good diode behaviour for roughly Vgate VFB (VFB 0 ~ 8 V) (figures 3.11 and 3.12). The diode ideality factor is typically 1 ~ 03 0 ~ 01. For Vgate VFB the current depends on the gate dimensions. No dependence on Imax is seen in this voltage range. In contrast, if Vgate VFB the diode current varies with maximum stress current Imax but not with gate area. To investigate the dependence of the diode current on the device size, the contributions of the perimeter and area current components were calculated. The two components were extracted from measurements on devices with different perimeter area (P A) ratios by writing the total current Itot as

Itot A JA

P JP

(3.1)

with JA and JP the area and perimeter current densities. Plotting Itot A versus P A yields JA at the intercept of the y-axis. Both in low forward bias and in reverse bias, the perimeter current is found to dominate. The area current density in reverse bias has scattered values of 50 pA/cm2 JA 50 pA/cm2 (see figure 3.13 and table 3.1). We conclude that the perimeter current component is dominant, and that for a quantitative analysis the area current density is below the detection limit. n 9 poly-Si / oxide / n-Si Figures 3.14 and 3.15 show I V characteristics of n 9 n-Si capacitors after HBD; note that the currents are plotted on a linear scale. The reproducibility is comparable to the n 9 p devices. The I V curves are a-symmetrical and a weak dependence on the maximum stress current Imax is observed. The current 31

n+ poly-Si / oxide / p-Si


100

100 high forward

high forward -3

10

10-6

current (A)

current (A)

10

rcap= 200µm low forward

10-9 rcap = 25µm

rcap= 200µm -15

10

10

-2

-1 0 1 gate voltage (V)

2

-2

Figure 3.11: Experimental I V characteristics of n 9 p capacitors after HBD, with different device areas.

reverse

6

3

4

2 Vgate= -0.25 V

1

Table 3.1: current densities as obtained from figure 3.13.

| Itot | / Area (µA/cm2 )

4

2.0 V

Vgate

JA

Forward bias: -0.25 V -0.44 µ A/cm2

1.0 V

500 0 500 Perimeter / Area ratio

2

Figure 3.12: Experimental I V characteristics of n 9 p capacitors after HBD, with different maximum stress currents Imax .

5 Vgate=

Vgate=


forward

10 | Itot | / Area (nA/cm 2 )

low forward

10-9

reverse

Imax = 10mA

-15

0 0

Imax= 10mA

10-12

10

2

10-6

reverse

-12

8

Imax = 50mA

-3

0

Reverse bias: 1.0 V 0.045 nA/cm2 2.0 V -0.017 nA/cm2

Figure 3.13: Extraction of the area current density using devices with different areas.

32

+

+

n poly-Si / oxide / n-Si 2.0

n poly-Si / oxide / n-Si 2.0

accumulation

depletion

1.5

1.5 r r

1.0

= 25 µm

current (mA)

current (mA)

accumulation

depletion

cap

= 100 µm

cap

0.5 0.0

I

= 10 mA

I

= 20 mA

max

1.0

max

0.5 0.0

I

r

=20 mA

max

-0.5 -2


-0.5 -2

2

Figure 3.14: Experimental I V characteristics of n 9 n capacitors after HBD, with different device areas.

= 25 µm

cap


2

Figure 3.15: Experimental I V characteristics of n 9 n capacitors after HBD, with different stress currents.

levels are high compared to n 9 p devices, and the variation with gate voltage is slightly stronger than linear. In accumulation the curves show a dependence on the device size: the differential resistance decreases with increasing r cap (figure 3.16). Observation of the breakdown spot After HBD, the poly-silicon gate was etched in a 5% Tetramethyl Ammonium Hydroxide (TMAH) solution at 85 C. This etchant has a selectivity of roughly 1:1000 towards SiO2 [11]. For each capacitor that suffered one HBD event, Figure 3.16: Differential resistance of an n 9 n-Si capacitor after HBD as a function of rcap . The maximum stress current was Imax 10 mA. For each value of rcap three devices were measured.

104 I

= 20 mA

resistance dV / dI (Ω)

max

V

gate

=2V

103 ~r

-1 cap

2

10

10

100 rcap (µm)

1000

33

Figure 3.17: Etch pit in the silicon substrate after removal of the poly-silicon gate with TMAH. The breakdown spot is visible as an aperture in the remaining gate oxide over the etch pit. The gate oxide thickness was 3 nm. this procedure results in precisely one etch pit in the substrate (figure 3.17). The etch pit is covered by a thin membrane (the gate oxide) with an aperture of approximately 100 nm in diameter. We consider this aperture to be the remains of a silicon rich breakdown spot that can be etched with the TMAH solution. This observation is in agreement with reports on 6–15 nm gate oxides, where the breakdown spot is silicon-rich [12, 13] and has a radius of the order of 10– 100 nm [14, 15].

3.2.3 Device simulations We simulated charge transport after HBD using the device simulator MEDICI. Figure 3.18 shows the simulation structure with the simulation grid. Cylindrical symmetry was used to approximate the dimensions of an actual breakdown spot, and to obtain a circular capacitor as used in the experiments described above. The MOS capacitor has a radius rcap and a gate oxide thickness of 5 nm. The substrate thickness was 500 µ m; its radius was fixed at 104 µ m to account for current spreading. The doping is n-type or p-type at a level of 1015 cm 8 3 . The minority carrier lifetime was fixed at 1 ms, and Shockley-Read-Hall recombination was enabled. The carrier mobilities were described with the Lombardi model [16], which includes surface roughness scattering. As in our experiments, the simulated device has an n 9 poly-Si gate; p 9 doped gates can be analysed in an analogous manner. The gate is approximated by a 34

top electrode: n+ poly-Si

distance (nm)

0

gate oxide: tox=5nm bulk material: n-Si or p-Si

50

100 0

50 100 radial distance (nm)

150

bottom electrode: neutral

Figure 3.18: Simulation structure of a MOS capacitor with breakdown path. The substrate thickness is 500 µ m; the substrate radius is 104 µ m. At the right an equivalent gated diode structure is shown. dimensionless electrode with a work function potential of 4.17 V. This approximation is necessary to make optimal use of the limited number of grid nodes. If the doping levels of substrate and gate are comparable, the approximation is no longer valid and grid nodes should be assigned to the gate. From figure 3.17 we assume that the breakdown spot can be described as a poly-Si cylinder with radius rbd . Its doping is assumed to be n 9 like the gate; however, the results are not significantly different if moderately doped n-Si or p-Si is specified for the breakdown spot. The resulting simulation structure is actually a gated diode with the gate short circuited to the drain. n 9 poly-Si / oxide / p-Si The simulated I V curves (figure 3.19) show the same trends as the results in figures 3.11 and 3.12. The diode behaviour is due to the formation of a p n junction between the gate and the substrate during breakdown. There are three transport regimes: (1) In reverse bias a space charge region (depletion layer) is present in the substrate over the complete device area. Minority carriers may be present in this region due to diffusion from the neutral substrate, or due to a generation process in the region itself. The carriers are collected at the gate oxide and transported to the gate through the breakdown spot. (2) In low forward bias minority carriers are injected from the gate and distributed evenly under the gate oxide to form an inversion layer. This layer acts as an electrode from which carriers are injected into the substrate. The carriers then diffuse and recombine in the space charge region or the substrate.

35

n+ poly-Si / oxide / p-Si 10

high forward (accumulation)

Vgate = -0.75 V

rbd = 50 nm

10

10-6 current (A)

current (A)

10-3 -6

rcap= rcap=

500µm

5µm

10-9 -12

10


10-3

0

low forward (inversion)

reverse (depletion)

rbd= 50 nm

10-9

Vgate = -0.25 V

10-12

~rcap2 Vgate = 2 V

10-15 10-1

-15

10

-2


2

Figure 3.19: Simulated I V characteristics of an n 9 p-Si MOS capacitor after HBD.

~rcap

100 101 102 103 device radius rcap (µm)

104

Figure 3.20: Forward and reverse current in an n 9 p-Si MOS capacitor after HBD as a function of rcap .

The presence of a depletion- or inversion layer results in scaling of the current with device dimensions (figure 3.20). Minority carriers diffusing towards or from these layers participate in generation/recombination processes in the substrate. The contributing substrate volume thus depends on the minority carrier diffusion length. In small devices, the volume is mainly determined by the device edges; in larger devices it scales with area. This is recognised by the r cap 2 scaling of the current in figure 3.20. In case of low carrier lifetimes and rcap 2 scaling or generation/recombination in the space charge region, the onset of r cap will occur at smaller device sizes. (3) As the gate voltage approaches the flatband voltage, the inversion layer disappears, which shows as a kink in the I V curves. When the high forward bias regime is reached the minority carriers are locally injected from the breakdown path (figure 3.21). In high forward bias, the barrier to majority carrier flow has vanished, resulting in high level injection; the current is partly carried by majority carrier drift, which is sustained by a significant voltage drop in the substrate. It consequently varies with the breakdown spot radius rbd and the substrate resistivity ρ . The latter can be described as

ρ

1 q µn n

qµ p p

(3.2)

with n and p the electron and hole densities, and µn and µ p their respective mobilities. In thermal equilibrium, n and p are determined by the substrate doping 36

Figure 3.21: Current flowlines (each pair delineating 5% of the total current) in an n 9 p-Si MOS capacitor for varying gate voltages. For ease of interpretation, a cartesian coordinate system was used in these plots. The transition from low to high forward bias results in a more localised carrier injection.

0um 5um 0um

20um

n+ poly-Si / p-Si; Rcap=5um

level. Under high level injection conditions, they are significantly higher and also voltage and position dependent, which affects the variation of ρ with r bd . n 9 poly-Si / oxide / n-Si The simulated I V curves are shown in figure 3.22. The doping in the gate and the substrate are of the same type, so that carrier transport in the structure is dominated by majority carriers. The configuration resembles a semiconductor point contact [17]. In figure 3.17, rbd is approximately 50 nm. The mean free path of the charge carriers is expected to be of the same order, or even smaller due to the presence of defects. For this reason we believe that charge transport through the breakdown spot itself is dominated by diffusion. The drift current in the substrate is described by the spreading resistance RM which is given by Maxwell’s formula [18, §308]

ρ (3.3) 4r with ρ the substrate resistivity and r the radius of the contact. Maxwell’s formula was derived for conductors, but will prove useful in understanding the simulation results. In n 9 n devices, there are two transport regimes: RM

(1) In accumulation (positive bias) the carriers drift through the substrate towards the accumulation layer, and hence towards the breakdown spot. Assuming that the resistance of the breakdown spot is negligible, the cur37

Rcap=5um

n+ poly-Si / oxide / n-Si 0.5

rcap=

0.4 current (mA)

Rcap=50um

500 µm rbd= 50 nm

0.3

rbd= 25 nm

rcap=

0.2

5 µm

0.1 0.0 -0.1 -2

Rcap=500um depletion

0um

accumulation


5um 0um 20um n+ poly-Si / n-Si; Vgate=2V

2

Figure 3.22: Simulated I V characteristics of an n 9 n-Si MOS structure after HBD.

Figure 3.23: Current flowlines in an n 9 n device in accumulation. The accumulation layer resistance limits the current in large devices.

rent is thus limited by the accumulation layer- and substrate resistance. In small devices, the substrate resistance dominates. It is a combination of the 8 1 (see equation 3.3 with r rcap ), spreading resistance, which varies as rcap 8 2 ). In large devices, the accumulation layer and the bulk resistance (∝ π rcap resistance becomes significant. As a result only a limited area of the accumulation layer participates in carrier transport, and the total resistance becomes independent of rcap (see figure 3.23). We illustrate this rcap dependence further in figure3.24. In one set of simulations, 8 1 dependence. In other simulations, unrestrained current spreading results in a rcap the substrate radius was put equal to the device radius to prevent current spread8 2 . In both situations the resistance becomes ing. Now, the resistance varies as rcap independent of rcap in large devices, as argued above. (2) In depletion (negative bias) the majority carriers are locally injected from the breakdown path into the substrate. Figure 3.25 shows that a depletion layer below the gate oxide confines the spreading current. This results in a deviation of the resistance from the spreading resistance as given by equation 3.3. In large devices this confinement is stronger than in small devices, but this dependence vanishes for rcap larger than the lateral current spreading distance. 38

Vgate=-0.25V

n+ poly-Si / oxide / n-Si

8

resistance dV / dI (Ω)

10

107 ~rcap-2

no current spreading

Vgate = 2 V

Vgate=-1V

rbd= 50 nm

6

10

105

~rcap-1

104 103

Vgate=-2V

with current spreading

102 10-1

100 101 102 103 device radius rcap (µm)

0um

5um 0um 20um n+ poly-Si / n-Si; Rcap=15um

104

Figure 3.24: Differential resistance of an n 9 n-Si capacitor after HBD as a function of rcap .

Figure 3.25: Current flowlines in an n 9 n device in depletion. The spreading current confinement by the depletion layer is visible.

3.2.4 Discussion The trends of the measured I V curves are well reproduced in the simulations. This shows that the main concepts of our model, i.e. diode behaviour in n 9 p devices and point-contact behaviour in n 9 n devices, are correct. The rcap dependence of n 9 n devices in accumulation (figure 3.16) agrees with the theoret8 α ical trend in figure 3.24. The experimentally determined resistance varies as rcap (0 α 1). This corresponds to the transition region in figure 3.24 where the current is limited by a combination of substrate- and accumulation layer resistance. The rbd dependencies as observed in depleted n 9 n devices and n 9 p devices (in high forward bias) are only qualitatively understood. Due to the depletion layer, the effective radius of the charge injection point differs from r bd , and is expected to vary with voltage. Maxwell’s formula does not describe such nonlinearities. A detailed quantitative analysis is not relevant for the purpose of this work. This would also stretch the limits of our model, which assumes that the breakdown spot is an n 9 poly-Si cylinder. In reality, the breakdown spot and its surroundings may exhibit defects, varying material composition and dopant profiles, which would affect the actual conduction properties.

39

+

Figure 3.26: I V characteristics after HBD and SBD (no recovery) on areas of 1.3 10 8 5 cm2 and 2.5 10 8 4 cm2 . For SBD the stress currents were 3 µ A and 18 µ A; for HBD the maximum stress current was 2 mA. We measured three capacitors for each condition. Also shown is the initial curve of a 1.3 10 8 5 cm2 device.

10

-3

-5

2

-4

2

1.3 10 cm

HBD

10 current (A)

n poly-Si / p-Si

0

2.5 10 cm

10-6 SBD -9

10

-12

10

10-15 -2

initial

-1

0

1

2

gate voltage (V)

3.2.5 Conclusions We have studied the current-voltage characteristics of Metal-Oxide-Semiconductor capacitors after hard breakdown. Post-HBD characteristics were measured as a function of device size and substrate doping type. The breakdown spot size was varied by applying different maximum stress levels. Based on the experimental observations, we propose that the breakdown spot may be modelled as a highly conductive poly-silicon cylinder with a radius of typically 50 nm. Simulations based on this model agree well with the measured I V curves. The results show that if the gate and substrate have opposite doping types, the charge carrier transport resembles that of a diode. The presence of an inversion or depletion layer results in scaling of the current with device area. If gate and substrate have the same doping type, the breakdown spot shows characteristics of a diffusive point contact. In this case, the current scales with device dimensions in accumulation.

3.3 Comparison of Soft and Hard Breakdown Having developed a model for charge transport after HBD, the question arises whether charge transport after SBD can be described in similar terms. SBD differs from HBD in the lower conductivity and the higher noise level, but an important similarity is the localised breakdown spot. As with HBD, the accumulation and inversion regimes are likely to be reflected in the I V curves. Figure 3.26 shows I V curves of devices after HBD plotted together with curves after SBD without recovery, as measured on devices with n 9 gate and pSi substrate. No significant difference between SBD and HBD exists in reverse bias. This means that in reverse bias minority carrier generation limits charge transport, both for SBD and HBD. In forward bias, the I V curves after HBD and SBD differ significantly. 40

In the high-injection regime (Vgate VFB ), the charge transport after HBD is limited by the breakdown spot size, even though the resistivity of the breakdown spot was assumed negligible (section 3.2.2). The spot size is determined by the maximum power dissipation. In the case of SBD, the leakage current remains low until the onset of the high-injection regime, after which the current increases. According to the model for HBD, part of this current is carried by holes. This agrees with observations of a large hole current increase after SBD [19, 20]. Figure 3.4 shows that the SBD breakdown path becomes unstable as the gate voltage approaches its pre-SBD value. This suggests that the breakdown spot characteristics in high-injection are still determined by power dissipation. The power dissipation is dominated by the capacitor discharge during the breakdown, which is not well controlled. This may explain the weak area dependence and the scattered results. The model of section 3.2.2, when applied to the case of SBD, does not contradict the experimental results. However, the conductivity fluctuations show that the assumption of negligible breakdown path resistivity may not be applicable. As noted in chapter 2, various models exist for post-SBD leakage: the oxide thinning model, [19], the variable range hopping model [21], and the percolation model [22]. The latter is most successful in describing the temperature and voltage dependence of the leakage current.

3.4 Conclusions In this chapter we have studied Soft Breakdown (SBD) and Hard Breakdown (HBD) in gate oxides. We have shown that, after SBD, the breakdown path may wear out at high enough stress levels. In typical tests, this recovery phenomenon depends on the system impedance after breakdown, which includes the breakdown path and the substrate. Next, we have developed a model that describes charge transport in Metal-Oxide-Semiconductor structures after HBD; this model fits the measurements well. When applied to SBD, the model does agrees with the observations; yet it needs an additional mechanism that limits the conductivity of the breakdown spot itself and that explains the conductivity fluctuations.

41

References [1] K. Okada. Extended time dependent dielectric breakdown model based on anomalous gate area dependence of lifetime in ultra thin silicon dioxides. Jpn. J. Appl. Phys., 36:1443–1447, 1997. [2] R. Degraeve, J. L. Ogier, R. Bellens, Ph. Roussel, G. Groeseneken, and H. E. Maes. On the field dependence of intrinsic and extrinsic timedependent dielectric breakdown. In Proc. Int. Rel. Phys. Symp., volume 34, pages 44–54, New York, NY, USA, 1996. IEEE. [3] T. Tomita, H. Utsunomiya, T. Sakura, Y. Kamakura, and K. Taniguchi. A new soft breakdown model for thin thermal SiO2 films under constant current stress. IEEE Trans. El. Dev., 46:159–164, 1999. [4] B. Kaczer, R. Degraeve, N. Pangon, and G. Groeseneken. The influence of elevated temperature on degradation and lifetime prediction of thin silicondioxide films. IEEE Trans. El. Dev., 47:1514–1521, 2000. [5] S. Yoon and A. Iranmanesh. Investigation of wafer level reliability of amorphous Si antifuses for high density FPGA’s. In Int. Symp. VLSI Technology Digest of Technical Papers, pages 190–194, Piscataway, NJ, USA, 1995. IEEE. [6] B. Kaczer, R. Degraeve, G. Groeseneken, M. Rasras, S. Kubicek, E. Vandamme, and G. Badenes. Impact of MOSFET oxide breakdown on digital circuit operation and reliability. In Tech. Dig. IEDM, pages 553–556, New York, NY, USA, 2000. IEEE. [7] J. Suñé, E. Miranda, M. Nafría, and X. Aymerich. Point contact conduction at the oxide breakdown of MOS devices. In Tech. Dig. IEDM, pages 191– 194, Piscataway, NJ, USA, 1998. IEEE. [8] H. Satake and A. Toriumi. Dielectric breakdown mechanism of thin-SiO 2 studied by the post-breakdown resistance statistics. In Int. Symp. VLSI Technology Digest of Technical Papers, pages 61–62, Piscataway, NJ, USA, 1999. IEEE. [9] R. Degraeve, B. Kaczer, A. De Keersgieter, and G. Groeseneken. Relation between breakdown mode and breakdown location in short channel NMOSFETs and its impact on reliability specifications. In Proc. Int. Rel. Phys. Symp., volume 38, New York, NY, USA, 2000. IEEE. [10] G. Zhang, C. Hu, P. Y. Hu, S. Chiang, S. Eltoukhy, and E. Z. Hamdy. An electro-thermal model for metal-oxide-metal antifuses. IEEE Trans. El. Dev., 42:1548–1558, 1995. 42

[11] J. T. L. Thong, W. K. Choi, and C. W. Chong. TMAH etching of silicon and the interaction of etching parameters. Sensor and Actuators, A63:243–249, 1997. [12] M. Kimura and H. Koyama. Mechanism of time-dependent oxide breakdown in thin thermally grown SiO2 films. J. Appl. Phys., 85:7671–7681, 1999. [13] E. Hasegawa, A. Ishitani, K. Akimoto, M. Tsukiji, and N. Ohta. SiO 2 /Si interface structures and reliability characteristics. J. Electrochem. Soc., 142: 273–282, 1995. [14] R. Sugino, T. Nakanishi, K. Takasaki, and T. Ito. Identification of MOS gate dielectric breakdown spot using high selectivity Cl radical etching technique. J. Electrochem. Soc., 143:2691–2694, 1996. [15] S. Ikeda, M. Ikihara, H. Uchida, and N. Hirashita. Cross-sectional transmission electron microscope studies on intrinsic breakdown spots of thin gate oxides. Jpn. J. Appl. Phys., 36:2561–2564, 1997. [16] C. Lombardi, S. Manzini, A. Saporito, and M. Vanzi. A physically based mobility model for numerical simulation of nonplanar devices. IEEE Trans. Computer-Aided Design, 7:1164–1170, 1988. [17] J. W. H. Maes. Microstructural and electrical properties of silicon point contacts. PhD thesis, Technical University Delft, 1999. [18] J. C. Maxwell. A treatise on electricity & magnetism. Clarendon Press, 3 rd edition, 1891. [19] S. H. Lee, B. J. Cho, J. C. Kim, and S. H. Choi. Quasi-breakdown of ultrathin gate oxide under high field stress. In Tech. Dig. IEDM, pages 605–608, Piscataway, NJ, USA, 1994. IEEE. [20] F. Crupi, R. Degraeve, G. Groeseneken, T. Nigam, and H. E. Maes. On the properties of the gate and substrate current after soft breakdown in ultrathin oxide layers. IEEE Trans. El. Dev., 45:2329–2334, 1998. [21] K. Okada and K. Taniguchi. Electrical stress-induced variable range hopping conduction in ultrathin silicon dioxides. Appl. Phys. Lett., 70:351– 353, 1997. [22] M. Houssa, T. Nigam, P. W. Mertens, and M. M. Heyns. Model for the current-voltage characteristics of ultrathin gate oxides after soft breakdown. J. Appl. Phys., 84:4351–4355, 1998.

43

44

Chapter 4 Breakdown caused by metallic contamination The results in this chapter have partly been published in: T. Bearda, S. De Gendt, L. Loewenstein, M. Knotter, P. Mertens, M. Heyns: Behaviour of metallic contaminants during MOS processing. Proceedings of the Fourth International Symposium on Ultra Clean Processing of Silicon Surfaces (UCPSS 1998). Solid State Phenomena 65-66 (1999) 11–14. T. Bearda, P. H. Woerlee, H. Wallinga, P. W. Mertens, M. M. Heyns: Current-Voltage characteristics of gate oxides after Hard Breakdown. 2001 International Conference on Solid State Devices and Materials (SSDM 2001).

The most frequent process step in device fabrication is wafer cleaning. The purpose of cleaning is to obtain a wafer with a sufficiently low level of residues before the subsequent process step. Examples of common residues are metallic or organic impurities, and small oxide- or nitride particles. They may deposit on the wafer through contact with process equipment or chemicals, and through the ambient. Especially metallic impurities are known to degrade the quality of gate oxides. Examples of sources for metallic contamination are deionised water (Ca, Mg), stainless steel (Fe, Mn, Ni, V, Cr) and materials for silicides (Co, Pt, Ti). Also, materials that are considered for use in high-k dielectrics pose an additional risk for conventional gate oxides (Bax Sr1 x TiO3 , PbZrx Ti1 x O3 , Ru). Some of 8 8 these contaminants may be relatively harmless, while others have a large impact. For many contaminants the effect on gate oxide integrity has been investigated to some extent. The common contaminants Fe, Cu and Ni are relatively well understood; however, little is known about high-k related contamination. A complicating factor is that the experiments that are described in the various publi-

45

cations are carried out under different conditions. The methods of contamination vary, as well as processing conditions and analysis methods. This complicates comparison of different publications. This chapter systematically investigates the behaviour of metallic contaminants. Appendix A lists these contaminants, some of their compounds, their vapour pressures and the expected solid solubilities and diffusivities in silicon. For all contaminants identical processing conditions and analysis methods were applied. Special attention is paid to the evaluation of the contamination at different stages during processing. An important technique for this is Total Reflection X-Ray Fluorescence (TXRF). The TXRF response is found to depend on the wafer treatments, which complicates interpretation of the measurement results. Also Metal-Oxide-Semiconductor (MOS) capacitors were fabricated to study the effect on gate oxide breakdown. The results are interpreted in terms of redistribution of the contamination in the MOS structure. The systematic approach allows a direct comparison of the impact of the different contaminants.

4.1 Experimental 4.1.1 Contamination procedure For the experiments described in this chapter we used 150 mm and 200 mm p-Si 100 wafers. Prior to processing, all wafers received an IMEC clean [1], with a final rinse in ozonated water to obtain a hydrophilic surface. For each contaminant under study, a 1000 ppm AAS or ICP standard solution was diluted to 0.1 ppm or 1 ppm and acidified with 0.5 M HCl or HNO3 . The freshly made solution was applied to the wafers, which were then spun dry at 3000 rpm after a waiting time of 90 s. As reference conditions we included clean solutions and blank wafers that received no spinning treatment.

4.1.2 Capacitor fabrication Within two hours after contamination, the wafers were loaded into a cluster furnace with a nitrogen purged load-lock. In this way, organic contamination is reduced. The temperature was ramped to 800 C in 3% O2 ; the gate oxide was grown in pure O2 to a thickness of 4.5 nm. 450 nm poly-silicon was deposited in the same cluster at a temperature of approximately 610 C. The gate was doped with phosphorous solid source diffusion to a level of approximately 10 20 cm 8 3 . MOS capacitor structures were fabricated with areas ranging from 0.13 mm 2 to 16 mm2 . The regions adjacent to the gate areas were implanted with 1011 cm 8 2 boron to prevent the formation of a surface inversion layer.

46

4.1.3 Analysis Contaminant evaluation • Direct TXRF The surface contamination was measured by means of Total Reflectance X-ray Fluorescence (TXRF) on an Atomika 8010 instrument. The samples were illuminated from a Molybdenum tube under an incident angle of 1.3 mrad with respect to the surface plane (critical angle for total reflection: 1.7 mrad). This is the so-called iso-kinetic angle which yields a similar response for particle-type and film-type contamination. The detection limit for TXRF measurements is typically 1010 1012 atoms/cm2 . In the following, direct TXRF is abbreviated as D-TXRF. • Droplet Collection To lower the detection limit of D-TXRF, the surface contamination is concentrated into a smaller volume. The wafer is brought into a saturated HF ambient, which removes native or thermal oxide layers and makes the wafer hydrophobic (vapour phase decomposition, VPD). By scanning a droplet over the wafer using an automated scanning tool, a fraction of the total contamination can be collected (droplet collection, DC). This fraction is termed the Collection Efficiency CE. We used 50 µ l droplets of an acid mixture (HF/H2 O2 /H2 O = 1/3/100). After drying the droplet on the wafer, its content is measured. It was always checked that the TXRF measurement spot was larger than the dried droplet. If S0 is the area of the measurement spot and CDC the concentration in this area after droplet collection, then the number of contaminant atoms S0 CDC can be written as S0 CDC

S0 CMt

SW S0 CE CMt

(4.1)

SW is the wafer area, and CMt is the contaminant concentration on the wafer prior to droplet collection. In practice, CDC CMt and SW S0 . With known collection efficiency CMt

S0 CDC SW CE

(4.2)

If CMt is known from independent D-TXRF measurements, this equation can also be used to determine CE. An alternative method to determine CE is to measure the residual concentration next to the dried droplet. This concentration is a fraction 1 CE of the surface concentration before VPDDC. The VPD-DC-TXRF technique has a detection limit that is about 1–2 orders of magnitude lower compared to D-TXRF. Note that the procedure 47

collects the contaminants at the oxide/air interface, as well as the contaminants in the oxide and at the silicon/oxide interface. • Atomic Absorption Spectroscopy (AAS) TXRF has a low sensitivity to light elements such as Mg. For this case, the contamination was collected using the Droplet Collection procedure described above. The contamination in the droplet was then analysed by Graphite Furnace Atomic Absorption Spectroscopy (AAS, Perkin Elmer 4110 ZL). The Mg detection limit of this technique is approx. 108 atoms/cm2 . Other characterisation methods • Surface roughness and particle contamination during processing were monitored by means of a light scattering tool (Censor ANS-100). • The surface roughness after oxidation was measured with Atomic Force Microscopy (AFM) on a Nanoscope III instrument in tapping mode. • To evaluate diffusion of contaminants into the bulk of a wafer, Secondary Ion Mass Spectroscopy (SIMS) measurements were performed on MOS structures. • The diode leakage current of capacitors after breakdown was measured as a measure for the minority carrier lifetime (see chapter 3). • Ramped voltage stress was applied to MOS capacitors to investigate the reduction of gate oxide integrity (GOI) due to contamination. The failure criterion was a breakdown voltage below 5 V, or alternatively a leakage current larger than 10 8 7 A at voltages below 3 V. The corresponding defect density will be termed GOI defect density.

4.2 Results 4.2.1 TXRF/AAS analysis Surface contamination before oxidation The metal concentrations on the wafer after contamination are shown in figure 4.1. For some conditions the contamination level was below the detection limit of D-TXRF, so that we had to apply the VPD-DC method (see below). When plotted as a function of the metal concentration in the spinning solution, the surface contamination exhibits a linear dependence which, within experimental error, is identical for the different contaminants (figure 4.2). It should be noted that the surface contamination often has a radial position dependence (figure

48

13

1 ppm 0.1 ppm

2

AAS

12

Ti

V

Cr Mn Fe Co Ni Cu Zn Ru Pt Pb element

not available

not available

not available

1010

not available

11

10

not available

not available

10

not available

concentration atoms/cm )

10

Mg Ca Sr Ba

Figure 4.1: Contamination levels after spinning. The value for Mg was obtained with AAS. For the 0.1 ppm levels of Ti, Ca and Ba the concentrations were obtained with VPD-DC-TXRF assuming a collection efficiency of 50%. All other conditions were measured with D-TXRF. 4.3). For this reason, all D-TXRF results reported here are valid at a distance of at least 2 cm from the centre of the wafer. Surface contamination after oxidation The metal concentration on contaminated wafers was measured after oxidation. Because the X-rays have a limited penetration depth of roughly 3 nm in the oxide [2], the measurements were performed with and without preceding VPD treatment. We thus take into account that contaminants may be located at the oxide surface or at the oxide/substrate interface. Figure 4.4 shows the results, relative to the measured concentration before oxidation. For most metals except Cu, Zn and Pt the detected fraction increases significantly after application of a VPD treatment. For Ti and V the surface concentration has increased above the original contamination level. In section 4.3 this increase will be discussed in more detail. The group II elements show a strong tendency to remain in or close to the oxide during oxidation. Vapour Phase Decomposition - Droplet Collection The Collection Efficiency of the VPD-DC procedure was evaluated both before and after gate oxidation. Only samples treated with a 1 ppm spinning solution have been considered; lower contamination levels were often close to or below the detection limit of the D-TXRF measurement. CE was calculated from equation 4.2 with CMt from figure 4.4 without VPD treatment. CE was also de49

13

400

Zn Sr Ba

2

atoms/cm )

12

300

10

10

concentration (10

metals on wafer (atoms/cm2)

10

Ti Mn Ni Cu

11

10

1:1 1 ppm 0.1 ppm

10

10

14

10

15

16

100

0 -50 0 50 distance from wafer center (mm)

17

10 10 10 metals in solution (atoms/ml)

Figure 4.2: Metal concentration on the wafer surface as a function of the metal concentration in the spinning solution. All measurements were done with DTXRF.

Figure 4.3: Contamination levels after application of a 1 ppm contaminated spinning solution. We often observe a position dependence of contamination levels.

1.5

D-TXRF VPD + D-TXRF

1.0

not available

fraction measured after oxidation

200

0.5

0.0 Ti

V

Cr Mn Fe Co Ni Cu Zn Ru Pt Pb contaminant

Mg Ca Sr Ba

Figure 4.4: Surface concentration of metallic contaminants after oxidation, relative to the concentration before oxidation. The measurements were performed with and without preceding VPD treatment (group II metals and Pb only without VPD treatment). All wafers were treated with a 1 ppm contaminated spinning solution.

50

~250%

~160%

Collection Efficiency

100%

CE before oxidation CE after oxidation, from droplet

Ti

V

not available

0%

not available

50%

Cr Mn Fe Co Ni Cu Zn Pt contaminant

Pb

Mg Ca Sr Ba

Figure 4.5: Collection efficiencies of a 50 µ l droplet (HF/H2 O2 /H2 O = 1/3/100) for different metals, before and after 4.5 nm gate oxidation. Error bars cover both within wafer non-uniformity and wafer-to-wafer variation. All results were obtained on wafers, treated with a 1 ppm contaminated acid solution. The collection efficiencies after oxidation calculated from residual concentrations after DC (dashed lines) are lower limits (not available for Pb and group II metals). termined from the residual concentration next to the dried droplet. Because all concentrations were below the TXRF detection limit, only lower limits for CE were obtained. The results are shown in figure 4.5. In most cases, CE from the residual contamination was equal to or higher than the value obtained from measurements on the droplet. Section 4.3 discusses this in more detail. The difference in CE before and after oxidation is within experimental error for most metals. Exceptions are Co and Ni with CE 100% after oxidation. This value indicates different detection efficiencies before and after the VPD-DC procedure. It is reasonable to assume that oxidation has no large effect on the detection efficiency of metals in the droplet. We conclude that after oxidation Co and Ni are mainly present at the oxide/substrate interface, and are therefore less easily detected by D-TXRF.

Cross contamination Clean reference wafers were placed in the gate oxidation furnace adjacent to contaminated wafers. With TXRF measurements we checked for cross contamination of the contaminants. Only Zn and Pb were found in the range of 5 10 10 to 1 1011 atoms/cm2 , corresponding to 5–10% of the initial concentration on contaminated wafers.

51

4.2.2 SIMS analysis SIMS analysis was carried out for the elements shown in table 4.1. The concentration profiles of elements that were above the detection limit are shown in figures 4.6, 4.7 and 4.8. For all profiles it was checked that the Si signal was stable, to account for the stabilisation time at the start of the measurement. It should be noted that the SIMS profiles do not represent the actual impurity levels; the observation of streaks in sections 4.2.3 and 4.2.4 indicate a localised contaminant distribution. This may be the reason why some contaminants were not detected. The light transition metals V, Cr and Mn (figures 4.6, 4.7) are detected at significant levels close to the substrate surface after the oxidation. After polysilicon deposition, V has redistributed through the poly-silicon. The impurity concentration corresponds to approximately 1012 atoms/cm 8 2 , which is the original contamination level as measured with TXRF. Ti and Cr could not be detected after poly-silicon deposition. Because it was observed that these elements increase the poly-silicon roughness in a similar way as V does, a similar redistribution behaviour during the poly-silicon deposition is anticipated. Mn is also present at the surface after oxidation. The profile after polysilicon deposition is not available due to a processing error. The Co concentration in the poly-silicon is roughly a factor 103 higher than expected. This may partly be explained by the inhomogeneous contaminant distribution after spinning. However, it is most likely due to interference with Si-P pairs. In that case, the detection limit for Co in highly phosphorous doped poly-Si is approximately 1019 atoms/cm3 , which means that it can not be detected at levels relevant in this work. The group II contaminants Ba and Sr are found close to the gate oxide (figure 4.8), both before and after poly-silicon deposition. The Mg concentration is below the detection limit, but on the basis of the electrical results (section 4.2.5) we believe that the profile should be similar to that of Sr and Ba.

4.2.3 Oxide morphology For all contaminated wafers the differences in oxide thickness, as measured with ellipsometry, were below the experimental error of 0.1 nm. Light scattering measurements of the surface haze after oxidation yield low haze values in the range 55–65 ppb, independently of the contaminant. The RMS surface roughness as determined with AFM is shown in figure 4.9. Ba contaminated wafers have slightly higher RMS roughness; the roughness values for other contaminated wafers do not differ significantly from the reference condition. Likely these AFM results do not reflect the actual surface morphology; figure 4.10 shows a Ba-contaminated wafer after etching of the poly-silicon gate area. The underlying substrate exhibits a radial pattern of streaks, which originates from the spin contamination procedure. The pattern was also found on Sr con-

52

20

20

Cr DL

15

10

DL V

10

10

0

poly-silicon

bulk silicon

250 500 depth [nm]

750

3

Ba DL DL

Sr

10

10

0

poly-silicon

bulk silicon

250 500 depth [nm]

DL

15

10

0

poly-silicon

bulk silicon

250 500 depth [nm]

750

Figure 4.7: Depth profiles as measured with SIMS on wafers contaminated with Mn and Co. The Mn contaminated wafer with poly-silicon was lost during processing.

20

15

Mn

10

10

10

DL

10

Figure 4.6: Depth profiles as measured with SIMS on wafers contaminated with V and Cr. The dashed line is the position of the gate oxide. DL indicates the detection limit. Thick curves were measured after oxidation; thin curves were measured on MOS structures with poly-silicon gate.

concentration (atoms/cm )

Co

3


10

3


10

750

Figure 4.8: Depth profiles as measured with SIMS on wafers contaminated with Sr and Ba.

53

Table 4.1: Detection limits (DL) for SIMS measurements.

element detection limit (atoms/cm 8 3 )

Ti V Cr Mn Co Ni

2 5 2 3 2 2

element detection limit (atoms/cm 8 3 )

1015 1013 1014 1015 1018 1017

Zn Pt Pb Mg Sr Ba

8 1 8 4 3 1

1017 1018 1017 1014 1014 1015

taminated wafers. Apparently these contaminants remain near the gate oxide during gate oxidation oxidation.

4.2.4 Poly-silicon morphology Contamination at the wafer surface can have a large impact on the deposition of poly-silicon. For Ti, V and Cr contaminated wafers, a radial pattern was observed on the poly-silicon with an optical microscope (figure 4.11) and with a light scatter tool (figure 4.12). In the case of Cr contamination, the pattern was even visible with the bare eye after sputtering of a 500 µ m aluminum layer. The poly-silicon roughness for Ti, V and Cr will be discussed in more detail in section 4.3. For all other contaminants the haze level was comparable to the reference condition (figure 4.12 left).

4.2.5 Electrical measurements Figure 4.13 shows the GOI defect density obtained from automated ramped voltage stress measurements. The reference condition (IMEC clean) has a low defect density close to the lower detection limit (0.1 defects/cm2 ). Group II contamination results in very high defect densities. Transition metals with low contaminant loss after oxidation (Ti, V, Cr) also cause significant amounts of oxide failures (defect densities of the order of 1–10 defects/cm2 ). The same holds for Ni and (particularly) Co, both located at the oxide/substrate interface. Contaminants with higher contaminant loss result in lower defect densities (Mn, Cu). Mn and Ru related GOI defects are close to the lower detection limit. Breakdown events on Zn and Pt contaminated wafers were dominated by process induced oxide

54

0.5 0.4

0.0 IMEC Ti

V Cr Mn Fe Co Ni Cu Zn Ru Pt Pb contaminant

not available

0.1

not available

0.2

not available

0.3 not available

roughness RMS (nm)

scan area: 1 µm x 1 µm

Mg Ca Sr Ba

Figure 4.9: Surface roughness of contaminated wafers after 4.5 nm gate oxidation at 800 C, as determined by Atomic Force Microscopy. A scan area of 5 µ m 5 µ m yields the same results.

Figure 4.10: Radial patterns on the substrate surface of a Ba contaminated wafer after etching of the poly-Si gate. Similar patterns were observed for Sr contaminated wafers.

Figure 4.11: Radial patterns on the poly-silicon surface of a Ti contaminated wafer after etching of the poly-Si gate. Similar patterns were observed for wafers contaminated with Cr and V.

55

Figure 4.12: Haze plots measured on a C ENSOR ANS -100 of a clean reference wafer (left) and a wafer spin-contaminated with Ti (right) after gate oxidation and poly deposition. Similar patterns were observed for V and Cr. failures and are excluded from the plot. No capacitors were fabricated on Fe contaminated wafers. Figures 4.14 to 4.19 show MOS Igate Vgate characteristics of various capacitors on contaminated wafers. The reference condition is indicated by the arrow (small area capacitors on IMEC cleaned wafers). The curves are ’typical’ examples to illustrate the mode of oxide failure. The curves for Mn and Ru contamination are not shown because very few extrinsic failures were observed. For all conditions, devices are found that are highly conductive even at low voltages. However, for small devices sometimes only an increased tunnel current is observed (which may eventually develop into an early breakdown). This is the case for Ti, V and Cr (figure 4.14). Increased tunnel currents were also found in large capacitors for Ni and Pb contamination (figures 4.16, 4.18). Contaminants that only lead to highly conductive defects are Co, Cu and group II metals (figures 4.15, 4.17, 4.19). Figure 4.20 shows the reverse leakage current measured after breakdown of the capacitors (see chapter 3). The devices are identical to the 1.00 10 8 2 cm2 devices that were shown above; for the contaminants V, Ba, Sr and Pb no leakage measurements were possible because no field implantation was done, resulting in surface inversion below the oxide adjacent to the devices. There were no large differences between the diode characteristics, regardless of the mode of breakdown or the contaminant on the wafer. The contaminated wafers exhibit somewhat higher leakage currents than the reference condition. Only Ru contamination results in a relatively high leakage current.

56

3

10

2

10

10-1 IMEC Ti

V

not available

0

10

not available

1

10

not available

GOI defect density (defects/cm2 )

4

10

Cr Mn Fe Co Ni Cu Zn Ru Pt Pb contaminant

Mg Ca Sr Ba

Figure 4.13: Defect density as calculated from the fraction of early device failures. All wafers were contaminated to a level of approximately 1012 atoms/cm2 by application of a 1 ppm contaminated acid solution.

Ti

100 -3

-3

10 current (A)

10 current (A)

Co

100

10-6 d -9

10

c

10-6

c b

10-9

c 10-12

10-12

b a

10-15

0

reference 10-15

-1 -2 -3 -4 -5 -6 -7 -8 gate voltage (V)

Figure 4.14: Igate Vgate curves of capacitors on Ti contaminated wafers. Areas: a. 1.26 10 8 5 cm2 b. 3.14 10 8 4 cm2 c. 1.00 10 8 2 cm2 d. 0.25 cm2 . Similar curves were obtained with V and Cr contamination.

a

reference

0

-1 -2 -3 -4 -5 -6 -7 -8 gate voltage (V)

Figure 4.15: Igate Vgate curves of capacitors on Co contaminated wafers. Areas: a. 1.26 10 8 5 cm2 b. 3.14 10 8 4 cm2 c. 1.00 10 8 2 cm2 .

57

Ni

100

d

-3

10 current (A)

current (A)

d

-3

10

-6

10

10-9 c

-12

10

10-15

Cu

100

0

-6

10

10-9 c

b

a

a

10

reference

reference 10-15

-1 -2 -3 -4 -5 -6 -7 -8 gate voltage (V)

Figure 4.16: Igate Vgate curves of capacitors on Ni contaminated wafers. Areas: a. 1.26 10 8 5 cm2 b. 3.14 10 8 4 cm2 c. 1.00 10 8 2 cm2 d. 0.25 cm2 .

0

-1 -2 -3 -4 -5 -6 -7 -8 gate voltage (V)

Figure 4.17: Igate Vgate curves of capacitors on Cu contaminated wafers. Areas: a. 1.26 10 8 5 cm2 b. 3.14 10 8 4 cm2 c. 1.00 10 8 2 cm2 d. 0.25 cm2 .

Pb

100

b

-12

Ba

100 d

-3

-3

10 current (A)

current (A)

10

10-6 10-9 10-12

c

-15

10

0

b

10-6 10-9

b a

10-12 a

reference

10-15

-1 -2 -3 -4 -5 -6 -7 -8 gate voltage (V)

Figure 4.18: Igate Vgate curves of capacitors on Pb contaminated wafers. Areas: a. 1.26 10 8 5 cm2 b. 3.14 10 8 4 cm2 c. 1.00 10 8 2 cm2 d. 0.16 cm2 .

b, c

reference 0

-1 -2 -3 -4 -5 -6 -7 -8 gate voltage (V)

Figure 4.19: Igate Vgate curves of capacitors on Ba contaminated wafers. Areas: a. 1.26 10 8 5 cm2 b. 3.14 10 8 4 cm2 c. 1.00 10 8 2 cm2 . Similar curves were obtained with Mg and Ca contamination.

58

Figure 4.20: Diode leakage as measured on capacitors after hard breakdown. The error bars indicate the minimum and maximum values in a total of six devices.

102 V

= +2 V

leakage current (pA)

gate

area: 1 mm

2

1

10

100 IMEC Ti Mn Ni Co Cu Ru Mg Ca

contaminant

4.3 Discussion In this study substrates were contaminated by applying a contaminated liquid, followed by a spin-dry. Metal contamination from solutions has long been explained by differences in electronegativity of contaminants and silicon [3]. More recently alternative adsorption/desorption models were proposed, that consider the treatment time [4], pH dependence [5] and interaction with the wafer surface [6]. These models assume homogeneous metal deposition over the wafer surface. In our experiments however we have seen a radial position dependence of the concentration in D-TXRF measurements (figure 4.3) and a metal-independent linear relation between the concentrations in the liquid and on the surface (figure 4.2). We also observed radial haze patterns after poly-silicon deposition (figure 4.12). We therefore propose that the contamination level in our experiments mainly depends on the liquid layer that evaporates during spinning [7]. The TXRF results after oxidation depend on the application of a VPD treatment. Without VPD treatment, a decrease of the impurity concentration is observed for most transition metals. This decrease may be explained by in-diffusion of contaminants into the substrate (discussed below) or by the presence of contaminants at the substrate/oxide interface, which is not probed by the X-rays [2]. A VPD treatment removes the oxide layer; as expected, the measured metal concentration increases (figure 4.4). However, in some cases (Ti, V) the measured concentration after VPD is higher than originally present on the wafer after spinning. This is most likely a measurement problem, which therefore also affects the other measurement results. It is known that the TXRF response depends on the morphology of the contamination [2]. Contamination may be either ’film-type’ (a thin, homogeneous layer on the substrate) or ’particle-type’. Below the critical angle (αcrit 1 ~ 7 mrad for silicon), film-type contaminants exhibit an increasing fluorescence intensity with increasing angle of incidence. In contrast, particles give 59

Figure 4.21: Theoretical dependence of the TXRF response on the angle of incidence for a silicon substrate. Shown are the responses for three different diameters of particles. The 1 nm and 100 nm particle responses approximate the limits for ideal film-type and particle-type responses, respectively. The figure was taken from Ref. [2].

Fluorescence intensity (a.u.)

4 10 nm 100 nm ’particletype’

3

1 nm ’film-type’

2

1 α

0 0

iso

α

crit

1 2 angle of incidence (mrad)

3

an angle-independent response. Both responses are equal at the iso-kinetic angle αiso αcrit 2. While this applies to particles larger than approx. 100 nm diameter, smaller particles show a transition to film-type response (figure 4.21). In these cases the response peak is rather broad, leading to a net increase of the response at the iso-kinetic angle. Metal compounds formed at the surface during oxidation may have a similar TXRF response as ’particle-like’ contamination. This would explain why the detected fraction of Ti and V is larger than 100%. As a check, the Ti and V response was measured after VPD of substrates that were not oxidised. No increase of the response was found, indicating that oxidation indeed affects the response of these contaminants. This interpretation has not yet been confirmed by angledependent D-TXRF measurements. In this study, the concentrations measured before and after VPD are therefore considered as lower and upper limits of the metal concentrations after oxidation. Another possible explanation for the measured decrease of metal concentrations after oxidation is in-diffusion of impurities into the substrate. It is possible to estimate a theoretical upper limit Nlim for the number of atoms that diffuse into the substrate. If during oxidation the contaminant concentration at the surface is fixed at the solubility limit, Nlim is given by Nlim

2Cs Dt π

(4.3)

with t the oxidation time (approximately 30 min.), and D and Cs the diffusivity and solubility at the oxidation temperature (800 C). If Nlim is larger than the initial surface concentration (roughly 1012 atoms/cm2 ), a significant fraction of the contamination can be dissolved into the substrate. Otherwise, the contamination will remain at the surface. It should be noted that the actual value for Nlim is affected by gettering, either at the surface (resulting in a reduction of Nlim ) or in the bulk (increased Nlim ). However, gettering in the bulk is not likely because the wafers were not annealed to create internal gettering sites. 60

fraction measured after oxidation

Figure 4.22: Measured fraction after oxidation at 800 C, versus the theoretical maximum number of atoms that can be dissolved during a heat treatment of 30 min. at 800 C. The dashed line gives the approximate initial surface concentration for wafers contaminated with a 1 ppm solution. For V we assumed that the solubility and diffusivity are between those of Ti and Cr [8]. The error bars delineate the concentrations as measured with and without preceding VPD treatment.

1.5 Ti V

1.0

Cr Mn Ni

0.5 Co

Fe

Zn Cu Pt

0.0

9

12

10

N

lim

15

10 10 (atoms/cm2 )

Figure 4.22 shows the measured contaminant fraction after oxidation as a function of Nlim . As argued above, the error bars indicate the maximum and minimum concentrations from TXRF measurements with and without preceding VPD treatment, respectively. The figure shows that the surface concentration of Cu, Zn and Pt decreases significantly during oxidation due to in-diffusion (Cu, Pt) or evaporation (Zn, see section 4.2.1). Droplet Collection (DC) can be used to avoid the uncontrolled effects of the location of the contamination and its morphology. For this, the collection efficiency (CE) must be known. When calculated from the residual concentration, CE is systematically larger than expected from measurements on the droplet (figure 4.5). Apparently the fraction that is collected by the droplet is larger than what is actually measured in the droplet. It follows that TXRF has a reduced sensitivity for contaminants in the dried droplet. Recent studies at IMEC show that this is caused by saturation of the VPD-DC-TXRF technique [9]. This may be due to e.g. scattering of X-rays at the dried droplet, or due to absorption of the fluorescence field. Saturation depends on the contaminant, but generally occurs if the concentration in the drying spot exceeds 1013 1015 atoms/cm2 . This means that there is an upper limit for quantitative VPD-DC-TXRF measurements unless a calibration curve is available from independent measurements (e.g. AAS, ICP-MS). In the following we discuss the experimental results for each contaminant separately. In the interpretation we will make use of data that is collected in appendix A. Titanium Titanium is commonly used for interconnects (in the form of silicide) and for interconnect barriers (TiN). It has a low diffusivity and solubility in silicon, which

61

$

Figure 4.23: Ternary phase diagram of the Ti-O-Si system in the temperature range 700–1000 C [15]

%& '

*+

!#"

,.- /-

()

explains its low loss after oxidation (appendix A, figure 4.22). From the increased TXRF response after a VPD treatment it was concluded that Ti probably forms a compound at the surface (figure 4.4). Ti is known to form silicides [8]; however this is not likely to occur in an oxidising ambient [10]. Even if silicide were formed, it would oxidise [11, 12], thus inhibiting interaction with the poly-silicon. This clearly contrasts with the observations in figure 4.12. From appendix A we conclude that Ti likely forms metal oxides during gate oxidation. These form weak spots in the gate oxide, leading to an increase of the tunnel current and of the number of early failures (figures 4.20, 4.13). The oxides may also act as nucleation centres for poly-silicon deposition, thus increasing the poly-silicon surface roughness (figure 4.12). The concentration of Ti in the polysilicon was below the SIMS detection limit; however, the similarities between Ti, V and Cr in the other experimental results suggest that all these elements are partly gettered in the poly-silicon (figure 4.6). A similar gettering mechanism has also been described for Fe contamination [13]. To visualise this gettering mechanism, consider the phase diagram of the TiSi-O system in figure 4.23. During gate oxidation the formation of Ti oxides is in equilibrium with SiO2 growth. During the subsequent poly-silicon deposition this equilibrium is disturbed. The Ti oxide will be partly converted to silicide, which then acts as a source for Ti diffusion into the polysilicon. This process strongly resembles solid phase epitaxy [14]. Vanadium Vanadium is present as an additive in stainless steel in typical concentrations of 0.1–1.0%. Its diffusion behaviour in silicon is not known well [8], but TXRF and SIMS measurements show that little V is dissolved during oxidation (figures 4.4, 4.6). V, like Ti, most likely forms an oxide during gate oxidation (appendix A). In spite of the high vapour pressure of V2 O5 , no cross contamination is observed. The effect of V and Ti contamination on the poly-silicon deposition and on the 62

gate oxide integrity is very similar (figures 4.12, 4.13). We conclude that the same arguments apply for Ti and V contamination. Chromium Like vanadium, chromium is used as an additive in steel (0.5–9%). TXRF and SIMS measurements show that little Cr is dissolved during oxidation (figures 4.4, 4.6); it likely forms an oxide which limits its diffusion into the substrate [8] (appendix A). Like Ti and V, Cr contamination causes a radial haze pattern in the poly-silicon surface (figure 4.12). The effect of Cr contamination on the gate oxide integrity is less pronounced compared to Ti and V (figure 4.13), but the observed increase of the tunnel current is typical for all three metals (figure 4.14). We conclude that the behaviour of Cr as a contaminant is largely analogous to that of Ti and V. Manganese Manganese is an important steel component (up to 10%). It most likely forms a silicate (appendix A). TXRF and SIMS measurements indicate that a significant fraction remains at the surface during oxidation (figures 4.4, 4.7); however, contaminant redistribution during poly-silicon deposition can not be excluded. The impact on the gate oxide integrity and diode leakage current is very small (figures 4.13, 4.20). Iron Iron is the most abundant contaminant in cleanroom environments, and the most extensively studied. Like most transition metals, it oxidises during oxidation or it forms a silicate, depending on the temperature (appendix A, Ref. [16]). The detected fraction after oxidation is comparable to that of metals such as Mn, Cr and Co (figure 4.4). Fe contamination is known to increase the poly-silicon roughness if oxygen is present during the ramp-up to the oxidation temperature [17]. This is similar to our observations with Ti, V and Cr contamination, and may be explained by a similar mechanism of silicide formation during polysilicon deposition. Cobalt Cobalt is widely used as a silicide to form contacts to the gate and source/drain regions. In oxidising ambients it easily forms a metal oxide (appendix A). From figure 4.22 little Co is expected to diffuse into the substrate. As with Ni, it is found predominantly at the oxide/substrate interface (figure 4.5). It is does not noticeably affect the diode leakage current (figure 4.20) but it is very harmful for the gate oxide integrity (figure 4.13). 63

Nickel Nickel is used for high-temperature corrosion resistant steels and is often found as a contaminant. The data in appendix A do not clearly indicate whether an oxide or silicide will be formed during oxidation. From figure 4.5 it was concluded that a significant amount of Ni is located at the substrate/oxide interface after oxidation. This would be consistent with the formation of Ni silicide [11]. It may also explain the relatively small impact on the gate oxide integrity [16] (figure 4.13). Ni has only a small effect on the recombination lifetimes [18, 19], so that diode leakage measurements (figure 4.20) are no reliable indication for Ni in-diffusion. However, even if in-diffusion occurs, Ni is expected to precipitate as a silicide at the surface upon cooling [19]. Copper Copper easily deposits on silicon from wet chemicals, and the use of copper as interconnect metal is a challenge for contamination control in cleanrooms [20]. During oxidation, it first forms a silicide (Cu3 Si) [8, 21] which then serves as a source for Cu diffusion into the substrate. Due to its high diffusivity and solubility, a very low Cu concentration is detected after oxidation (figure 4.4). This agrees with the observation that Cu contamination does not lead to high GOI defect densities (figure 4.13), and not even to an increase of the diode leakage (figure 4.20). Similar results were obtained in a recent study that used comparable conditions [22]. It should be noted that for n-type silicon a larger effect on minority carrier lifetimes is expected [23]. Zinc Zn as a contaminant is relatively rare. While Zn silicate has been reported to reduce breakdown yield for surface concentrations exceeding 10 12 atoms/cm2 [16], such concentrations are unlikely under normal conditions. Due to a processing error, a reduction of breakdown yield can not be confirmed. However, only little Zn was found after oxidation (figure 4.4). Cross contamination of Zn was significant due to its high vapour pressure [8, 24] (appendix A). Roughly 10% of the contamination was transferred to an adjacent reference wafer. We conclude that yield loss is not likely for the conditions applied in our study. Ruthenium The use of ruthenium in device fabrication is not well established, but it is considered a possible electrode material for para-electric [25] or ferro-electric [26] capacitors. The reason is that RuO2 is a conducting oxide: exposure to oxygen does not lower the stack capacitance. Therefore, the effect of Ru on the GOI defect density is expected to be considerable if a metal oxide is formed. The 64

low GOI defect density (figure 4.13), which agrees with a previous study [27], shows that no oxide is formed. Also, Ru is the only contaminant that results in a significant increase of the diode leakage current (figure 4.20). We conclude that Ru dissolves completely in the substrate, but does not diffuse more than several µ m. The solubility and diffusivity of Ru in silicon are not known at present. Platinum Platinum is used as a dopant to control carrier lifetimes in silicon. It is also increasingly used as electrode material for ferro-electric devices because it does not oxidise [26]. Silicides, when formed, act as a source for diffusion into the substrate [8]; Pt has a very high diffusivity and solubility in silicon. This explains the low contaminant fraction that is measured after oxidation (figure 4.4). Although its collection efficiency is comparable to that of other contaminants, its response in a VPD-DC-TXRF measurement is relatively low (figure 4.5). This shows that the saturation of the VPD-DC-TXRF technique is element dependent. Lead Lead is used in ferro-electric materials such as PbZrx Ti1 x O3 (PZT) in non8 volatile memories. Its effect as a contaminant has not previously been investigated, and no data on its diffusivity and solubility in silicon are available. During the gate oxidation a large fraction remains at the surface due to the formation of oxides or silicates (figure 4.4). Pb is, with Zn, the only element causing prominent cross contamination, likely in the form of volatile oxides (appendix A). Pb contamination results in a slightly increased GOI defect density of the order of 1 defect/cm2 (figure 4.13). Group II metals: Magnesium, Calcium, Strontium, Barium Calcium and magnesium can be present in quartz and DI water, and are a major concern for yield loss [28]. Strontium and Barium are used in ferro-electric materials for non-volatile memories or for high-k gate dielectrics (e.g. BaSrTiO 3 , BST). These contaminants all have very similar behaviour. Their vapour pressures are very high, as well as the solubilities of Mg and Ca in silicon. However, the metals are also very reactive [29]: Mg and Ca form silicates [16], which is also expected for Sr and Ba (appendix A). After gate oxidation, the surface roughness on Ba contaminated wafers has increased (figure 4.9). TXRF and SIMS measurements reveal the presence of Sr and Ba contaminants near the gate oxide after gate oxidation and poly-silicon deposition (figures 4.4, 4.8). Although the poly-silicon roughness was not increased, radial patterns were seen on Sr and Ba contaminated wafers after gate etching (figure 4.10). This may be explained by a locally altered etch rate in the presence of contaminants. 65

The gate oxide defect density is high, and increases with atomic weight (figure 4.13). This trend correlates with the increasing heats of silicate formation, suggesting that silicates are indeed formed. All observations are consistent with the presence of group II contaminants close to the gate oxide. As a result, the minority carrier lifetimes are not degraded (figure 4.20), which has independently been confirmed for the case of Sr [30].

4.4 Conclusions The effect of various metallic contaminants on the gate oxide integrity has been investigated. The contaminants of interest were Mg, Ca, Sr, Ba, Pb, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ru and Pt. Using identical processing conditions and analysis methods, the behaviour during gate oxidation and poly-silicon deposition was traced. For the conditions used in this study, in-diffusion was only significant for metals with very high diffusivity and solubility (Cu, Pt). Only Pb and Zn evaporate and lead to cross contamination. The transition metals Ti, V and Cr behave very similarly. They remain close to the substrate surface during oxidation, and therefore do not significantly degrade carrier lifetimes in the substrate. However, when incorporated in the gate oxide they increase the tunnel current, and the number of gate oxide failures is relatively high. All three elements cause roughening of the poly-silicon gate, which may be due to metal gettering in the poly-silicon. The group II elements (Mg, Ca, Sr, Ba) all behave similarly under the conditions used in this work. They remain at the substrate surface during gate oxidation and form silicates. No evidence was found for lifetime degradation, but group II elements cause the highest number of gate oxide failures compared to other contaminants. The location of the contaminant in the thermal oxide can significantly affect the detection efficiency of D-TXRF. Removal of the oxide layer by application of a VPD treatment reveals a dependence of D-TXRF on the morphology of the contamination as well. This complicates a quantitative interpretation of DTXRF measurements. Use of a droplet collection (DC) method, followed by droplet drying, is shown to result in a reduced sensitivity of TXRF for the contamination in the droplet. For this reason, it is required to carry out a calibration of the VPD-DC-TXRF procedure for each contaminant of interest, using an independent technique such as AAS.

66

References [1] M. M. Heyns, S. Verhaverbeke, M. Meuris, P. W. Mertens, H. Schmidt, M. Kubota, A. Philipossian, K. Dillenbeck, D. Gräf, A. Schnegg, and R. de Blank. New wet cleaning strategies for obtaining highly reliable thin oxides. In MRS Symposium Proceedings, volume 315, pages 35–45, Pittsburgh, PA, USA, 1993. Mat. Res. Soc. [2] R. Klockenkämper. Total-Reflection X-Ray Fluorescence Analysis. John Wiley & Sons, Inc., New York, USA, 1997. [3] K. Graff. Transition metals in silicon and their gettering behaviour. Mat. Sc. Eng., B4:63–69, 1989. [4] J. Ryuta, T. Yoshimi, H. Kondo, H. Okuda, and Y. Shimanuki. Adsorption and desorption of metallic impurities on si wafer surface in sc1 solution. Jpn. J. Appl. Phys., 31:2338–2342, 1992. [5] Y. Mori, K. Uemura, and K. Shimanoe. Adsorption species of transition metal ions on silicon wafer in SC-1 solution. J. Electrochem. Soc., 142: 3104–3109, 1995. [6] L. M. Loewenstein, F. Charpin, and P. W. Mertens. Competitive adsorption of metal ions onto hydrophilic silicon surfaces from aqueous solution. J. Electrochem. Soc., 146:719–727, 1999. [7] W. Fyen, F. Holsteyns, P. W. Mertens, J. Lauerhaas, and M. M. Heyns. Estimation of evaporating water film during different drying processes. In Electrochem. Soc. Proc., Pennington, NJ, USA, 2001. The Electrochemical Society. submitted. [8] K. Graff. Metal impurities in silicon-device fabrication. Springer Verlag, Berlin/Heidelberg, 1995. [9] A. Maes. Metaalcontaminatie monitoring met behulp van totale x-stralen fluorescentie spectroscopie voor geavanceerde silicium processing. Master’s thesis, Groep T, Leuven, Belgium, 2001. [10] K. Maex, E. Kondoh, A. Lauwers, A. Steegen, M. de Potter, P. Besser, and J. Proost. Control and impact of processing ambient during rapid thermal silicidation. In Rapid Thermal and Integrated Processing VII, volume 403, pages 297–306, Warrendale, PA, USA, 1998. Symposium. Mater. Res. Soc. [11] O. Thomas, L. Stolt, P. Buaud, J. C. Poler, and F. M. d’Heurle. Oxidation and formation mechnisms in disilicides: VSi2 and CrSi2 , inert marker experiments and interpretation. J. Appl. Phys., 68:6213–6223, 1990. 67

[12] Q. T. Zhao, F. Klinkhammer, M. Dolle, L. Kappius, and S. Mantl. Nanometer patterning of epitaxial CoSi2 /Si (100) for ultrashort channel schottky barrier metal-oixide-semiconductor field effect transistor. Appl. Phys. Lett., 74:454–456, 1999. [13] R. Sugino, Y. Tada, T. Ito, Y. Okui, and J. Sakuma. Removal of fe contaminants in SiO2 layers with successive processing of poly-si deposition and cl-radical etching. J. Electrochem. Soc., 144:4059–4061, 1997. [14] M.-A. Nicolet and S. S. Lau. Formation and Characterization of Transition-Metal Silicides, volume 6 of VLSI electronics: microstructure science, chapter 6, pages 329–459. Academic Press, New York, 1983. [15] K. Maex and M. van Rossum, editors. Properties of Metal Silicides. INSPEC, London, 1995. [16] M. Takiyama, S. Ohtsuka, S. Hayashi, and M. Tachimori. Dielectric degradation of silicon dioxide films caused by metal contaminations. In Proc. 7th Int. Symp. Silicon Materials Science and Tehcnology, volume 94-10 of Electrochemical Society Proceedings, pages 346–355, Pennington, NJ, USA, 1994. The Electrochemical Society. [17] P. W. Mertens, S. de Gendt, M. Depas, K. Kenis, A. Opdebeeck, P. Snee, D. Gräf, G. Brown, and M. M. Heyns. Effect of fe contamination on 5 nm oxide-poly silicon gate structures. In 3rd Int. Symp. Ultra Clean Processing of Silicon Surfaces, pages 33–36, Leuven, 1996. Acco. UCPSS, September 23–25, 1996, Antwerpen, Belgium. [18] M. Hourai, T. Naridomi, Y. Oka, K. Murakami, S. Sumita, N. Fujino, and T. Shiraiwa. A method of quantitative contamination with metallic impurities of the surface of a silicon wafer. Jpn. J. Appl. Phys., 27:L2361–L2363, 1988. [19] A. A. Istratov and E. R. Weber. Electical properties and recombination activity of copper, nickel and cobalt in silicon. Appl. Phys. A, 66:123–136, 1998. [20] M. Takenaka, T. Tachibe, S. Kozuka, M. Hayashi, and H. Matsunaga. Evaluation of ultratrace metallic impurities in thin copper layers, barrier metals and silicon wafers for copper metallization technology. Jpn. J. Appl. Phys., 35:L1628–L1630, 1996. [21] S. M. Myers, D. M. Follstaedt, and D. M. Bishop. Binding of copper and nickel to cavities in silicon formed by helium ion implantation. In Materials Synthesis and Processing Using Ion Beams Symposium, pages 33–38, Pittsburgh, PA, USA, 1994. Mater. Res. Soc. 68

[22] M. Inohara, H. Sakurai, T. Yamaguchi, H. Tomita, T. Ijima, H. Oyamatsu, T. Nakayama andH. Yoshimura, and Y. Toyoshima. Copper contamination induced degradation of MOSFET characteristics and reliability. In Proc. Int. Symp. VLSI, pages 26–27, Piscataway, NJ, USA, 2000. IEEE. [23] M. Itsumi, Y. Sato, and K. Imai. Characterization of metallic impurities in si using a recombination-lifetime correlation method. J. Appl. Phys., 82: 3250–3255, 1997. [24] A. Giese, H. Bracht, and N. A. Stolwijk. Out-diffusion of zn from si: a method to study vacancy properties in si. J. Appl. Phys., 83:8062–8064, 1998. [25] E.-S. Choi, J.-S. Hwang, and S.-G. Yoon. Contact properties of Pt/RuO 2 /Ru electrode structure integrated on polycrystalline silicon. J. Electrochem. Soc., 147:2340–2342, 2000. [26] J. Bandaru, T. Sands, and L. Tsakalakos. Simple ru electrode scheme for ferroelectric (pb, la) (zr, ti) o3 capacitors directly on silicon. J. Appl. Phys., 84:1121–1125, 1998. [27] Y. Kawai, E. Uchida, M. Itoh, M. Yoshimaru, and J. Ida. The effect of capacitor electrode contaminant on high density DRAM’s device characteristics. In Int. Conf. Solid State Dev. Mat., pages 34–35, Hamamatsu, 1997. [28] L. M. Loewenstein and P. W. Mertens. Competitive adsorption of cations onto the silicon surface: the role of the ammonium ion in ammoniaperoxide solution. In Cleaning Technology in Semiconductor Device Manufacturing. Proceedings of the Sixth International Symposium., volume 9936 of Electrochemical Society Proceedings, pages 512–519, Pennington, NJ, USA, 1999. The Electrochemical Society. [29] H. Sigmund. Solubilities of magnesium and calcium in silicon. J. Electrochem. Soc., 129:2809–2812, 1982. [30] S. Yamamichi, Y. Muramatsu, P. Lesaicherre, and H. Ono. Influence of strontium impurities on silicon substrates during thermal processing. Jpn. J. Appl. Phys., 34:5188–5192, 1995.

69

70

Chapter 5 Breakdown caused by substrate defects The results in this chapter have partly been published in: T. Bearda, M. Houssa, P. W. Mertens, J. Vanhellemont, M. Heyns: Observation of critical gate oxide thickness for substrate-defect related oxide failure. Applied Physics Letters 75 (1999) 1255–1257. T. R. Bearda, J. Vanhellemont, P. W. Mertens, M. Heyns: Effect of substrate defects on GOI of ultra-thin gate oxides. Proceedings of the Fifth International Symposium on High Purity Silicon V. Electrochemical Society, Pennington, NJ, USA (1998) 258–263.

Silicon substrates for microelectronic devices have to meet strict specifications with regard to geometry, impurity levels and crystalline defects. In chapter 4 we have already considered the impact of metallic impurities on the Gate Oxide Integrity (GOI). Crystalline defects are also known to be harmful: GOI levels may vary strongly between different types of wafers [1, 2]. The crystalline defects that are responsible for this variation have only recently been identified to be vacancy agglomerates (voids) [3]. The relation between voids and GOI will be the topic of the present chapter. Section 5.1 gives a short introduction to the origin of voids. In section 5.2 we discuss the relation between the position of the void in the substrate and its impact on GOI. The harmfulness of individual defects will be addressed in section 5.3. The dependence of defect induced oxide failures is discussed in section 5.4; the results support the argument of section 5.2, and indicate a number of possible failure mechanisms.

71

5.1 Origin of void-related defects A common method to fabricate single crystal silicon is the so-called ’Czochralski’ (CZ) method. A crucible containing high-purity silicon is heated to slightly above the silicon melting temperature (1412 C). A seed crystal is dipped into the melt and pulled upwards at a speed of the order of 10 mm/hr. Molten silicon adheres to the end of the seed and forms a crystal (ingot) as it cools and solidifies. Depending on the pull rate and the temperature gradient, point defects (i.e. lattice vacancies and lattice interstitials) are incorporated in the crystal during pulling. Commercial silicon wafers, which are pulled at relatively high rates, are ’vacancy-rich’. Although many other factors determine the pull rate [4], high pull rates are favoured for economic reasons. Furthermore lower pull rates result in interstitial-related defects that are more difficult to control. As the crystal cools to temperatures of 1000–1100 C, the vacancies supersaturate. They partly recombine with interstitials, and partly form vacancy clusters (voids) [5]. With slower cooling rates, the size of the voids becomes larger and their density decreases. The voids have octahedral shapes of typically 100– 250 nm in diameter [6]. The density is about 106 cm 8 3 , corresponding to a volume defect density of 0.01 ppm. Both isolated and clustered voids have been reported [7, 8]. After cooling, the ingot is sliced to form wafers, so that the voids can appear as pits at the wafer surface [3] (see figure 5.1). Because the voids were first observed in this form, using a light scattering system for particle detection [9], they were named Crystal Originated Particles (COP). The appearance of COP can be changed by treatments such as annealing, polishing or etching [10]. A clear correlation exists between the number of COP and the gate oxide failures of Metal-Oxide-Semiconductor (MOS) structures [2, 11]. The failure mechanism has been related to gettering of impurities [12], mechanical stress [13], oxide thinning [14, 15] and field enhancement [13, 14] at the tip of the COP.

5.2 Voids versus COP Although voids and COP are essentially the same type of defects, it is useful to make a distinction. In our definition, voids are buried below the substrate surface, whereas COP appear as pits at the surface. The correlation of gate oxide failures with COP implies also a correlation with voids. We assume that both defect types lead to structural imperfections in the oxide ("oxide defects"). Obviously, the number of void-related oxide defects increases with the amount of silicon that is consumed during oxidation (typically 40% of the oxide thickness). In contrast, the number of COP-related oxide defects remains constant. The COP density can be related to the as-grown void density by considering how many voids are intersected by the wafer surface. This number is given by the number

72

edge tip

150 nm voids

COP

Figure 5.1: Distinction between sub-surface defects (voids) and defects that appear at the surface (COP). of voids that is present in a layer with the same thickness as the void diameter. The total oxide defect density is then, in mathematical form: oxide defects

COP in oxide void density void size void density void size

voids in oxide void density 40% tox

(5.1) The expected variation of the defect density with tox is shown in figure 5.2. In the range of interest (where tox void size) the number of COP dominates the number of voids that is incorporated in the oxide. Typical values for the void size and void density are 150 nm and 106 cm 8 3 , respectively. Using these values, the expected oxide defect density is 15 cm 8 2 . This is close to experimental values for GOI defect densities on as-grown CZ wafers (see section 5.4). Assuming that each "oxide defect" causes GOI degradation, we anticipate that most substratedefect related oxide failures are due to COP rather than voids.

5.3 Correlation between COP and oxide failure Although we expect COP to dominate over voids with regard to extrinsic gate oxide failures, this does not necessarily mean that every COP is harmful. To clarify this relation further, the positions of light scattering defects (LPD or Light Point Defects) were determined on CZ wafers, followed by MOS capacitors fabrication. The positions of failing capacitors correlate well with the positions of the 73

region of interest: tox< 20 nm 30 -2

oxide defect density (cm )

Figure 5.2: Contribution of voids and COP to the number of oxide defects for a void density of 106 cm 8 3 and void size of 150 nm.

sum of defects

due to COP

15

due to voids

0 0

100 200 oxide thickness (nm)

light scatterers. Assuming that the light scatterers are Crystal Originated Particles, this implies a good correlation between oxide failure and the presence of COP.

5.3.1 Experimental The substrate used in this experiment was a 150 mm standard mirror polished 100 p-Si wafer. COP were detected as LPD in a 1 cm 1 cm window using a lightscattering tool (CENSOR ANS -100). The defect detection criterion was a Latex Sphere Equivalent diameter 0 ~ 12 µ m. The positions of the LPD were determined to an accuracy of approximately 100 µ m. After inspection the wafer received an IMEC clean [16]. A 7 nm gate oxide was grown at 850 C followed by deposition and phosphorous doping of a poly-Si gate. MOS capacitors of 190 µ m 190 µ m, covering 90% of the sample surface, were fabricated and measured by applying a ramped voltage stress in gate injection mode. Typical criteria for oxide failure were a reduced breakdown voltage VBD 10 V, or an increased leakage current Ileak 1 nA at a gate voltage of 6 V.

5.3.2 Results The positions of LPD and failing capacitors are shown in figure 5.3. Figure 5.4 shows the current-voltage (I V ) characteristics of those failing capacitors that are located within 200 µ m of an LPD. Of the 2500 capacitors, five (0.2%) fail without a corresponding LPD being detected. The I V curves of these devices are shown in figure 5.5. Similarly, some LPD were detected that are not correlated to capacitor failure. All failing capacitors show similar failure modes, irrespective of the presence 74

LPD failing capacitor

Figure 5.3: Positions of LPD as detected with a CENSOR ANS -100 (LSE diameter 0 ~ 12 µ m) and the positions of failing capacitors. All coordinates have a precision of approximately 100 µ m. The arrows indicate matching pairs of LPD and failing capacitors.

y (mm)

30

25

20

-20

-15

-10

-5

x (mm)

of an LPD: either a reduction of VBD , or an increase of Ileak . Considering the large number of devices, the correlation between failing capacitors and LPD is reasonably good. The additional failures may be explained by defects (not necessarily COP) that are below the optical detection limit [14, 17]. The nondetrimental LPD may likewise be harmless defects (due to composition, shape or size), or defects that were cleaned off prior to gate oxidation. If the LPD in figure 5.3 are interpreted as COP, then a significant part of the observable COP is harmful for the gate oxide.

5.4 Oxide thickness dependence In section 5.2 the number of substrate-defect related oxide failures was predicted to be independent of the oxide thickness. This seems to contrast with experimental observations: it has been reported that ultra-thin oxides are relatively insensitive to the presence of substrate defects [18, 19, 20]. The present section discusses defect induced oxide failures for a range of oxide thicknesses, taking into account the "impact" of a defect on the gate oxide.

5.4.1 Experimental Different types of 150 mm 100 p-type CZ substrates were used, labelled A, B, C and D in order of decreasing cooling rate1 . As reference, we included p p 9 epi substrates. For the gate oxidations the conditions as shown in table 5.1 apply. Capacitor areas ranged from 2 10 8 5 cm2 to 0.25 cm2 . For electrical evaluation a gate voltage ramp was applied with negative polarity. Breakdown was detected as a sudden increase of the slope in the current-voltage characteristics.

1 The

wafers were supplied by Wacker Siltronic AG

75

0

0

10

10

EBD failures near LPD

EBD failures without LPD -3

10 current (A)

current (A)

10-3 t : 7 nm ox

-6

10

area: 190µm x 190µm

-9

-9

10

10

10-12 -0

-12

10

-0

-6

10

-2

-4 -6 -8 -10 -12 gate voltage (V)

Figure 5.4: Current-voltage characteristics of failing capacitors that are located near LPD (failure criterion: see text). The intrinsic curve is shown with a thick line.

-2

-4 -6 -8 -10 -12 gate voltage (V)

Figure 5.5: Current-voltage characteristics of capacitors that failed without detection of a corresponding LPD. The intrinsic curve is shown with a thick line.

For the calculation of the electric field over the oxide, we used the ellipsometric oxide thicknesses, and the flatband voltage as obtained from High-Frequency Capacitance-Voltage characteristics.

5.4.2 Results Figure 5.6 shows the breakdown field distributions for 15 nm gate oxides grown on a CZ substrate. Devices larger than 1 mm2 have significantly lower breakdown fields than devices on epi substrates (figure 5.7). The distribution of 5 mm2 devices shows a clear shoulder, with the extrinsic failures positioned at around 7 MV/cm. We define the impact of a defect as the reduction of the breakdown field due to that defect. The spread of the extrinsic breakdown field is assumed to be caused by variations between defects. A spread in defect impact also explains the lower average breakdown field of large devices. This is further illustrated in figure 5.8, which shows breakdown fields of devices on different types of CZ substrates. The varying heights of the shoulders indicate the different defect densities. As the defect density decreases, both the spread and the average breakdown field increase. The defect impact decreases with decreasing gate oxide thickness (figure 5.9). At the same time, the height of the shoulder remains fixed at approximately 50%; apparently the number of extrinsic oxide failures is independent of the oxide thickness. This confirms the prediction of section 5.2. The calculated defect density is 14 ~ 5 2 ~ 5 cm 8 2 , which is also very close to the predicted value 76

Table 5.1: Oxidation conditions. Oxide thicknesses are measured with ellipsometry. Substrates with an epitaxial layer were always included as a reference condition. Temperature

Ambient

Oxide Oxidation wafer type thickness time

750 C

pure O2

2.5 nm 2.8 nm 3.2 nm 3.4 nm

10 min. 20 min. 30 min. 40 min.

B-CZ B-CZ B-CZ B-CZ

850 C

10% O2 /N2

3.0 nm 3.6 nm 3.7 nm 4.0 nm 4.3 nm 4.6 nm 5.1 nm 5.5 nm 6.6 nm 7.6 nm

10 min. 20 min. 30 min. 40 min. 50 min. 60 min. 80 min. 100 min. 150 min. 200 min.

B-CZ B-CZ B-CZ B-CZ B-CZ B-CZ B-CZ B-CZ B-CZ B-CZ

850 C

pure O2

6.1 nm 7.4 nm 8.8 nm 9.9 nm 12.3 nm 14.8 nm 17.1 nm 19.2 nm 22.7 nm 26.5 nm

20 min. 30 min. 40 min. 50 min. 75 min. 100 min. 125 min. 150 min. 200 min. 250 min.

B-CZ B-CZ B-CZ B-CZ B-CZ B-CZ B-CZ B-CZ B-CZ B-CZ

900 C

pure O2

24.9 nm

unknown

A-CZ B-CZ C-CZ D-CZ

77

2

CZ

1

99% 90%

t = ox

Weibull

14.8 nm

30% 2

5 mm

-2

2

5 mm

70% 50%

2

1 mm

30%

-1 -2

10%

-3

25 mm

ox

0

2

25 mm

-1

99% 90%

2

t = 14.8 nm

70% 50%

0

epi

1 Weibull

2

10%

-3

2

1 mm

-4

-4 0

5 10 15 breakdown field (MV/cm)

0

Figure 5.6: Breakdown field distribution of 14.8 nm gate oxide grown on a B-CZ substrate. Capacitor areas as indicated. Absent plot symbols mark the condition of 40 mA leakage current (compliance limit) without detection of breakdown.

5 10 15 breakdown field (MV/cm)

Figure 5.7: Breakdown field distribution of 14.8 nm gate oxide grown on an epi substrate.

-2

defect densities:

A-CZ: > 34 cm -2

B-CZ: 13 cm

-2

C-CZ: 8 cm

-2

D-CZ: 5 cm

Figure 5.8: Breakdown field distributions of 25 nm gate oxide grown on four different types of CZ substrates.

epi:

-2

< 0.1 cm

2 area = 2

0.16 cm t = 25 nm

1

99% 90%

Weibull

ox

0

70% 50%

-1

30%

-2

10%

-3 -4 0

78

5 10 breakdown field (MV/cm)

15

current compliance intrinsic breakdown extrinsic breakdown 2.5 nm 4.5 nm 7.4 nm 9.9 nm 14.8 nm 19.2 nm

Weibull

1 0

-30 area = 2

5 mm

B-CZ substrate

99% 90%

mean gate voltage (V)

2

70% 50% 30%

-1 -2

10%

-3 -4 0


-25

2

area: 5 mm

-20 -15 -10 -5 0 0

15

Figure 5.9: Breakdown field distributions of 5 mm2 capacitors on BCZ substrates with varying gate oxide thicknesses.

5 10 15 20 25 oxide thickness (nm)

30

Figure 5.10: Mean intrinsic and extrinsic breakdown voltages. If no breakdown could be detected, the voltage required to reach current compliance is given.

for ’typical’ as-grown CZ substrates. The defect density remains constant down to an oxide thickness of approximately 5 nm. Below this thickness, two factors complicate the detection of extrinsic breakdown. Firstly, extrinsic breakdown is not easily distinguished if the defect impact becomes comparable to (or smaller than) its spread. Secondly, the tunnel current in these large area devices may reach the current compliance of the measurement setup before breakdown. No distinction between extrinsic and intrinsic breakdown is possible for this case. However, from the trend in figure 5.10 we conclude that in very thin oxides (tox 5 nm) the defect impact vanishes completely. In a ramped voltage stress, the wear-out of the gate oxide is accelerated by stepwise increasing the gate voltage (typically ∆V 0 ~ 1 V). Because the occurrence of breakdown is very sensitive to the stress level, some information may be lost if the voltage step size is too large. We increased the resolution by applying a constant voltage stress. The measurements did not reveal significant differences between intrinsic and extrinsic breakdown for the 5.1 nm gate oxide (figure 5.11). Increasing the sensitivity further by reducing the stress voltage would lead to very long measurement times. From these results we expect that, if substrate defects are a reliability problem, alternative techniques are needed to detect defects in sub-5 nm gate oxides. COP induced oxide failures have been related to a number of possible failure

79

2

2

1

2

area = 5 mm

epi

B-CZ

t = 5.1 nm

Weibull

0

ox

V

gate

= -7 V

1

70% 50%

0

70% 50%

-1

30%

30%

-1 -2

substrate injection gate injection

99% 90% Weibull

CVS

99% 90%

-2

10%

10% B-CZ substrate

-3

-3

-4 0.1

-4 1 10 100 time to breakdown (s)

1000

2

area = 5 mm t = 15 nm ox

0

Figure 5.11: Time to breakdown distribution in Constant Voltage Stress measurements on 5 mm2 devices with 5.1 nm gate oxides.


15

Figure 5.12: Polarity dependence of extrinsic breakdown. The electric field was calculated as Vgate VFB tox . In substrate injection, the devices were illuminated. Absent plot symbols indicate that no breakdown occurred due to limited carrier generation or due to the compliance limit.

mechanisms, such as mechanical stress [13], oxide thinning [14, 15] and field enhancement [13, 14]. When stressed with positive gate polarity instead of negative gate polarity, the defect induced failures occur at higher fields (figure 5.12). This is a clear signature of field distortion, which may be due to the convex tip and concave edges of the COP. At the same time, contributions of other failure mechanisms, can not be excluded. For example, oxide thinning increases the electric field, but is expected to be less severe in thin oxides; this may explain the dependence of defect impact on oxide thickness [21] (see chapter 6).

5.5 Conclusions In this chapter we investigated extrinsic gate oxide breakdown due to vacancy defects in CZ grown substrates. We have shown that the gate oxide defect density is essentially independent of the oxide thickness for thicknesses above approximately 5 nm. This indicates that the oxide failures are mainly due to voids appearing at the surface (Crystal Originated Particles, COP). A reasonably good correlation exists between oxide breakdown and light scattering defects that are present at the surface before gate oxidation. The light scatterers are assumed to be COP. 80

The average breakdown field for COP-related oxide failures increases with decreasing oxide thickness. Oxides thinner than 5 nm do not exhibit significant COP-related degradation in common techniques such as a ramped voltage stress or constant voltage stress. This means that, if COP degrade the reliability of thin oxides, other evaluation techniques are required. This will be addressed in chapter 6. The polarity dependence of the breakdown field indicates that field distortion at COP tips and corners is at least partly responsible for oxide degradation. However, field distortion alone can not explain the observed oxide thickness dependence of the degradation. Other failure mechanisms such as oxide thinning are expected to play a role, but can not be distinguished at this moment. Chapter 6 will discuss this in more detail.

References [1] M. Itsumi and F. Kioysumi. origin and elimination of defects in SiO2 thermally grown on czochralski silicon substrate. Appl. Phys. Lett., 40:496– 498, 1982. [2] H. Yamagishi, I. Fusegawa, N. Fujimaki, and M. Katayama. Recognition of d defects in silicon single crystals by preferential etching and effect on gate oxide integrity. Semicond. Sci. Technol., 7:A135–A140, 1992. [3] M. Itsumi, H. Akiya, T. Ueki, M. Tomita, and M. Yamawaki. The composition of octahedron structures that act as an origin of defects in thermal SiO2 on czochralski silicon. J. Appl. Phys., 78:5984–5988, 1995. [4] W. von Ammon. Expected limits for manufacturing very large silicon wafers. Solid State Phenomena, 47–48:97–106, 1996. [5] E. Dornberger, J. Esfandyari, D. Gräf, J. Vanhellemont, U. Lambert, F. Dupret, and W. von Ammon. Simulation of grown-in voids in czochralski silicon crystals. In Electrochem. Soc. Proc., volume 97-22, pages 40–49, Pennington, NJ, USA, 1997. Electrochemical Society. [6] T. Ueki, M. Itsumi, and T. Takeda. Octahedral void structure observed at the grown-in defects in the bulk of standard cz-si for moslsis. In Int. Conf. Solid State Dev. Mat., pages 862–863, 1996. [7] M. Itsumi, H. Akiya, T. Ueki, M. Tomita, and M. Yamawaki. Octahedralstructured gigantic precipitates as the origin of gate-oxide defects in metaloxide-semiconductor large-scale-integrated circuits. Jpn. J. Appl. Phys., 35:812–817, 1996.

81

[8] H. Bender, J. Vanhellemont, and R. Schmolke. High resolution structure imaging of octahedral void defects in as-grown czochralski silicon. Jpn. J. Appl. Phys., 36:L1217–L1220, 1997. [9] J. Ryuta, E. Morita, T. Tanaka, and Y. Shimanuki. Crystal-originated singularities on si wafer surface after sc1 cleaning. Jpn. J. Appl. Phys., 29: L1947–L1949, 1990. [10] D. Gräf, M. Suhren, U. Lambert, R. Schmolke, A. Ehlert, W. von Ammon, and P. Wagner. Characterization of crystal quality by crystal originated particle delineation and the impact on the silicon wafer surface. J. Electrochem. Soc., 145:275–284, 1998. [11] D. Gräf, M. Suhren, U. Lambert, R. Schmolke, A. Ehlert, W. Von Ammon, and P. Wagner. Characterization of crystal quality by delineation of cop and the impact on the silicon wafer surface. In Electrochem. Soc. Proc., volume 96-13, pages 117–131, Pennington, NJ, USA, 1996. Electrochemical Society. [12] M. Itsumi, H. Akiya, M. Tomita, T. Ueki, and M. Yamawaki. Impurity dependence of oxide defects in czochralski silicon. J. Appl. Phys., 80: 6661–6665, 1996. [13] M. Tamatsuka, Z. Radzimski, G. A. Rozgonyi, S. Oka, M. Kato, and Y. Kitagawara. Medium field breakdown origin on metal oxide semiconductor capacitor containing grown-in czochralski silicon crystal defects. Jpn. J. Appl. Phys., 37:1236–1239, 1998. [14] T. Mera, J. Jablonski, M. Danbata, K. Nagai, and M. Watanabe. Structure of the defects responsible for b-mode breakdown of gate oxide grown on the surface of silicon wafers. In Defects in Electronic Materials II, volume 442, pages 107–112, Pittsburgh, PA, USA, 1997. Mater. Res. Soc. [15] M. Itsumi, M. Maeda, and T. Ueki. Dependence of the density of defects in the oxide on czochralski silicon on its thickness. J. Appl. Phys., 84: 1241–1245, 1998. [16] M. M. Heyns, S. Verhaverbeke, M. Meuris, P. W. Mertens, H. Schmidt, M. Kubota, A. Philipossian, K. Dillenbeck, D. Gräf, A. Schnegg, and R. de Blank. New wet cleaning strategies for obtaining highly reliable thin oxides. In MRS Symposium Proceedings, volume 315, pages 35–45, Pittsburgh, PA, USA, 1993. Mat. Res. Soc. [17] M. Miyazaki, S.Miyazaki, T. Kitamura, Y. Yanase, T. Ochiai, and H. Tsuya. Influence of crystal-originated ’particle’ microstructure on silicon wafers on gate oxide integrity. Jpn. J. Appl. Phys., 36:6187–6194, 1997. 82

[18] U. Lambert, A. Huber, J. Grabmeier, G. Obermeier, J. Vanhellemont, R. Wahlich, and G. Kissinger. Dependence of gate oxide integrity on grown-in defect density in czochralski grown silicon. Microel. Eng., 48: 127–130, 1999. [19] W. Cho, K. Lee, Y. Cha, C. Park, H. Shim, Y. Kim, and H. Kuwano. Effects of crystal originated particles on breakdown characteristics of ultra thin gate oxide. Jpn. J. Appl. Phys., 38:6184–6187, 1999. [20] F. González, M. R. Seacrist, M. J. Binns, A. Wang, S. Pirooz, and R. Barbour. Influence of crystal-originated pits on ultra-thin gate oxides. In Electrochem. Soc. Proc., volume 99-16, pages 496–509, Pennington, NJ, USA, 1999. Electrochemical Society. [21] Y. Satoh, T. Shiota, and H. Furuya. Simulation of degradation of dielectric breakdown field of thermal SiO2 films due to voids in si wafers. IEEE Trans. El. Dev., 47:398–403, 2000.

83

84

Chapter 6 Simulation of Crystal Originated Particles The results in this section have partly been published in: T. Bearda, P. W. Mertens, M. M. Heyns, R. Schmolke: Fabrication and characterization of artificial crystal originated particles. Japanese Journal of Applied Physics 38 (1999) L1509–L1511. T. Bearda, P. W. Mertens, M. M. Heyns, R. Schmolke: Morphology change of artificial crystal originated particles, and the effect on gate oxide integrity. Japanese Journal of Applied Physics 39 (2000) L841–L843.

In the previous chapter we studied the relation between Crystal Originated Particles (COP) and gate oxide degradation. The interpretation of the results relied on existing knowledge about the origin of the defects, and about their typical shape and size. Section 5.3 was a first attempt to investigate the relation between individual defects and oxide failure. Such an investigation is complicated by two factors. First, the position of the defects is uncontrolled. Usually a light scattering tool is used to determine an approximate location. The spatial resolution of a light scattering tool is limited by its laser beam spot size. For a state-of-theart instrument like the SP 1- TBi (KLA - TENCOR), this is 500 µ m2 . A COP of 100 nm 100 nm covers only 0.002% of this area. More precise coordinates of the defect can be obtained by subsequent Scanning Electron Microscopy (SEM) or Atomic Force Microscopy (AFM); however, searching the defect is not only labour intensive, but often also incompatible with further device fabrication on the same wafer. Second, the shape and the size of the defects is uncontrolled. Depending on the intersection of the original void with the wafer surface (see figure 5.1), the

85

defects vary in size and have different numbers of edges. Delineation of defects by etchants increases the spread further by widening ’old’ defects while opening up new defects at the surface. Treatments such as polishing may affect defects in different ways, depending on defect size and polishing parameters. Determining the shape of individual COP involves the same positioning problems as mentioned above. In section 6.1 we present a method to fabricate artificial COP with reproducible shapes and known positions. Metal-Oxide-Semiconductor (MOS) capacitors are fabricated on wafers containing these artificial defects, and their effect on the gate oxide is studied. In section 6.2 we compare the experimentally obtained results with computer simulations. First, oxide growth in v-grooves is investigated. Next, the simulated oxide profiles are used to calculate the electric field distributions. It is found that local variations of the oxide growth change the electrode curvature. The electrode curvature modifies the electric field distribution and results in a stress polarity dependence of the leakage current.

6.1 Artificial COP 6.1.1 Fabrication The substrates used in the experiments were highly doped 200 mm 100 p 9 -Si with a moderately doped epitaxial layer. A 20 nm nitride layer was patterned using a mask with 0.2–1.0 µ m diameter holes (pitch 1–2 µ m). By immersion for 4 min in a 5% Tetramethyl Ammonia Hydroxide (TMAH) solution at 80 C, artificial COP (ArtCOPs) were etched with 111 boundary planes and a typical size of 600 nm 600 nm in the surface plane. Figure 6.1 shows an ArtCOP after removal of the nitride layer with phosphoric acid. The total increase in area due to the presence of ArtCOPs is of the order of 10–15%. After preparation of the artificial COP, some wafers received additional treatments1 :

1. no treatment (as-etched) 2. polishing 3. deposition of 3 µ m epitaxial silicon at a ’low’ temperature of approximately 1100 C 4. deposition of 3 µ m epitaxial silicon at a ’high’ temperature of approximately 1200 C 5. Rapid Thermal Anneal (RTA) in 100% hydrogen for 30 s at approximately 1200 C 6. Anneal in 100% hydrogen for 60 min. at 1200 C 1 All

treatments were carried out by Wacker Siltronic, AG

86

Figure 6.1: Scanning Electron Microscope photograph of an artificial COP after etching in TMAH. Metal-Oxide-Semiconductor (MOS) capacitors were fabricated on wafers containing ArtCOPs. Gate oxides were grown in dry ambient at 800 C (4 nm and 6 nm on 100 oriented surface) and 900 C (7.5 nm, 15 nm). The capacitor structures were 100 µ m 100 µ m with a phosphorus doped poly-silicon gate. The number of ArtCOPs per capacitor varied with their pitch from none to several thousands.

6.1.2 As-etched ArtCOPs Morphology Figure 6.2 shows a cross-section Transmission Electron Microscope (TEM) photograph of neighbouring v-grooves after gate oxidation and poly-silicon deposition; because of their sharp tips, preparation of ArtCOPs for TEM was not possible. The fringes reveal the presence of significant mechanical stress. This may be caused by either poly-silicon deposition, which has a different thermal expansion coefficient than silicon, or by the gate oxidation, which is accompanied by a large volume expansion. Figure 6.3 shows a v-groove in more detail. The oxide on the 111 planes is thicker by approximately 40% compared to 100 planes. This agrees with the commonly observed differences on 100 and 111 oriented substrates [1, 2]. Figure 6.4 shows the distorted oxide growth in the tip of the v-groove for several oxide thicknesses. Table 6.1 lists the relative oxide thicknesses as determined from the photographs. In the case of 6 nm and 15 nm oxides, the oxide in the tip is significantly thin

87

+,)-. & ')(*

!#"%$

Figure 6.2: TEM photograph of neighbouring v-grooves.

/ 00)12

Figure 6.3: Cross-section TEM photograph of a v-groove after 15 nm gate oxide growth.

Figure 6.4: Cross-section TEM photograph of v-groove tips after gate oxide growth and poly-silicon deposition. The gate oxide thicknesses on the 100 surface are (from left to right): 4 nm, 6 nm, 7.5 nm, 15 nm.

ner than on the 100 plane. For the 15 nm oxide the effect is most pronounced. Negligible thinning is observed for 4 nm and 7.5 nm oxides. For the 7.5 nm oxide a higher oxidation temperature was used. This reduces oxide thinning effects [1]. Regardless of oxide thickness, the higher growth rate on 111 planes leads to a sharpening of the gate electrode. During etching of the ArtCOPs an undercutting of the hard mask occurs, leading to sharp features at the edges of the defects (figure 6.5). In section 6.1.3 we will show that these edges have a pronounced effect on the electrical characteristics with positive gate bias.

Electrical characterisation Figure 6.6 shows I V characteristics of capacitors with 15 nm gate oxides for positive and negative bias polarities. The presence of ArtCOPs results in a dras88

Table 6.1: Oxide thicknesses on 100 and 111 surfaces. Values are obtained from TEM photographs, and from HFCV measurements on capacitors with and without ArtCOPs. Also shown are the relative oxide thicknesses in the tip of v-grooves.

oxidation temp.

100 (nm) tox nominal HFCV

0~ 1 0~ 2

4 ~ 52 6 ~ 08

0 ~ 10 0 ~ 10

111 t 100 tox ox HFCV TEM

tip t 100 tox ox TEM

800 C

4~ 0 6~ 0

1 ~ 20 1 ~ 33

0 ~ 12 1 ~ 39 0 ~ 14 1 ~ 47

0 ~ 03 1 ~ 02 0 ~ 03 0 ~ 56

0 ~ 02 0 ~ 03

900 C

7 ~ 5 0 ~ 9 7 ~ 79 0 ~ 15 1 ~ 16 15 ~ 0 0 ~ 5 14 ~ 68 0 ~ 30 1 ~ 33

0 ~ 12 1 ~ 33 0 ~ 14 1 ~ 42

0 ~ 05 1 ~ 14 0 ~ 03 0 ~ 88

0 ~ 15 0 ~ 13

100

t = 15 nm ox -4 -2 area = 10 cm

current (A)

10-3 ∆V= 7.75 V

10-6 10-9 10-12 -25

Figure 6.5: TEM photograph of an ArtCOP edge with 6 nm gate oxide.

~2500 ArtCOPs as-etched

∆V= 6.5 V

no ArtCOPs

0 gate voltage (V)

25

Figure 6.6: Current-voltage characteristics of capacitors with and without ArtCOPs. In positive bias, the sample was illuminated to generate minority carriers.

89

tic increase of the leakage current. Because the oxide on the 111 surface is thicker than on the 100 surface, we assume that the increase in leakage current originates only from the ArtCOP edges and tips. With negative gate polarity, the degradation is stronger compared to positive gate polarity. A similar polarity dependence with real COP in figure 5.12 was explained by field enhancement due to electrode curvature. The interpretation is more complicated for the case of ArtCOPs, because of the edge features that are formed during etching (figure 6.5). In section 6.1.3 we will consider ArtCOPs with rounded edges after wafer polishing. Figure 6.7 shows I V curves for varying oxide thicknesses. To facilitate comparison, the results have been plotted as a function of electric field (after 100 as measured by HFCV, see correction for the flatband voltage, and using tox table 6.1). ArtCOPs do not appreciably degrade the 4 nm gate oxide in terms of leakage current or breakdown field. In contrast, the 6 nm and 7.5 nm oxides exhibit large leakage currents starting at approx. 6 MV/cm. The leakage current of the 15 nm oxide has an even earlier onset at about 3 MV/cm. This trend agrees well with the trend in figure 5.10, which suggests a threshold thickness of tox 5 nm for substrate-defect related failures. Infrared light emission was used to identify the position of the breakdown spots (figure 6.8). Breakdown events typically occur along the gate edge of the capacitors. This shows that the breakdown events are technology related. For this reason we decide not to use breakdown events (time-to-breakdown, breakdown voltage) to evaluate the impact of ArtCOPs. One exception is when the performance of the device is identical to that of a device without ArtCOPs; in that case ArtCOPs have no effect regardless of their position. High-frequency Capacitance-Voltage (HFCV) curves were measured at a frequency of 100 kHz (figure 6.9). Compared to intrinsic devices, capacitors with ArtCOPs have distinctly different curves. From the number of ArtCOPs per capacitor (approximately 1000) the total 111 surface area can be calculated. From TEM and SEM observations we estimate the uncertainty in the 111 area to be less than 10%, which includes the area increase due to undercutting. The extracted C V characteristics for the 111 and 100 areas were reproducible to within 2% (figure 6.9). Table 6.1 gives the resulting oxide thicknesses. The effective values for the 111 orientation include the effect of the ArtCOP tips 111 is systematically and edges. Oxide thinning in these regions explains why tox smaller with HFCV than in the TEM pictures.

90

10

no ArtCOPs ~2500 ArtCOPs

0

10

0

t = 6 nm

t = 4 nm

ox

10

-3

10

-6

10

-9

10

Current (A)

Current (A)

ox

-12

0

10

5 10 Electric field (MV/cm)

10

-3

10

-6

10

-9

10

15

0

-12

0

10

t = 15 nm

10

-6

10

-9

10

ox

Current (A)

Current (A)

ox

10

-12

0

15

0

t = 7.5 nm -3



10

-3

10

-6

10

-9

10

15

-12

0


15

Figure 6.7: Tunnel currents in capacitors with and without ArtCOPs. The device area was 100 µ m 100 µ m.

Figure 6.8: Infrared light emission during breakdown in a capacitor. The region between the dashed lines contains several thousands of ArtCOPs. The arrows indicate successive breakdown events.

2 3 1

91

1.0 Capacitance (µF/cm )

t = 4.52 nm

-2

ox

-2

Capacitance (µF/cm )

1.0

t

eff

= 5.44 nm

0.5

0.0 -4

0 Voltage (V)

ox

0.5

t

eff

0.0 -4

4

1.0

= 8.12 nm

0 Voltage (V)

4


1.0 -2

-2


t = 6.08 nm

t = 7.79 nm

0.5

ox

t

eff

0.0 -4

= 9.07 nm

0 Voltage (V)

0.5 t = 14.68 nm ox

t

eff

0.0 -4

4

= 19.51 nm

0 Voltage (V)

4

Figure 6.9: High-frequency capacitance-voltage characteristics. The curves for the 111 plane include the effect of edges and tips.

92

1:

as-etched

4:

2:

polishing

5:

epi 1200°C H RTA 1200°C

3:

epi 1100°C

6:

H anneal 1200°C

2

2

25

depth (nm)

0

1

-100

-200

3, 6

0

4

-25 5

-300

2

1

-0.5

-50 -3

0.0 0.5 distance (µm)

Figure 6.10: AFM profiles of ArtCOPs after polishing.

-2

-1 0 1 distance (µm)

2

3

Figure 6.11: Profiles of ArtCOPs after heat treatments, obtained with Atomic Force Microscopy.

6.1.3 ArtCOPs and wafer treatments Morphology Figures 6.10 and 6.11 show Atomic Force Microscope profiles of ArtCOPs before and after the treatments mentioned in section 6.1.1. The anneal treatments in hydrogen cause a significant restructuring of the substrate surface. From the AFM data, the area increase due to the presence of the ArtCOPs is reduced by more than 99% after RTA treatment. Since this restructuring takes place in 30 s, the disappearance of the ArtCOPs after 30 min. anneal is reasonable. The widening and smoothing indicate material migration from the edge to the tip [3]. The amount of material displacement can not be determined in these samples, because the distance between individual ArtCOPs is too small. During epitaxial silicon deposition the surface flattens in a similar way. Here, deposition at 1200 C preserves some topography, while the surface is flat after deposition at 1100 C. This is contradictory to what would be expected if material migration were dominant. However, it is known that surface patterns are better reproduced at higher deposition temperatures [4]. Because of the limited surface height variation, TEM photographs of MOS structures were not made after silicon deposition and hydrogen anneal. The polishing treatment reduces the size of the ArtCOP from 550 nm to approximately 40 nm. The top layer and the sharp features at the edges (figure 6.5) are removed (figures 6.10 and 6.12). The edges of the ArtCOP are even some-

93

1:

as-etched

4:

2:

polishing

5:

epi 1200°C H RTA 1200°C

3:

epi 1100°C

6:

H anneal 1200°C

2

2

0

10

as-etched -3

current (A)

10

2 -6

10

-9

10

3 4 5 6

2 1

1

3 4 5 6

-12

10

Figure 6.12: TEM photograph of a vgroove after polishing. The depth resolution is limited by the finite sample thickness. The gate oxide thickness is 15 nm. The dashed line represents the oxide/substrate interface in an asetched v-groove.

-25

0 gate voltage (V)

25

Figure 6.13: Current-voltage characteristics of capacitors with and without ArtCOPs. The wafers received various treatments before gate oxidation. The oxide thickness is 15 nm.

what smoothed after polishing. Comparison of the TEM photographs shows that the treatment does not substantially affect the tip of the v-groove. Electrical characterisation The effect of wafer treatments on the I V curves of capacitors is shown in figure 6.13. In the case of polishing, the negative gate leakage is reduced by roughly an order of magnitude. The reduction of the negative gate leakage current is related to the reduced length of the ribs after polishing. The disappearance of the positive gate leakage correlates with the removal of the sharp edge features (figure 6.5). We conclude that the gate leakage mainly originates from the edges in positive bias and from the ribs in negative bias. Wafer treatments involving high temperatures eliminate the leakage current for both polarities. Also the breakdown voltage is comparable to the intrinsic level. As in section 5.4.2, Constant Voltage Stress (CVS) measurements were performed to increase the sensitivity. The results in figure 6.14 do not show any effect of the presence of ArtCOPs on the time to breakdown.

94

no ArtCOPs ~2500 ArtCOPs as etched

Figure 6.14: Time to breakdown of capacitors with and without ArtCOPs for various wafer pre-treatments. The gate oxide thickness was 15 nm, the device area was 10 8 4 cm2 . The devices were stressed at a gate voltage of 19 ~ 5 V. On as-etched wafers and polished wafers, capacitors with ArtCOPs fail well below this voltage, and primarily along the gate edge. Therefore these conditions are not included in the graph.

not available

H anneal 2

H RTA 2

low-temp. epi high-temp. epi polish

not available 0

10

1

2

10 10 63% time to breakdown (s)

Figure 6.15: TEM photographs of v-grooves with deposited oxide. The nominal oxide thicknesses were 4 nm (left photograph) and 6 nm (middle photograph). Also shown is the deposition of 6 nm oxide on the edge (right photograph).

6.1.4 Deposited dielectrics Thermal oxide growth in ArtCOPs results in significant oxide thickness variations. Figure 6.4 shows that these variations change the shape of the gate- and substrate electrodes, independently of the oxide thinning effect. To estimate the importance of this morphology change, we have studied the effect of ArtCOPs on the electrical characteristics of deposited SiO2 . The oxide was deposited at a rate of 0.3 nm/min and a temperature of 780 C (High Temperature Oxide or HTO). The oxide layer was approximately 10% thinner on the 111 surface compared to the 100 surface. TEM photographs of v-grooves are shown in figure 6.15. In contrast to thermal oxide, the oxide in the tip is slightly thicker due to a ’fill-up’ with dielectric material. A similar oxide thickness increase is also expected in the ribs of the ArtCOPs. No variations of the oxide thickness were observed at the edges. The I V curves of capacitors without ArtCOPs with deposited oxides are similar to those of thermal oxides with the same oxide thickness (figure 6.16).

95

100

100 HTO oxide (t = 4.68 nm) ox

-3

ox

-6

10

10-9

ox

-3

10

thermal oxide (t = 4.52 nm)

current (A)

current (A)

10

HTO oxide (t = 6.08 nm)

2600 ArtCOPs

-12

thermal oxide (t = 6.56 nm) ox

-6

10

2600 ArtCOPs

10-9 -12

10

10

no ArtCOPs

no ArtCOPs

10-15 -10


10-15 -10

10


10

Figure 6.16: I V curves of capacitors with deposited gate oxides, with and without ArtCOPs. The shown oxide thicknesses were determined by means of HFCV. With positive gate bias the sample was illuminated. Devices with 2500 ArtCOPs have 1.5–2.0 times higher leakage currents, independently of stress polarity. If this leakage would originate from field distortion, a polarity dependence should be observed. We conclude that the leakage stems mainly from the slightly thinner oxide on the 111 planes. For negative stress polarity, the breakdown voltage is not affected; for positive polarity, a VBD reduction is beyond the detection limit due to the limited current injection. ArtCOPs did not degrade the time to breakdown distributions in 4 nm oxides; using the light emission microscope, failures of the 6 nm oxides were primarily found to occur along the gate edge. Compared to thermal oxides, the defect-induced leakage current in deposited oxides has almost disappeared. This is partly explained by the fill-up of the tips and ribs of the ArtCOPs. However, also the conformal coverage of the edges does not increase the leakage current. This indicates that the thickness variations of thermal oxides indeed contribute significantly to the increased gate current in capacitors with ArtCOPs.

6.2 Computer simulations In the previous section we observed significant oxide thickness variations in the edges and tips of ArtCOPs. These variations induce local electric field variations if a bias is applied to the gate. However, in the edges and tips the electric field will also be non-uniform, being amplified near convex electrodes and diminished near concave electrodes (field distortion). The electric field variations in a COP are therefore a combination of oxide thickness variations and field distortion. 96

The simultaneous occurrence of the two mechanisms makes it difficult to distinguish their effects. In the current section we will first study the oxidation of a non-planar silicon surface. To limit the simulation time, two-dimensional vgrooves were considered. The simulated oxide profiles are then used to calculate the electric field distributions.

6.2.1 Simulation of oxide growth Model for stress dependent thin oxide growth Oxidation of 100 silicon increases the material volume by a factor of approximately 2. This results in an expansion of the oxide layer in the direction normal to the substrate surface. Compressive stress in the oxide restrains the volume increase in lateral direction. If the oxide is present at only one side of the substrate, the substrate is bent to relieve this stress. This shows that structures, that accommodate the volume expansion differently, may lead to varying stresses and oxide thicknesses. An example is LOCOS (’local oxidation of silicon’) isolation: thick field oxides, locally confined by nitride layers, exhibit significant stresses and stress-induced oxide thinning. The stress phenomena associated with LOCOS isolation initiated the development of stress-dependent oxide growth models. Most of these models were developed as an extension of the Deal-Grove model. The Deal-Grove model describes oxide growth well for the case of thick oxides ( 25 nm). It postulates that the oxidant diffuses through the oxide to react at the oxide/silicon interface. Important parameters are the diffusivity D and solubility C of the oxidising species in the oxide, and the surface reaction rate ks . The effect of stress on oxide growth was extensively studied in Refs. [1, 5, 6]. The stress dependencies of ks , D and C were described with Arrhenius-like functions:

σnnVk (6.1) kT pVD D D0 exp (6.2) kT pVs C C0 exp (6.3) kT with Vk , VD and Vs material dependent ’activation volumes’, σnn the normal stress at the Si-SiO2 interface, and p the hydrostatic pressure in the oxide. This approach is adopted by most models, although equation (6.3) is usually omitted. For the stress dependence of the oxide viscosity η , the following expression [7] replaces the one in Ref. [6]:

ks

ks0 exp

η

η0 T

σsV0 2kT sinh σsV0 2kT 97

(6.4)

where σs the shear stress, and V0 a fitting parameter resembling the activation volumes above. Application of this so-called "visco-elastic" model to the growth of thin gate oxides is not evident for a number of reasons. • Oxide growth strongly depends on technological issues such as substrate doping, pre-oxidation cleaning, and variations in oxidation ambient. As a result, the reported values for the parameters in equations (6.1) to (6.4) vary significantly between different publications, see table 6.2. Specifically, these values are only valid for oxides grown in a wet ambient, as normally used for LOCOS. • The stress dependencies are described in terms of the Deal-Grove model. This works well for oxides thicker than approximately 25 nm [8]. However, the Deal-Grove model clearly underestimates the growth rate of thinner oxides. Various alternatives have been proposed; some models are modifications of the Deal-Grove model, others assume fundamentally different mechanisms [9]. Consequently, equations (6.1) to (6.4) possibly do not adequately describe thin oxide growth. Clearly, a model for the stress dependence of thin oxide growth is lacking at this moment. • In-plane stress is generally neglected during oxidation modelling; yet it is known that it affects thin oxide growth [10, 11, 12]. The process simulator SUPREM - IV offers the possibility to specify an activation volume VT associated with the in-plane stress component; however, no values are presently available for this parameter. We conclude that the stress dependence of thin oxide growth is not well understood, and that consequently an accurate simulation, based on a physical understanding, is not yet possible. Our aim is to qualitatively reproduce trends, rather than produce a quantitative fit of actually observed oxide profiles. Model parameters should be considered fitting parameters with limited physical meaning and range of validity. Simulation structure The simulation structure used in this study is a v-groove with 111 boundary planes (figure 6.17). Due to the symmetric shape, only half of the structure needs to be simulated. Because in reality the COP tip is not infinitely sharp, the tip radius was varied between 0 nm and 30 nm. All simulations were carried out using the process simulator SUPREM - IV. The visco-elastic oxidation model that is used incorporates equations 6.1, 6.2 and 6.4 as well as terms for oxide reflow and surface tension. The oxidation ambient was specified as 5% oxygen and 5% hydrogen at atmospheric pressure and a temperature of 800 C. The growth

98

Table 6.2: Reported values for parameters describing the stress dependence of oxide growth. Values for oxidation temperatures of 800 C and 1000 C are shown; all oxidations were in wet ambient. Refs. [7, 13] make use of the data in Ref. [1].

800 C VD (Å3 )

Vk (Å3 )

η0 (poise)

75 75 75

25 12.5 15 15

1 2 2 9

1015 1015 1014 1015

1000 C V0 (Å3 )

180 350 300

VD Vk 3 (Å ) (Å3 )

75 75 75 100 46

25 12.5 15 15 25 30

η0 (poise)

V0 (Å3 )

1013 1013 1012 1014

340 440 300

2 1014

450

3 7 4 2

Ref.

[6] [7] [14] [13] [15] [16]

rate constants are based on the partial pressure of H2 O. Table 6.3 lists the most important parameter values that were used in the simulations. It should be noted that the orientation dependence of the Young’s modulus and the Poisson ratio is not included in SUPREM - IV.

6.2.2 Simulation of field distortion The simulated oxide profiles were loaded in the device simulator MEDICI to calculate the electric field distribution. Charge tunnelling through the gate oxide was not taken into account. The gate electrode was n 9 poly-silicon. The doping level of the p-type substrate was 1015 cm 8 3 ; its dimensions were large enough to ensure that the boundaries did not influence the simulation results (depth 10 µ m, width 0.5 µ m). In the simulations, the electric field in the oxide on the 100 plane was fixed at 0.1 MV/cm or 1 MV/cm.

6.2.3 Results and discussion Figure 6.18 shows simulation results for oxide growth in a v-groove with two different tip radii. Clearly visible are the orientation dependence of the oxide growth rate, and the oxide thinning at the edges and at the tip. Figure 6.19 shows the oxide thickness in the tip as a function of the oxidation time. The initial oxide growth in the tip does not show a difference with the 100 surface, but the

99

Figure 6.17: Structure for simulating oxide growth in a v-groove. The tip radius is 10 nm.

Table 6.3: Parameter values for simulation of oxide growth.

linear rate constant

B A

parabolic rate constant

B

Young’s modulus

E

Poisson ratio

ν

Activation volumes

VD Vk V0

100

100 110 111

silicon oxide silicon oxide

0.319 Å/min 0.445 Å/min 0.535 Å/min 0.457 Å2 /min 187 GPa 66 GPa 0.28 0.17 0 Å3 15 Å3 225 Å3

@

' ( ) !#"$&%

ACBD ;

E5M N O F&GIHJLK *+ ,.-/102#35476 8:9

Figure 6.18: Simulated oxide profiles in a v-groove with tip radii of 10 nm (left) and 20 nm (right). The profiles are plotted in intervals of 100 min. oxidation time. The dashed line is the initial silicon surface. growth rate decreases as the thickness exceeds 3–5 nm. The higher oxidation rate of the 111 planes initially leads to a sharpening of the gate electrode tip. For prolonged oxidation times and small tip radii, the simulations show a marked oxide thickness increase as the oxides on the two opposite 111 planes meet. Additional experiments with different oxidation times are required to study this effect in more detail. When comparing the simulated oxide profiles (figure 6.18) with experimentally observed profiles (figure 6.4) we note important similarities: the orientation dependence of the oxide thickness, the low oxidation rate in the tip, and the resulting sharpening of the gate tip. The main differences are the tip radius and the

Figure 6.19: Simulated oxide thicknesses in v-groove tips for different tip radii. Also shown is the oxide thickness on the 100 surface.

oxide thickness (nm)

20 rtip=10nm

15

rtip=20nm

10

5

0 0

100 200 300 400 oxidation time (min)

500

101

Figure 6.20: Simulated oxide profiles in the tip of a v-groove for two values for Vk . The tip radius was 10 nm. The profiles are plotted in intervals of 100 min. oxidation time. The dashed line is the initial silicon surface.

occurrence of the ’bump’ for the 15 nm oxide in figure 6.4. Both can be adjusted in the simulations by proper choice of rtip and Vk . As an example figure 6.20 shows the simulated oxide profile for two values of Vk . We conclude that, using the model in SUPREM - IV , a reasonably accurate description of oxide growth in v-grooves is possible. Figure 6.21 shows the simulated field distributions for low and high electric fields and for several oxide thicknesses. Considering the 4 nm gate oxide, three main effects are observed. Firstly, at 0.1 MV/cm the field enhancement in the tip of the v-groove is larger in depletion (small positive bias) than in accumulation (small negative bias) (figures 6.21a and b). Secondly, for both polarities the variations in the relative field strength is larger at 0.1 MV/cm than at 1 MV/cm (see figures 6.21c and d). Thirdly, the polarity dependence is absent at 1 MV/cm. The absence of polarity dependence at high fields is explained by the presence of the inversion- or accumulation layer. The charge in this layer varies exponentially with the amount of band bending in the substrate. Hence to a first approximation in inversion or accumulation the surface potential is pinned. In contrast, the voltage over the gate oxide varies linearly with the amount of charge. Any change in Vgate therefore appears almost completely over the gate oxide, independently of bias polarity. Due to the inversion- or accumulation layer, this voltage drop across the oxide is constant throughout the structure. The electric field in the oxide is only determined by the oxide thickness and by the curvature of the two oxide interfaces. At low fields (0.1 MV/cm), the valence or conduction band do not yet cross the fermi level, so that no accumulation or inversion layers are present. In this case, the potential difference over the oxide (and therefore the electric field in the oxide) is affected by band bending in the substrate. This may vary with position in the v-groove. Because the dielectric displacement is continuous at the interface (εox Eox εSi ESi ) we consider the electric field in the substrate using Gauss’ Law: 102

(a) accumulation 100 =4 nm MV/cm; tox

100 =0.1 Eox

(b) depletion 100 =4 nm MV/cm; tox

(c) accumulation 100 =4 nm MV/cm; tox

100 =1 Eox

100 =0.1 Eox

(d) inversion 100 =4 nm MV/cm; tox

100 =1 Eox

(e) accumulation 100 =7 nm MV/cm; tox

(f) accumulation 100 =15 nm MV/cm; tox

100 =1 Eox

100 =1 Eox

Figure 6.21: Calculated electric field distributions in v-grooves with different gate oxide thicknesses. The electric field strength is plotted relative to its value on the 100 surface. The tip radius is 10 nm.

103

Figure 6.22: Schematic representation of an MOS structure with curved electrodes. The edge of the space charge region is indicated by the dashed line.

S

εSiESi ds

ρSidV

V

(6.5)

with ρSi the space charge density in the substrate. ESi reaches its maximum value Emax at the oxide/substrate interface, and it vanishes at the edge of the space charge region. For convenience we describe this region with a cylindrical symmetry (figure 6.22). The radius of curvature of the oxide/substrate interface is r0 . Application of Gauss’ Law to the hatched region in figure 6.22 results in

ρSixSC 1

εSiEmax

xSC 2r0

(6.6)

In depletion, xSC is the depletion region width and ρSi scales with the dopant concentration. In a planar structure (r0 ∞) equation 6.6 reduces to a common expression for Emax . If r0 xSC the field enhancement is expected to be significant. This is the case in the v-groove in figure 6.21b. In accumulation less band bending is required to obtain the same amount of charge at the gate, so that xSC is smaller than in depletion. As a result the field enhancement is smaller as well, in agreement with figure 6.21a. With increasing gate oxide thickness, the variation in relative field strength in the v-groove tip increases. In the case of 7 nm oxide, the field is locally enhanced due to variations in the oxide growth rate (6.21e). For the 15 nm gate oxide, the field is enhanced at the gate/oxide interface, while it is reduced at the oxide/substrate interface (6.21f); this is a clear example of field distortion due to electrode curvature. Distortion is more pronounced in thick oxides due to the gradual sharpening of the substrate edges and the gate tip. It shows that the oxidation affects oxide thinning, electrode curvature, and their relative impact on the electric field distribution. The expected field enhancement in the tip due to thinning alone is calculated as tip Eox 100 Eox

tip Vox tox 100 Vox tox

100 tox tip tox

(6.7)

The actual deviation from this value at either interface of the oxide is caused by the electrode curvature. Both contributions are known from the simulation results and are shown in figure 6.23. 104

rtip=10 nm

relative electric field strength

relative electric field strength

3

gate/oxide interface

2 due to thinning only

1 oxide/substrate interface

0

3

rtip=20 nm

2

gate/oxide interface

due to thinning only

1 oxide/substrate interface

0 0

5 10 15 oxide thickness (nm)

20

0


20

Figure 6.23: Calculated electric field in a v-groove tip, relative to the field in oxide on a planar 100 surface. Shown are values at the gate/oxide interface, oxide/substrate interface, and the field enhancement that is due to thinning alone.

Figure 6.24: Simulated oxide profile in the tip of a v-groove after 100 min. oxidation (corresponding oxide thickness: 4 nm). The oxide in the tip can be described with a coaxial cylindrical capacitor. The dashed line is the initial silicon surface. The figure shows that, over a large range of oxide thicknesses, field distortion due to electrode curvature dominates over oxide thinning. Figure 6.24 illustrates the effect of electrode curvature. Shown is the simulated profile of a 4 nm oxide in a v-groove. Also shown is an approximation of this structure by a cylindrical capacitor with concentrical electrodes. Clearly the validity of the model is limited. The higher oxidation rate of the 111 plane sharpens the gate electrode, even though there is no oxide thinning. This sharpening becomes more pronounced for thicker oxides. We conclude that the electrode curvature is amplified by variations in the oxidation rate, and that its effect on the electric field is stronger than that of oxide thinning alone. The effect of field distortion is a function of stress polarity. This is illustrated in figure 6.25. In the case of a convex electrode, the field is enhanced at the injecting electrode, causing a reduction of the tunnel distance for Fowler-Nordheim Tunnelling (FNT) and a corresponding increase of the leakage current. For concave electrodes, the same amount of field distortion leads to an increase of the tunnel distance for FNT. This explains the polarity dependence of the leakage

105

Direct Tunneling

Fowler Nordheim Tunneling tunnel distance reduction cathode

tunnel distance increase injected electrons

cathode

injected electrons

cathode

anode anode

convex cathode

anode

concave cathode

Figure 6.25: Effect of field distortion on the injection of electrons in a MOS structure: Fowler-Nordheim tunnelling from a convex cathode (left) and a concave cathode (middle). Also shown is the band diagram for direct tunnelling (right). current due to ArtCOPs (figure 6.6) and of the breakdown voltage in real COP (figure 5.12). Also shown in figure 6.25 is the case of Direct Tunnelling (DT) in ultra-thin gate oxides. Now, field distortion does not alter the tunnel distance, and the effect of field distortion will be relatively small compared to thicker oxides. In figure 6.26 we calculated the transmission probability in a concentric cylindrical capacitor using equation 2.3. The figure shows that, for the same stress level, the transmission probability in the direct tunnelling regime is relatively insensitive to electrode curvature. The combined effect of reduced oxide thinning (figure 6.19), reduced field distortion (figure 6.23) and reduced sensitivity for field distortion (figure 6.26) provides a consistent explanation for the experimentally observed tox dependence of COP-induced oxide failures.

106

Figure 6.26: Transmission probabilities as a function of oxide thickness. The structure is a concentric cylindrical capacitor with r0 the radius of the oxide/substrate interface. The voltage drop across the oxide was chosen such that Vox tox 10 MV/cm. The dashed line indicates the transition from direct tunnelling to Fowler-Nordheim Tunnelling, assuming a barrier height of 3.15 eV.

transmission probability

100 V /t ox

10-3

ox

=

10 MV/cm r = 5 nm 0

10 nm

-6

10

20 nm -9

10

-12

10

0

planar oxide Direct Tunneling

Fowler-Nordheim Tunneling


8

6.3 Conclusions The effect of artificial Crystal Originated Particles (COP) on the gate oxide integrity has been analysed. Artificial COP with known position and shape were etched in the substrate using an anisotropic etchant. Thermal oxides grown in these defects exhibit higher oxidation rates on the 111 planes, and stress limited oxide growth at defect edges and tips. Due to this variation in oxidation rate, convex electrode regions become sharper, leading to field distortion. The gate oxide degradation due to ArtCOPs depends on the oxide thickness and oxidation conditions. Oxides between 4 nm and 6 nm show a transition from intrinsic tunnel current to a large increase in leakage current due to ArtCOPs. With real COP a similar trend in the oxide degradation was observed. This thickness dependence is due to a combination of factors. Experimental observations and computer simulations show that stress induced oxide thinning is less pronounced in 4 nm oxides than in thicker oxides; this reduces field enhancement due to oxide thinning. Less oxide thinning also implies a reduction of local variations in oxidation rate, which determines the electrode curvature. Consequently, field distortion becomes less pronounced. Moreover, direct tunnelling is less sensitive to field distortion than Fowler-Nordheim tunnelling. Wafer treatments involving a high temperature treatment in hydrogen cause a restructuring of the silicon surface. The limited surface height variation after these treatments do no longer degrade the gate oxide. Wafer polishing does not affect the defect tips but only the defect edges. This results in a pronounced polarity dependence of the ArtCOP induced leakage current. Also deposited dielectrics have been considered. The dielectric was slightly thinner on the 111 planes, resulting in a limited increase of the leakage current. It was thicker in the defect tip, which prevents reduction of the breakdown voltage in gate injection. With substrate injection such a reduction was beyond the detection limit but it can not be excluded.

107

References [1] D.-B. Kao, J. P. McVittie, W. D. Nix, and K. C. Saraswat. Two-dimensional thermal oxidation of silicon - I. experiments. IEEE Trans. El. Dev., 34: 1008–1017, 1987. [2] E. A. Taft. Thin thermal oxides of silicon and the orientation effect: an empirical approach. J. Appl. Phys., 69:3733–3738, 1991. [3] Y. Yanase, H. Nishihata, T. Ochiai, and H. Tsuya. Atomic force microscope observation of the change in shape and subsequent disappearance of "crystal originated particles" after hydrogen-atmosphere thermal annealing. Jpn. J. Appl. Phys., 37:1–4, 1998. [4] H. M. Liaw and J. W. Rose. Epitaxial Silicon Technology, chapter Silicon vapor-phase epitaxy. Academic Press, Inc., Orlando, Florida, USA, 1986. [5] D.-B. Kao, P. McVittie, W. D. Nix, and K. C. Saraswat. Two-dimensional silicon oxidation experiments and theory. In Techn. Dig. IEDM, pages 388– 391, New York, NY, USA, 1985. IEEE. [6] D.-B. Kao, J. P. McVittie, W. D. Nix, and K. C. Saraswat. Two-dimensional thermal oxidation of silicon - II. modeling stress effects in wet oxides. IEEE Trans. El. Dev., 35:25–37, 1988. [7] P. Sutardja and W. G. Oldham. Modeling of stress effects in silicon oxidation. IEEE Trans. El. Dev., 36:2415–2421, 1989. [8] V. Senez, D. Collard, P. Ferreira, and B. Baccus. Two-dimensional simulation of local oxidation of silicon: calibrated viscoelastic flow analysis. IEEE Trans. El. Dev., 43:720–731, 1996. [9] C. J. Sofield and A. M. Stoneham. Oxidation of silicon: the VLSI gate dielectric? Semicond. Sci. Techn., 10:215–244, 1995. [10] T. J. Delph. Intrinsic strain in SiO2 thin films. J. Appl. Phys., 83:786–792, 1998. [11] J. Tersoff, Y. Tu, and G. Grinstein. Effect of curvature and stress on reaction rates at solid interfaces. Appl. Phys. Lett., 73:2328–2330, 1998. [12] A. Mihalyi, R. J. Jaccodine, and T. J. Delph. Stress effects in the oxidation of planar silicon substrates. Appl. Phys. Lett., 74:1981–1983, 1999. [13] V. Senez, D. Collard, B. Baccus, M. Brault, and J. Lebailly. Analysis and application of a viscoelastic model for silicon oxidation. J. Appl. Phys., 76: 3285–3296, 1994. 108

[14] K. V. Loiko, I. V. Peidous, Y. Zu, and H.-M. Ho. Experimental study of Si3 N4 viscosity for calibration of stress-dependent models of silicon oxidation. J. Electrochem. Soc., 146:4226–4229, 1999. [15] H. Umimoto, S. Odanaka, I. Nakao, and H. Esaki. Numerical modeling of nonplanar oxidation coupled with stress effects. IEEE Trans. ComputerAided Design, 8:599–607, 1989. [16] V. Senez, A. Tixier, and T. Hoffmann. Calibration of a 2d numerical model for the optimization of LOCOS type isolations by response surface methodology. In 4th Int. Workshop on Statistical Metrology, pages 50–53, Piscataway, NJ, USA, 1999. IEEE.

109

110

Chapter 7 Summary and conclusions Gate oxide breakdown is an important failure mode in Metal-Oxide-Semiconductor (MOS) devices. The study of breakdown events is therefore a relevant tool to evaluate the Gate Oxide Integrity (GOI). In this thesis we have discussed the detection and characterisation of different types of breakdown. We have also investigated several possible extrinsic causes of breakdown.

7.1 Characterisation of breakdown phenomena 7.1.1 Detection of breakdown Hard Breakdown (HBD) and Soft Breakdown (SBD) events in MOS capacitors have been studied in measurement setups with a high time resolution and with varying source impedance. Breakdown events are sometimes followed within a few milliseconds by a partial recovery. Recovery is a transition of the device from a high-conductivity state after breakdown to a low-conductivity state. Recovery occurs most often in measurement systems with a low impedance. This is the case with a voltage source, or with a current source if appropriate stress conditions are chosen (large areas or high stress levels). It was shown that with a low system impedance a high stress level is maintained over the device after breakdown. From this it is concluded that the breakdown path is subject to a wear out mechanism, leading to recovery of the device. Breakdown is normally detected as a conductivity increase of the gate oxide. The detection is therefore more difficult if the conductivity of the oxide is already large before breakdown, which is the case with large area devices. Prevention of recovery, by measuring with a high-impedance system, increases the sensitivity to SBD events. This setup also resembles more closely the situation in integrated circuits.

111

Suggestions for future work As section 2.3.3 points out, several models explain post-SBD conductivity in terms of the degradation mechanism that precedes breakdown. However, figure 3.9 shows that recovery results in a region in the gate oxide that can easily be etched by a hot TMAH solution. Because charge transport mechanisms in gate oxides depend strongly on material properties, it may be expected that charge transport before and after recovery differ significantly. For this reason, it is proposed to avoid recovery when studying post-SBD conduction. When recovery is avoided, it is observed that the conductivity fluctuates between discrete levels. These fluctuations have been studied to some detail [1], and they were attributed to traps in the oxide. However, many properties remain unclear, such as the physical nature of the traps, and their spatial distribution in the oxide. If the traps are indeed related to the oxide degradation prior to breakdown, the fluctuations are of interest to understand the reliability behaviour of gate oxides. In section 3.1.3 it was suggested, that recovery is a thermal process. To confirm this, a method is needed that reveals heat generation in small areas (order of 10 nm) during a short time (order of ms). Using infrared emission microscopy, it has not yet been possible to detect heat generation during recovery. Alternative methods make use of phosphorous diffusion [2], thermally sensitive films [3] or thermo-reflectance [4]. These methods are more sensitive, but require dedicated processing or measurement facilities.

7.1.2 Charge transport after breakdown The charge transport after Hard Breakdown (HBD) in MOS capacitors was studied experimentally and by means of computer simulations. An n 9 -Si/oxide/pSi structure after breakdown resembles a gated diode with gate and drain electrode connected. Therefore the device operation is complex and three operation regimes can be distinguished. In reverse bias the leakage current is low ( 50 pA/cm2 ) and scales with device dimensions due to the presence of a depletion layer below the gate. The current is dominated by minority carrier generation in the depletion layer and by diffusion current from the neutral substrate. In forward bias with Vgate VFB the ideality factor is close to unity, and the current scales with device dimensions due to the inversion layer. For Vgate VFB ("high injection regime") the inversion layer disappears, and the current varies with the breakdown spot size. In n 9 -Si/oxide/n-Si devices after breakdown two different regimes are distinguished. In both regimes majority carriers dominate the charge transport, and the current is limited by spreading resistance. If an accumulation layer is present (Vgate VFB ), the spreading resistance scales with the device dimensions; without accumulation layer (Vgate VFB ) it depends on the breakdown spot size.

112

Suggestions for future work In the case of soft breakdown, the conductivity of the breakdown path is generally believed to be much smaller than after hard breakdown. Variations in the conductivity after SBD are therefore often attributed to the breakdown spot itself. In this thesis the conductivity after hard breakdown was found to depend also on substrate properties (resistivity, i.e. doping level, and carrier lifetimes). A similar dependence may be expected for charge transport after soft breakdown, but this has not been systematically studied before. It should be noted that the breakdown path is essentially a point contact to the substrate. A comparison with existing literature on point contacts may therefore be useful, and allow a better understanding of the nature of the breakdown path. A breakdown path in a transistor is more complex to analyse, because it is longer a two-dimensional problem. The source and drain regions strongly influence the behaviour of minority carriers. It has recently been shown that an NMOS transistor after hard breakdown may be considered a bipolar npn transistor. Such an ’equivalent circuit’ approach is expected to be useful in understanding the effect of breakdown in integrated circuits. This can be used to design a circuit in a way that breakdown is recognised and handled in a proper way.

7.2 Extrinsic causes of breakdown We have studied oxide breakdown to characterise the Gate Oxide Integrity (GOI) in the presence of extrinsic defects. ’Defect’ in our definition is a local feature in the oxide that facilitates the formation of the conduction path. Intrinsic defects are defects induced by the wear-out mechanism of the oxide. Extrinsic defects are defects that are already present in the oxide. We considered two possible sources of extrinsic defects: metallic contamination, and crystalline substrate defects.

7.2.1 Metallic contamination The effect of metal contamination on the gate oxide integrity has been investigated. The results were explained in terms of the contaminant behaviour during gate oxidation and poly-silicon deposition. This behaviour depends on the contaminant solubility and diffusivity in silicon, on the affinity to form metal compounds and on the vapour pressures. Group II metals interact strongly with the silicon surface, leading to high GOI defect densities. Transition metals often form oxides during oxidation. This results in poly-silicon roughness (Ti, V, Cr) and oxide failures. Some metals (Cu, Ru, Pt) diffuse into the substrate, and are relatively harmless for GOI. Cross contamination was only observed for Zn and Pb.

113

For evaluation of the metal concentrations Total Reflection X-Ray Fluorescence (TXRF) was used before and after gate oxidation. The detection efficiency of the TXRF measurements depends on whether the contamination is ’particletype’ or ’film-type’. It also depends on the distribution of the contaminant in the gate oxide. This complicates interpretation of the measurement results. Alternatively, the contamination can be dissolved in an acid droplet that is scanned over the wafer surface. After drying the droplet, its content can be measured with TXRF. Comparison of the measurement results shows, that a quantitative interpretation of this procedure requires calibration of the TXRF response and of the droplet collection efficiency, using an independent technique. Suggestions for future work The results in chapter 4 indicate that the contamination on the wafer surface results from water evaporation during spinning. This is a realistic situation, because any wafer drying method involves the evaporation of water [5]. However, the contamination level also depends on the pH of the spinning solution [6]. This can not be explained by water evaporation alone, and suggests the presence of other contamination mechanisms. The chemical state of contaminants is expected to yield information about these mechanisms. This is important to optimise cleaning, and to understand the effect of subsequent wafer treatments. However, relevant techniques such as X-ray Photon Spectroscopy (XPS) have detection limits of 1014 atoms/cm2 or higher, which is too high for realistic case studies. As an alternative, indirect experimental evidence may be obtained by using known properties of contaminant species. For example, the metal concentrations after heat treatments at varying temperatures may reflect the different vapour pressures of metal oxides and salts. In the particular case of gate oxidation, a dependence of the contaminant behaviour on the (ramp-up) ambient is anticipated as well. For example, a reduced oxygen content during ramp-up may promote contaminant in-diffusion [7]. Such dependencies become more relevant with the introduction of alternative gate dielectrics (nitrided oxides, deposited high-k dielectrics). For this reason, regarding the impact of metal contamination, both the range of contaminants and the range of processing conditions should be increased. The experimental results have identified several problems in the interpretation of TXRF data. Calibration of the measurement procedure has already been mentioned as a possible solution. Also a critical evaluation of the procedure itself may extend the measurement window. For example, optimisation of the droplet scanning and droplet drying may enhance the TXRF detection efficiency.

114

7.2.2 Void-related substrate defects The effect of vacancy-related crystalline defects, so-called ’voids’, on the gate oxide integrity has been investigated. In line with theoretical analysis, most failures were shown to be due to voids appearing at the surface (Crystal Originated Particles, COP). The defects have decreasing impact with decreasing oxide thickness, and below approximately 5 nm no oxide degradation was found. As an aid in studying the effect of COP on GOI, artificial COP (ArtCOPs) and v-grooves have been fabricated. Gate oxides grown in these defects exhibit strong oxide thinning, depending on oxidation conditions and oxide thickness. The oxide thickness dependence of the GOI degradation resembles well the case of real COP. From the polarity dependence of the leakage current we conclude that this is partly due to field distortion and partly due to oxide thinning. This agrees with computer simulations of oxide growth and field distortion in v-grooves. Moreover, we show that the effect of field distortion on electron tunnelling becomes less pronounced as the tunnel mechanism changes from FowlerNordheim Tunnelling to Direct Tunnelling. The effect of wafer treatments on the ArtCOP morphology has been studied. Polishing removes the edges of the ArtCOPs. This correlates with the disappearance of the leakage current with positive gate bias. The reduction of the rib length reduces the leakage current with negative gate bias. The tip of the defect is not affected, which explains why breakdown still occurs at low voltages. Heat treatments above 1100 C in hydrogen, or epitaxial silicon deposition, induce widening and rounding of all defect features. As a result, gate oxides grown in these defects show no detectable GOI degradation. In case of a deposited gate dielectrics, no effect of as-etched ArtCOPs on GOI was observed due to a larger oxide thickness in concave substrate corners. Suggestions for future work We have mainly focused on gate oxide breakdown due to stress induced oxide thinning and field distortion. However, stress (figure 6.2) can affect the electrical characteristics in several ways, such as atomic bond weakening [8, 9] or by changing of the silicon bandgap. Moreover, stress induced gettering of metal impurities can not be excluded [10]. These effects have not been investigated. Using electron diffraction techniques it may be possible to have an indication of the strain fields in the devices. In a more pragmatic approach, different types of gate stacks can be used to vary the strain in the substrate. With the reduction of void-related breakdown of thin oxides, other modes of void-related device failure may become more pronounced. For example, the impact of COP on transistor operation is not known. Currently, the transistor dimensions are reduced to below the typical COP size, which may cause significant defect-induced junction leakage. With ArtCOPs, it is possible to study these effects. Similarly, the effect of substrate defects on isolation related device failures 115

has only recently been recognised [11]. In this thesis no effect of ArtCOPs on deposited oxides was found, due to the larger oxide thickness in concave defect regions. In the case of deposited high-k dielectrics, the oxide thickness in these regions depends on the process details. Therefore, field distortion may still have a significant effect, especially if Fowler-Nordheim Tunnelling is the dominating tunnelling mechanism. This remains to be tested using dielectrics such as Al2 O3 or HfO2 .

References [1] F. Crupi, R. Degraeve, G. Groeseneken, T. Nigam, and H. Maes. Investigation and comparison of the noise in the gate and substrate current after soft-breakdown. Jpn. J. Appl. Phys., 38:2219–2222, 1999. [2] K. Yamabe, K. Taniguchi, and Y. Matsushita. Thickness dependence of dielectric breakdown failure of thermal SiO2 films. In Proc. Int. Rel. Phys. Symp., volume 21, pages 184–190, New York, NY, USA, 1983. IEEE. [3] R. E. Anderson, J. M. Soden, C. L. Henderson, and E. I. Cole. Challenges for IC failure analysis - present and future. In Proceedings of the 1995 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits, pages 1–8, New York, NY, USA, 1995. IEEE. [4] Y. S. Ju, O. W. Käding, Y. K. Leung, S. S. Wong, and K. E. Goodson. Short-timescale thermal mapping of semiconductor devices. El. Dev. Lett., 18:169–171, 1997. [5] W. Fyen, F. Holsteyns, P. W. Mertens, J. Lauerhaas, and M. M. Heyns. Estimation of evaporating water film during different drying processes. In Electrochem. Soc. Proc., Pennington, NJ, USA, 2001. The Electrochemical Society. submitted. [6] L. M. Loewenstein, F. Charpin, and P. W. Mertens. Competitive adsorption of metal ions onto hydrophilic silicon surfaces from aqueous solution. J. Electrochem. Soc., 146:719–727, 1999. [7] P. W. Mertens, S. de Gendt, M. Depas, K. Kenis, A. Opdebeeck, P. Snee, D. Gräf, G. Brown, and M. M. Heyns. Effect of fe contamination on 5 nm oxide-poly silicon gate structures. In 3rd Int. Symp. Ultra Clean Processing of Silicon Surfaces, pages 33–36, Leuven, 1996. Acco. UCPSS, September 23–25, 1996, Antwerpen, Belgium. [8] H. Miura, S. Ikeda, and N. Suzuki. Effect of mechanical stress on reliability of gate-oxide film in MOS transistors. In Tech. Dig. IEDM, volume 96, pages 743–746, Piscataway, NJ, USA, 1996. IEEE. 116

[9] S. Jeffery, C. J. Sofield, and J. B. Pethica. The influence of mechanical stress on the dielectric breakdown field strength of thin SiO2 films. Appl. Phys. Lett., 73:172–174, 1998. [10] K. Matsukawa, Y. Kimura, H. Yamamoto, and Y. Mashiko. Study of metal impurities behavior due to difference in isolation structure on ULSI devices. In Proc. IEEE Int. Rel. Phys. Symp., volume 39, pages 299–302, New York, NY, USA, 2001. IEEE. [11] Y. Satoh, T. Shiota, and H. Furuya. Simulation of degradation of dielectric breakdown field of thermal SiO2 films due to voids in si wafers. IEEE Trans. El. Dev., 47:398–403, 2000.

117

118

Appendix A Table A.1: Diffusivity and solubility of metals in silicon [1, 2, 3, 4, 5]. Also shown are the vapour pressures [6]. Metals indicated with an asterisk ( ) were not investigated in this thesis but are included for future reference.

element

mass (a.m.u.)

est. diffusivity est. solubility vapour pressure 2 at 800 C (cm /s) at 800 C (cm3 ) at 800 C (Pa)

Ti V Cr Mn Fe Co Ni Cu Zn Y Zr Ru La Hf Ta W Pt

47.883 2.0 10 8 50.941 1.0 10 8 51.996 2.0 10 8 54.938 8.2 10 8 55.847 7.5 10 8 58.933 1.4 10 8 58.691 1.4 10 8 63.546 4.7 10 8 65.392 2.6 10 8 88.906 91.224 101.07 138.906 178.49 180.948