Germanium Channel p-MOSFET with TiO2/Al2O3 Bilayer High-k Gate Stacks and Solutions for Metal/TiO2 Interface Stability Liangliang Zhang1, Marika Gunji2, and Paul C. McIntyre2* 1
Department of Electrical Engineering, Stanford University, 2Department of Material Science and Engineering, Stanford University *email:
[email protected]
Germanium MOSFETs have been regarded as an alternative for future CMOS devices due to the high electron and hole mobilities of germanium and its compatibility for integration in Si technology [1]. TiO2/Al2O3 bilayer high-k gate stacks on Ge are promising because they provides low gate leakage current densities at small capacitance equivalent thickness (CET) due to the high k value of TiO2 , permitting a physically thicker oxide stack, while including the large bandgap and thermal stability of the Al2O3 interfacial layer. In this paper, we successfully fabricated the first Ge-pMOSFET with TiO2/Al2O3 gate stacks, and investigated two possible solutions to the observed reaction between the metal gate and the TiO2 layer during device fabrication. The TiO2/Al2O3 layers are fabricated by atomic layer deposition (ALD), which provides precise control of monolayer film thicknesses. Figure 1 shows the capacitance-voltage characteristics of the Ge MOSCAP with TiO2/Al2O3 bilayer structures on Ge(100). The samples were fabricated using a similar method to that reported in [2]. Low CET and small frequency dispersion of the capacitance are achieved with optimized process parameters. P-type germanium MOSFETs with TiO2/Al2O3 bilayer dielectric on Ge (100) substrate are demonstrated for the first time. The key fabrication processes include TMA-first Al2O3 deposition of the ALDTiO2/Al2O3 bilayer structure, Al gate formation, ion implantation and forming gas annealed (FGA) at 325 °C for S/D dopant activation and interface trap passivation. The transfer (Fig.2(a)) and output (Fig.2(b)) characteristics of the device are shown in Figure 2. A small subthreshold swing of 115 mV/dec was achieved [3], and the drain induce barrier lowing effect (DIBL) was around 23 mV/V, suggesting good gate control of the drain current. The on state current was 60 uA/um, which suggests the feasibility and potential of TiO2/Al2O3/Ge structure for high performance applications after further optimization. Figure 3 shows a cross section TEM image of Al/TiO2/Al2O3/Ge and Pt/TiO2/Al2O3/Ge samples. The Al/TiO2 interface is unusually rough (Figure 3(a)) due to the oxidation of Al by the adjacent TiO2 and the reduction of TiO2 by Al at elevated FGA temperature. The Pt/TiO2 interface observed in MOSCAP samples is much more abrupt (Figure 3(b)), but Pt etching is very difficult and lift-off of Pt can damage the TiO2 layer and reduce the yield, limiting the value of Pt as a gate metal for transistors. Two possible candidate structures are investigated to avoid metal/TiO2 reaction and to allow further increase in FGA temperature for better dopant activation. One possibility is to add an interfacial tungsten layer between Al and TiO2. Capacitance frequency dispersion is greatly reduced for Al/W/TiO2/Al2O3/Ge structure, as shown in Figures 4 and 5. Another possibility is to add a tungsten layer between Pt and TiO2. In this Pt/W/TiO2/Al2O3/p-Ge structure (Figure 6), lift-off of Pt is possible without damaging high-k gate dielectrics due to the protection provided by the interfacial tungsten. The W layer can then be wet etched after Pt lift-off. Tungsten can also cause a positive shift of the threshold voltage (Figure 7) and can tolerate a relatively high temperature for post metal FGA. References [1] K. Saraswat et al., "Ge based high performance nanoscale MOSFETs," Microelectronics Engineering, vol. 80, no. 17, pp. 15-21, June, 2005. [2] S. Swaminathan et al., “Bilayer metal oxide gate insulators for scaled Ge-channel metal-oxidesemiconductor devices”, Appl. Phys. Lett., vol.96, no. 8, 082904, 2010. [3] R. Zhang et al., “High-Mobility Ge pMOSFET With 1-nm EOT Al2O3/GeOx/Ge Gate Stack Fabricated by Plasma Post Oxidation,” IEEE Trans. Electron Dev., vol.59, issue 2, pp.335-341, 2012. 978-1-4577-1865-6/12/$26.00 ©2012 IEEE
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Id (A/um)
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Figure 1 Capacitance voltage characteristics of germanium MOSCAP with TiO2/Al2O3 bilayer on Ge(100).
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Vg= 0V
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Figure.2 The transfer (a) and output (b) characteristics of the Ge MOSFET. Al/TiO2(60cyc)/Al2O3(30cyc)/pGe
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Figure.3 The cross section TEM pictures of Al/TiO2/Al2O3/Ge (a) and Pt/TiO2/Al2O3/Ge (b) samples. Al/TiO2 interface is roughened due to reaction between Al and TiO2 at high temperature, while the Pt/TiO2 interface remains abrupt.
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Figure.5 The capacitance voltage characteristics of Al/W/TiO2/Al2O3/p-Ge samples.
decrease Tungsten thickness 3.00
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Figure.4 The capacitance voltage characteristics of Al/TiO2/Al2O3/p-Ge samples. Large frequency dispersion is observed.
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Figure.6 The capacitance voltage characteristics of Pt/W/TiO2/Al2O3/p-Ge samples. l tungsten protection layer.
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Figure.7 The capacitance voltage characteristics of Pt/W/TiO2/Al2O3/p-Ge samples with different W thickness.
