Graphene Transistors -Challenges and Opportunities

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The transfer of the graphene layer in the wafer-scale has been developed ...... combined DC source and ammeter, RC-filter with time constant of 300 ms, an ..... DOS around the Fermi energy which suppresses the current injection from metal to.
Johanna Anteroinen

Graphene Transistors -Challenges and Opportunities

School of Electrical Engineering

Thesis submitted for examination for the degree of Licentiate of Science in Technology. Espoo xx.x.2015

Thesis supervisor: Prof. Jussi Ryynänen Thesis advisor: D.Sc. (Tech.) Kari Stadius

aalto-yliopisto sähkotekniikan korkeakoulu

lisensiaatintutkimuksen tiivistelmä

Tekijä: Johanna Anteroinen Työn nimi: Grafeenitransistorit - haasteet ja mahdollisuudet Päivämäärä: xx.x.2015

Kieli: Englanti

Sivumäärä:13+91

Mikro- ja nanotekniikan laitos Professuuri: Piiritekniikka

Koodi: S-87

Valvoja: Prof. Jussi Ryynänen Ohjaaja: TkT Kari Stadius Grafeeni on hiilen kaksiulotteinen muoto. Se johtaa hyvin sekä sähköä että lämpöä. Grafeeni on äärimmäisen ohut, joustava ja hyvin vahva, minkä vuoksi grafeenista on ajateltu seuraajaa piille transistorimateriaalina. Lisäksi grafeenilla on ominaisuuksia, jotka mahdollistavat sen hyödyntämisen elektroniikassa eri tavoin kuin pii. Uuden teknologian kehittäminen ei ole koskaan helppoa, ja grafeenista on löydetty monia elektroniikan ja erityisesti transistorien kannalta hankalia ominaisuuksia. Esimerkiksi, grafeenikanavatransistorin kanavaa ei voi koskaan täysin sulkea ja lisäksi grafeeni-metallikontaktin resistanssi on korkea. Tässä työssä pyrin korostamaan grafeenin sähköisten ominaisuuksien sekä hyviä että huonoja puolia transistorisovellutuksia ajatellen. Tässä lisensiaatintyössä esitän kirjallisuustutkimuksen grafeenikanavatransistoreista, niiden karakterisoinnista ja piiritason mallinnuksesta, sekä omaa kokeellista työtäni grafeenikanavatransistorien (GFET) ja kontaktiresistanssiongelman parissa. Grafeenin sähköiset ominaisuudet käydään läpi luvussa 2. Kolmannessa luvussa erilaiset grafeenitransistorit esitellään painottuen laajan alueen grafeenitransistoreihin. Piirimallinnusta ja sähköistä karakterisointia käsitellään luvussa 4. Viidennessä luvussa käydään läpi grafeeni-metallikontaktiresistanssin ominaisuuksia.

Avainsanat: grafeeni, kanavatransistori, karakterisointi, transistorimallinnus, kontaktiresistanssi

aalto university school of electrical engineering

abstract of the licentiate’s thesis

Author: Johanna Anteroinen Title: Graphene Transistors -Challenges and Opportunities Date: xx.x.2015

Language: English

Number of pages:13+91

Department of Micro- and Nanosciences Professorship: Electronic Circuit Design

Code: S-87

Supervisor: Prof. Jussi Ryynänen Advisor: D.Sc. (Tech.) Kari Stadius Graphene is a two-dimensional form of carbon. It is a very good conductor of electrons and heat, it is thin, bendable and very strong, which are the reasons why graphene has been thought to be an excellent replacement for silicon in transistors. Furthermore, graphene has many properties which enable it to be used in ways that silicon cannot. However, bringing forth a new technology is never easy, and graphene has been found to have qualities which are problematic for transistor operation. For example, the flow of electrons in graphene cannot be completely turned off and the contact resistance between graphene and a metal is very high. I aim to highlight both the opportunities and the challenges of using graphene as a transistor material. This licentiate thesis presents a literature review on graphene transistors, their characterization and circuit modeling, as well as experimental work on graphene field-effect transistor (GFET) and graphene-metal contact resistance characterization and modeling. Graphene electrical properties are summarized in Chapter 2. In Chapter 3. different types of graphene transistors will be reviewed with focus on large-area GFETs. Circuit modeling and characterization of GFETs is reviewed in Chapter 4. In Chapter 5, the graphene-metal contact resistance is reviewed and our work is presented.

Keywords: graphene, transistor, FET, characterization, compact modeling, contact resistance

iv

Preface This licentiate thesis is based on work done at Electronic Circuit Design Unit of Aalto University during years 2011 to 2015. Projects were funded by the European Union and TEKES. What began as a promising field of research in 2010 when I was writing my master’s thesis on graphene, has gradually turned into a difficult one. The hype and initial excitement around graphene has transformed into more realistic views. On a personal level these past years have offered many opportunities to learn and develop new skills, for which I am grateful. I’d like to thank my professor Jussi Ryynänen and instructor D.Sc. Kari Stadius for the opportunity to work in this field and for the guidance. I’d like to thank our collaborators in Micronova, especially Wonjae Kim and D.Sc. Juha Riikonen. My colleagues at ECD laboratory have been most helpful whenever anything needs to be measured. Last, I would like to thank my husband Sami for discussions about modeling and validation, and for just being patient with me. Finally, I would like to quote my favorite scientist since high school; R.P. Feynman: Science is like sex: sure, it may give some practical results, but that’s not why we do it.

Otaniemi, xx.xx.2015 Johanna Anteroinen

v

Contents Abstract (in Finnish)

ii

Abstract

iii

Preface

iv

Contents

v

Symbols and Abbreviations

vii

1 Introduction

1

2 Graphene as a Material for Electronics 2.1 Energy Dispersion . . . . . . . . . . . . 2.2 Quantum Capacitance . . . . . . . . . 2.3 Mobility . . . . . . . . . . . . . . . . . 2.4 Contact Resistance . . . . . . . . . . .

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30 32 32 33 34 36 37 38 42 44 45 47 51 51 54 55

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3 Graphene Electronics 3.1 Graphene Transistors . . . . . . . . . . . . . . 3.1.1 Graphene MOSFET (GFET) . . . . . 3.1.2 GFET Characteristics . . . . . . . . . 3.1.3 Current Saturation . . . . . . . . . . . 3.1.4 Channel Length Scaling . . . . . . . . 3.2 BiSFET . . . . . . . . . . . . . . . . . . . . . 3.3 SymFET . . . . . . . . . . . . . . . . . . . . . 3.4 Graphene-base Hot Electron Transistor (GBT) 3.5 Suspended-channel GFET . . . . . . . . . . . 4 GFET Models and Simulations 4.1 Physical Models . . . . . . . . . . . . . . . 4.1.1 Ryzhii Model . . . . . . . . . . . . 4.1.2 Meric Model . . . . . . . . . . . . . 4.1.3 Thiele Model . . . . . . . . . . . . 4.2 Compact Models . . . . . . . . . . . . . . 4.2.1 Jiménez Model . . . . . . . . . . . 4.2.2 Wang Model . . . . . . . . . . . . . 4.2.3 Habibpour Model . . . . . . . . . . 4.2.4 Frégonèse Model . . . . . . . . . . 4.2.5 Rodriguez Model . . . . . . . . . . 4.3 Models Summary . . . . . . . . . . . . . . 4.4 Parameter Extraction from Measurements 4.4.1 DC-Measurements . . . . . . . . . 4.4.2 Pulsed-IV Measurements . . . . . . 4.4.3 Series Parasitic Resistance . . . . .

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vi 4.4.4 4.4.5 4.4.6 4.4.7 4.4.8

Curve-fitting . . . . . . . . . . . . . . . Access Length Method . . . . . . . . . Transfer Length Method . . . . . . . . Intrinsic Transconductance and Output Scatttering Parameter Measurements .

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56 57 59 60 61

5 Graphene-Metal Contact Resistance 65 5.1 Physics of Graphene-Metal Contact Resistance . . . . . . . . . . . . . 65 5.2 Improving Contact Resistance . . . . . . . . . . . . . . . . . . . . . . 68 References

74

Appendix A

89

vii

Symbols and Abbreviations Symbols µ

Conductivity mobility [cm2 / Vs]

µe

Electron mobility [cm2 / Vs]

µF E

Field-effect mobility [cm2 / Vs]

µh

Hole mobility [cm2 / Vs]

µef f

Effective mobility [cm2 / Vs]

α

GBT common base current gain



Spatial inhomogeneity within the graphene layer

0

Vacuum permittivity 8.854·10−12 [F/m]

ρc

Contact resistivity [Ohm]

ρ

Sheet resistivity [Ohm]

IC

Collector current [A]

IC

Emitter current [A]

β

Empirical constant

γ0

Hopping integral

~

Reduced Planck constant 1.05457·10−34 m2 kg/s

κ

Relative permittivity

k

Wave vector [1/m]



Optical phonon frequency [rad]

σres

Residual conductivity at zero charge density [S]

σ

Conductivity [S]

τ

Scattering time [s]

A

Intrinsic gain

a

Lattice constant [m]

Cq

Quantum capacitance [F]

C0

Parallel plate capacitance in NEMS [F]

viii CBG

Back gate capacitance [F]

CDS

Drain to source capacitance in small signal models [F]

CGD

Gate to drain capacitance in small signal models [F]

CGS

Gate to source capacitance in small signal models [F]

Cinv

Effective gate-to-channel capacitance per unit area in strong inversion [F/m2 ]

Cox

Oxide layer capacitance [F]

Cpd,pg

Parasitic capacitances in small signal models [F]

CT G

The top gate capacitance [F]

Ctop

The total top gate capacitance [F]

E

Electric field strength [V/m]

Ed

Energy [eV]

EF

Fermi energy [eV]

Eg

Electronic band gap [eV]

ft

Cut-off frequency [Hz]

fkα

Distribution function

fmax

Maximum oscillation frequency [Hz]

Fs

Empirical fitting function in Wang model

G0

Conductance per unit width [S/m]

Gd

Drain conductance [S]

gm

Terminal transconductance [S]

Gq

Conductance quantum 7.748 ·10−5 [S]

gdi

Intrinsic output conductance [S]

gds

Output transconductance [S]

gmi

Intrinsic transconductance [S]

IDLIN

Drain current in linear region [A]

IDSAT

Drain current in saturation [A]

ix ID

Drain current [A]

Imin

Minimum current in the channel that cannot be modulated [A]

In,p

Electron/hole current [A]

kB

Boltzmann constant 1.3806503 ·10−23 m2 kg s−2 K−1

L

Transistor length [m]

LA

Access length [m]

LG

Gate length [m]

LT

Transfer length [m]

Lef f

Effective gate length [m]

Lmf p

Mean free path length [m]

Ln,p

The length of the electron or hole channel [m]

m

fitting parameter

m∗

Effective mass [kg]

n, p

Charge density/doping concentration [cm−2 ]

n0

Residual carrier concentration at Dirac point [cm− 2]

NA , ND

Local charge density [cm−2 ]

nimp

Impurity charge concentration [cm−2 ]

npuddle

The residual carrier concentration induced by spatial inhomogeneity in graphene [cm− 2]

Nsq

Number of squares

ntot

Total charge carrier density [cm−2 ]

q

Elementary charge, 1.602·10−19 [C]

Qn (0)

The inversion charge at the top of the barrier [C]

Qch

Channel charge density [C/m2 ]

Qmin

Minimum charge in the channel that cannot be modulated [C]

Qnet

Bias dependent mobile carrier charge [C/m2 ]

x Qsh

Carrier sheet charge density [C/m2 ]

Qtot

Total gate charge [C]

QV ES,e

Electron charge at the virtual source [C]

QV HS,h

Hole charge at the virtual source [C]

R0

fitting parameter

RA

Access region resistance [Ohm]

Rchannel

Channel resistance [Ohm]

Rc

Contact resistance [Ohm]

Rexto

Extra resistance in the channel due to electrons as majority carriers [Ohm]

Rext

Function describing the carrier dependence of S- and Dresistances

RG

Gate metal resistance [Ohm]

Rintrinsic

Intrinsic resistance [Ohms]

Rsh

Sheet resistance [Ohm]

RS

Series parasitic resistance. S stands for source and D for drain [Ohm]

Rtotal

Total resistance [Ohm]

imp Scol

0

Collision matrix for ionized impurities

imp Scol

Collision matrix for impurities

T

Temperature [K]

tox

Oxide layer thickness [m]

V (x)

Channel voltage at point x [V]

V0

Modified Dirac point voltage [V]

v0

Carrier velocity at virtual source [m/s]

V2

fitting parameter

Va

Local electrostatic potential [V]

vF

Fermi velocity, 1/300 of the speed of light [m/s]

xi VG

Gate voltage [V]

VT

Thermal voltage [V]

VBG

Back-gate voltage [V]

VCH

Voltage over the graphene channel [V]

VDP,BG

Dirac point with respect to the back-gate voltage [V]

VDP,top

Dirac point with respect to the top-gate voltage [V]

VDP

The voltage at which the GFET is at Dirac point [V]

vdrif t

Drift velocity [m/s]

VDSAT

Drain voltage in saturation [A]

VDS

Drain to source voltage [V]

Vef f

Effective gate voltage [V]

VGD,top

Top gate to drain voltage [V]

VGS,BG

Voltage applied to back gate [V]

VGS,top

Voltage applied to top gate [V]

VGS

Gate to source voltage [V]

Vmax

Maximum condensate voltage [V]

Vn/p

Control voltage over n- or p-layers [V]

Vnd,pd

Voltage drop over the electron or hole part of the channel [V]

vsat

Saturation velocity [m/s]

Vt,e,h

Effective threshold voltage for electrons or holes [V]

vV ES,e

Electron velocity at virtual source [m/s]

vV HS,h

Hole velocity at virtual source [m/s]

W

Transistor width [m]

Abbreviations

AC

Alternating current

xii Al2 O3

Aluminum oxide

ALD

Atomic layer deposition

ANN

Artificial neural network

BCI

Base-collector insulator

BiSFET

Bilayer pseudospin field-effect transistor

BLG

Bilayer graphene

BSIM3/4

Berkeley MOSFET SPICE models

CMOS

Complementary-metal-oxide semiconductor

CNP

Charge neutrality point, ie. the Dirac point

CO2

Carbon dioxide

CPU

Central processing unit

CVD

Chemical vapor deposition

DC

Direct current

DIDS

Drain induced Dirac shift

DOS

Density of states

DP

Dirac point

EBI

Emitter-base insulator

EBL

Electron beam lithography

ELDO

A commercial electronic circuit simulator

EOT

Effective oxide thickness

FD-SOI

Fully-depleted silicon-on-insulator

FinFET

Fin field-effect transistor

FLG

Few layer graphene

GBT

Graphene-base transistor

GFET

Graphene field-effect transistor

GNR

Graphene nanoribbon

hBN

Hexagonal boron nitride

xiii HfO2

Hafnium dioxide

IC

Integrated circuit

IGFET

Insulated gate field-effect transistor

IIP3

Third order intercept point

IV

Current-voltage

LA

Longitudinal acoustic (phonon)

LCAO

Linear combination of atomic orbitals

LNA

Low noise amplifier

LO

Longitudinal optical (phonon)

MoS2

Molybdenum disulfide

NEGF

Non-equilibrium Greens function

NEMS

Nanoelectromechanical system

PMMA

polymethy methacrylate

RF

Radio frequency

ROP

Remote oxide phonon

SCE

Short channel effect

Si-MOSFET

Silicon metal-oxide-semiconductor field-effect transistor

SiC

Silicon carbide

SiO2

Silicon dioxide

SLG

Single layer graphene

SO

Surface optical (phonon)

SPICE

Simulation Program with Integrated Circuit Emphasis, a circuit simulator

SymFET

Symmetric tunneling field-effect transistor

TBA

Tight-binding approximation

TCAD

Technology computer aided design

TLM

Transfer length method

UTB

Ultra thin body

VS

Virtual source

1

Introduction

Graphene is a form of carbon organized in a chicken-wire structure. Each corner of a hexagon holds one carbon atom. Unlike everyday materials around us which take up space in all three dimensions, graphene is inherently two dimensional. Graphene holds a multitude of beneficial material properties due to its planar structure. Many of these properties are especially interesting for electronics applications. Graphene has the potential to enable thin, lightweight and flexible electronics. In some application areas, graphene may bring new functionality or improve performance. As an example of improved performance, graphene may be used as a electronics display electrode and touch sensor simultaneously. An example of new functionality could be that adding a layer of graphene to a touch screen display could enable humidity sensing or detection of gas molecules, such as CO2 . In addition to the material properties, graphene is found in abundance, as is silicon. Graphene is a relatively new material find. Theoretically graphene was discovered late in the 1940s, but it was first intentionally isolated in 2004 [1]. The discovery of the first two-dimensional crystal in the world has led to a massive research effort into graphene. Moreover, the discovery of two-dimensional crystals has spurred a whole new research field in material science and graphene was quickly followed by two-dimensional crystals MoS2 and silicene. In fact, the field-effect in graphene was demonstrated already in 2004, and graphene field-effect transistors quickly became an active research topic. In the span of roughly ten years, graphene transistors have moved on from a single transistor to a fully functional graphene-based integrated circuit [2]. Despite the fast progress in graphene transistors, there are several unsolved problems related to graphene electronics. Figure 1 illustrates the fast pace at which graphene related research is published. The trend in graphene publications is exponential. Graphene has been researched as a material for analogue electronics at Aalto University Electronic Circuit Design group (ECD). The research interest at ECD has been in graphene for radio frequency (RF) applications. Graphene offers higher speed and new functionality at the gigahertz range. More specifically the research has focused on graphene field-effect transistors (GFET) and graphene resonators. Thus, the focus of my licentiate thesis is on graphene electronics and more specifically GFETs; the operation, modeling and characterization. I also want to convey the challenges of graphene as an electronics material, as well as the many opportunities. This licentiate thesis is based on my work at Aalto University Electric Circuit Design research group during three projects between 2011 and 2014: Nanoradio, Rodin and Moca. During the research projects, I have presented these results in the conferences listed below. My work during the research projects has focused on three aspects: how to measure graphene nanodevices, analyze the data and model the nanodevices. The main focus in my work has been on graphene based transistors and to a lesser extent graphene resonators. My thesis has two main topics, a literature review on graphene transistors and my own experimental work on graphene transistor characterization and modeling. The thesis is divided into chapters, starting with a short introduction

2 [3]

J. Anteroinen, W. Kim, K. Stadius, J. Riikonen, H. Lipsanen, and J. Ryynänen, “Electrical properties of CVD-graphene FETs,” in 29th Norchip Conference, Lund, Sweden, November 2011.

[4]

J. Anteroinen, W. Kim, K. Stadius, J. Riikonen, H. Lipsanen, and J. Ryynänen, “Graphene for gigahertz applications,” in Swedish Radio and Microwave Days, Solna, Sweden, March 2012.

[5]

J. Anteroinen, W. Kim, K. Stadius, J. Riikonen, H. Lipsanen, and J. Ryynänen, “Extraction of graphene-titanium contact resistances using transfer length measurement and a curve-fit method,” in World Academy of Science, Engineering and Technology, no. 68, pp. 1604-1607, Paris, France, August 2012.

[6]

J. Anteroinen, W. Kim, K. Stadius, and J. Ryynänen, “Towards highfrequency graphene electronics,” in XXXIII Finnish URSI Convention on Radio Science and SMARAD Seminar 2013, Espoo, Finland, April 24-25, 2013. pp. 169-172, Espoo, Finland, April 2013.

into the topic. Chapter 2 introduces graphene as a material for electronics. I will shortly describe the most important physical properties of graphene from the point of view of electronics. Chapter 3 is a literature review on graphene transistors with the focus on graphene field-effect transistors. Graphene transistor modeling approaches and measurement practices are reviewed in Chapter 4, where I have chosen models for large-area graphene transistors. Our work on graphene-metal contact resistance is covered in Chapter 5. I will summarize my thesis in Conclusions.

Figure 1: Number of graphene related publications in Scopus retrieved on 15.10.2014.

3

2

Graphene as a Material for Electronics

Graphene is a two-dimensional allotrope of carbon. Graphene can be viewed as the basis of other carbon allotropes; rolled graphene becomes carbon nanotube, tens of stacked graphene layers make graphite and balled up graphene creates fullerene. Graphene has existed in the purely theoretical form since roughly 1940s [7], and graphene is often the material on which aspiring material scientists perform their first tight-binding calculations. The fuss around graphene began around 2004 when scientists realized that graphene can exist outside textbooks [1]. Graphene was discovered by peeling small flakes of graphene from a block of highly-ordered graphite with a scotch-tape. The flakes were transferred to a standard silicon wafer simply by pressing. The graphene flakes are invisible to the naked eye, but on top of a silicon substrate with a 90 nm or 300 nm silicon dioxide layer, the graphene flakes become visible via interference effect. Graphene is a material with extraordinary properties which make it suitable for many applications. From electronics viewpoint the relevant material properties are heat conductivity and electronic transport. The heat conductivity of graphene is roughly 30 times better than thermal conductivity of silicon, around 5 ·103 W/mK in room temperature [8]. Thermal conductivity is very important for electronic applications. Graphene is also extremely strong and optically nearly transparent. Graphene mechanical properties are also unique, the breaking strength of graphene is many times higher than that of steel and the elastic properties are comparable to diamond [9]. The optical absorption of a single layer of graphene is relatively high, 2.3% corresponding to the fine structure constant [10]. Graphene exhibits a wide range of exotic physical phenomena, such as Klein tunneling [11] and Veselago lensing [12]. Very clean graphene samples exhibit Shubnikov-de Haas oscillations [13], minimum conductivity [14] and fractional quantum Hall-effect [15]. Despite the great material properties, graphene has no electronic band gap. For many electronics applications a band gap is essential to reach low power consumption. The terminology in the field of graphene nanoelectronics has not taken root yet and the nomenclature in the articles tend to vary. In this document I strive to follow the terminology suggested in [16]. Thus, graphene will refer to a single atomic layer and distinction will be made between 2-5 layers of graphene. The reason for the distinction is simple; the material properties change with the number of graphene layers. To illustrate this, a layer of graphene does not have an energy gap, but two layers of graphene, i.e. bilayer graphene, has a small but significant energy gap of the order of 300 meV when a electric-field is applied perpendicular to the bilayer [17] [18]. This chapter will briefly discuss concepts that are important for understanding graphene as an electronics material. First, the energy dispersion and density of states of graphene is reviewed, then topics related to electronic transport are discussed, i.e. quantum capacitance, mobility and contact resistance.

4

2.1

Energy Dispersion

Graphene is electrically extremely interesting with exciting properties arising out of its 2D nature. Graphene is composed of carbon atoms bonded covalently in the shape of a hexagon. Since graphene is a two-dimensional system, the electronic band structure can be calculated analytically using the tight-binding approximation (TBA) or the closely related linear combination of atomic orbitals method (LCAO). The band structure of graphene is given as q √ (1) Ed (k) = ±γ0 1 + 4 cos( 3kx a) cos(ky a) + 4 cos2 (ky a/2) where γ0 is the nearest neighbor hopping integral and a is the lattice constant. Equation (1) can be further simplified to a linear relation Ed (k) = ±~vF |k − K|. The linearization of (1) holds well for most graphene devices. The band structure of graphene is plotted in Fig. 2 with Eq. (1). The Ed − k dispersion is clearly linear near the K-K’ points where the valence and conductance bands meet. These points where the bands touch are referred to as Dirac points, because in this vicinity electrons behave as Dirac fermions. The effictive mass for graphene is defined as m∗ = ~2 k/(dEd (k)/dk)

(2)

The effective mass for graphene is isotropic, equal for electrons and holes, and proportional to the square root of charge density. Graphene has fourfold degeneracy, two for spin and two for valley, thus giving the density of states (DOS) as √ 2 πn 2Ed (3) DOS = 2 2 = πvF ~ π~vF The band structure of graphene provides many interesting physical phenomenon. Graphene has been found to exhibit such phenomena as half-integer quantum Halleffect [19], Klein tunneling [11], Hofstadter’s butterfly [20], and may enable Veselago lensing [12]. Furthermore, graphene has two equivalent A and B sublattices which gives rise to an additional quantum number; the pseudo-spin. The pseudo-spin conservation forbids complete backscattering which increases the mobility by roughly a factor of two [21]. Graphene is a versatile material that can be used for many applications, not only transistors. Graphene can be used as electrode material as a replacement for indium tin oxide [22], or as a sensor since the electrical characteristics are easily changed by the environment [23] or as a material for several optoelectronic applications [24].

2.2

Quantum Capacitance

State-of-the-art GFETs are dominated by quantum capacitance Cq rather than electrostatic oxide capacitance. All two- or one-dimensional transistors appear to have an additional capacitance in series with the typical electrostatic gate-oxide capacitance. This capacitance is called quantum capacitance Cq . Where does this additional capacitance arise from? Quantum capacitance is not a capacitance in the

5

Figure 2: Energy band structure of graphene according to tight-binding approximation. physical sense; it does not arise from electrostatics in the same sense as a plate capacitance, rather Cq appears in series with the typical electrostatic capacitance. Quantum capacitance is important in systems where the DOS is low, which generally means any 2D system. In a grounded metal plate, the electric field from quasi-static charges is completely shielded from entering the other side of the plate. In a low DOS system the electric field can partially penetrate the plate. The phenomenon is described with the concept of quantum capacitance [25]. A good account of quantum capacitance is also given in reference [26]. Generally, it can be shown that Cq ≡ δVδnch where n is the charge density and Va is the local electrostatic potential [27]. The quantum capacitance is derived from the density of states (DOS) of graphene assuming the Fermi-Dirac distribution for charge carriers [28]. Quantum capacitance is calculated for graphene in reference [29] as    2q 2 kB T qVCH Cq = ln 2 1 + cosh (4) π(~vF )2 kB T where kB is the Boltzmann constant, ~ the Planck constant and Vch is the voltage over the graphene channel. Equation (4) can be simplified to √ 2q 2 n 2 2qVch √ = q 2 DOS = (5) Cq ≈ q π(~vF )2 ~vF π when qVCH >> kB T . The quantum capacitance of graphene is approximately linearly dependent on the channel voltage and has a minimum value around the minimum conductance point [29]. Since Cq of graphene is linear with respect to the applied top gate voltage, it could be used in sensor applications. The challenge is in measuring the very small changes in the quantum capacitance. The quantum capacitance of the graphene

6 channel has to be taken into account when the gate dielectric thickness is reduced Cq is dominated by whichever capacitance because the series combination Ctot = CCoxox+C q is smaller. Thus, finding a suitable high-κ dielectric for the gate oxide is imperative as mere thinning of the gate oxide is not enough [30].

2.3

Mobility

Charge carrier mobility is a common performance metric for transistors. High mobility is desirable for a transistor because high mobility means high currents to charge the capacitances and thus higher frequency response. Graphene carrier mobility exceeds 10 000 cm2 /Vs [31] which is at least ten times better than for silicon. The GFET mobility is limited by scattering from impurities, surface/interface roughness and phonons [32]. According to Matthiessen’s rule 1/µ = 1 µ1 + 1/µ2 + ... the net mobility is dominated by the lowest mobility. Matthiessen’s rule assumes that the scattering processes have the same dependence on energy, which for most cases is true. For GFETs, the surface optical phonons and Coulomb scattering from oxide charges have been found to be the significant scattering processes [33]. The optical phonon energies in graphene at room temperature are larger than 150 meV, and are insignificant to mobility [21]. The longitudinal acoustic (LA) phonons interact with electrons leading to momentum loss and increased resistance. The LA phonons contribution to resistance is linear with respect to temperature and sets the practical upper limit for mobility in 300K as 2 ·105 cm2 /Vs [21]. In practice the LA phonons are shadowed by the remote oxide phonon (ROP) scattering processes which depend on the substrate and gate dielectric choices, since both surfaces contribute to ROP scattering. In general, low-κ dielectrics have less ROP scattering. The choice of substrate and dielectric materials for graphene transistors need to be carefully considered for optimal transistor operation. However, even if phonon scattering could be eliminated there are still other extrinsic scattering sources, such as oxide charges (impurities), interface roughness and lattice defects. There are many ways to define and measure mobility. In this text, the most common mobilities which are measured for a GFET are introduced. A careful reader may notice the absence of Hall-mobility. Hall-mobility is neglected here because it requires a Hall-bar structure and separate test-equipment to measure. In this text, the focus is on mobilities which can be extracted based on the typical DC IV-measurements of a transistor. The generic carrier mobility (often called conductivity mobility or intrinsic mobility) is given by Eq. (6) which can be manipulated for a GFET as follows [34] µ = σ/nq σ = Nsq /(Rtotal − RS ) n = κ0 (VG − VDP )/tox q Nsq tox ⇒µ= Rintrinsic (VG − VDP )κ0

(6) (7) (8) (9)

where Nsq = L/W of the transistor, Rtotal is the total resistance of the transistor and RS is the sum of parasitic series resistances which is subtracted from the total

7

Figure 3: Different mobilities as a function of carrier density for a GFET with 0.5 µm length and 25 µm width. Mobility is plotted only for holes at low VDS = 100 mV. resistance. The charge carrier density n is determined by the gate capacitance and is corrected for the parasitic charges which shift the Dirac voltage. If the contact resistance is taken into account when extracting the generic carrier mobility value, the model is sometimes called constant mobility model [35]. Effective mobility is defined as µef f = gds Nsq /Cox VG

(10)

where gds is the transistor output conductance. The field-effect mobility is defined as µF E = gm LG /W Cox VDS

(11)

where gm is the transistor transconductance, LG the gate length and VDS the applied bias. The transconductance and output conductance are given by Eq. (27) and (28), respectively. The three different mobilities are not equal for any transistor. GFET intrinsic mobility is the one most often given in research articles because it is almost always the highest value for GFETs. It can be argued that intrinsic mobility does not accurately describe the characteristic of the transistor. However, intrinsic mobility has been found to be a good indicator of the quality of the graphene itself. Figure 3 shows the three mobilities that I measured and extracted for a embedded local bottom gate GFET with L=0.5 µm and W=25 µm. The GFET was fabricated by W. Kim at Micronova cleanroom. The field-effect mobility for this transistor is very

8 poor, which is due to very small transconductance of this GFET. The effective mobility is a bit higher, but the intrinsic mobility is the highest, as would be expected. Generally, for any MOSFET, effective mobility is higher than field-effect mobility. The reason is that the electric field depence of µef f is neglected in the derivation of µF E [36]. Mobility ceases to be a good transistor performance metric when the charge transport becomes ballistic. In a ballistic transistor, the charge carriers zoom through the channel with no scattering, thus mobility is no longer a valid performance metric. In fact, the rapid reduction of mobility as the gate length is reduced is a sign of a ballistic channel [37]. Graphene transistors with extremely pure and very short (< 100nm) graphene channel exhibit ballistic transport at room temperature [38].

2.4

Contact Resistance

Graphene-metal contact resistance Rc has proven to be the biggest performance killer in graphene applications so far. Contact resistance is the resistance between the source/drain metal and the graphene channel. The specific contact resistance is denoted here with Rc and the total series parasitic resistance of a GFET is denoted with RS or RD . The total series parasitic resistance is the sum of Rc and the resistance of the ungated channel. The excellent intrinsic properties of graphene transistors are masked by the contact resistance. Especially for short channel GFETs, the contact resistance is detrimental since Rc does not scale down with length, thus the total GFET resistance is dominated by Rc [39]. Contact resistance has a huge impact on the transistor performance merits, such as the cut-off frequency, extrinsic transconductance, maximum frequency of oscillation and the ID -VG linearity and limit on the on-current. Contact resistance is defined as the sum of the resistances of the physical metal interconnects and the metal-graphene interface (interfacial resistivity). The specific contact resistivity is a combination of several phenomena, such as interfacial resistivity, and it cannot be predicted from theory. Theory is able to predict interfacial resistivity, which unfortunately cannot be measured directly [36]. Graphene-metal contact resistance is a burning issue for GFET development. Table 1 summarizes contact resistances from literature. It is obvious from Table 1 that the variance between results is great. The variance is mainly caused by two things; the fabrication process differences and different measurement methods. Rc problem is of high priority for many graphene applications, not only for GFETs, thus Chapter 5 is devoted to the topic.

9

Table 1: Collected contact resistivity values (T = 300 K). Metal/Graphene ρc Reference Ni 500 Ω µm [40] Ti > 1000 Ω µm [40] Ti/Pt/Au stack 100 Ω µm [41] Cr/Pd/Au stack (1D edge contact) 100 Ω µm [42] Cu (Cuts patterned) 125 Ω µm [43] Pd (Cuts patterned) 457 Ω µm [43] Pd 185-900 Ω µm (BG bias dependent) [44]

10

3

Graphene Electronics

Electronics is an integral part of modern everyday life. Personal computers, mobile phones and even cars and coffee machines are packed full of electronics and more specifically, integrated circuits (IC). In many ways, the most important element on an IC is the transistor, the general handy-man of electronics. Among the many tasks of transistors, the main use of transistors is to either act as a switch or amplify signals. Currently, the most common transistors are silicon based MOSFETs, and more specifically complementary metal-oxide-semiconductor (CMOS) technology in which a n- and p-type transistor are connected together to form an inverter. The CMOS technology has evolved to a stage where developments tend to be incremental rather than game-changing, and performance improvements come at great financial cost. For the past decade, the death of Si-MOSFET has always been five years away. Yet, always a new fabrication technology or a slight improvement is found that extends the life of the Si-MOSFET [45]. Technological feats to develop the MOSFET include strain engineering to improve mobility and continued channel length scaling to fit ever more transistors on a chip, to name a few. To illustrate the difficulty of continued scaling of the MOSFET, a growing issue currently for CMOS is the heat dissipation, but the problem has been solved by turning down the clock frequency which reduces the heating. Clever microprocessor architectures have been invented to compensate for the loss of computing speed with several parallel CPUs which consume less power thus generating less heat. These solutions, however, will not carry the CMOS much further in to the future. New solutions which extend the life of the MOSFET have been developed in the meanwhile, namely fully depleted silicon-on-insulator MOSFETs (FD-SOI) and FinFET [46] [47]. The scaling of FinFETs and FDSOI FETs is nowhere near their limits, but critics are already estimating that the continued performance improvements will come to a gradual end in the following decades [46]. It is clear that new materials and even completely different transistors are needed in the future if the semiconductor industry wants to keep growing its revenue. Furthermore, many other industries rely on the continuous improvement of integrated circuits. The future transistor scenarios are referred to as ’More-Moore’, ’More-thanMoore’ and ’Beyond-CMOS’ in the International Technology Roadmap for Semiconductors [48]. The first scenario requires little explaining; business as usual with continued scaling of CMOS. More-than-Moore scenario means that value is added to devices with new functionality, but the scaling law is broken. Last, but not least, beyond-CMOS is an umbrella term referring to new materials and device concepts. Graphene transistors are a prime example of beyond-CMOS devices. Ever since graphene was intentionally fabricated for the first time in 2004 [1], graphene has been touted as the new silicon. The frenzy that took over the transistor research after the field effect was demonstrated in graphene does have a deep motivation; the scaling limit of silicon MOSFET is nearing its end. The electronic transport properties of graphene have made some declare graphene prematurely as the next silicon and savior of Moore’s law. Electrons (and holes) move decades faster in graphene than silicon, yet graphene has no energy gap. These

11 two properties are linked, if one induces an energy gap in graphene, some of the speed is lost. Therefore, the solution is either to compromise some of the speed or make do without an energy gap. As with many engineering problems, there is not just one answer; analog electronics may not require as stringent power handling as digital electronics. Currently graphene-based RF transistors are pushing closer to state-of-the-art in semiconductor RF transistors. The development of the GFET has been fruitful, though possible roadblocks have appeared in the horizon. In 2004 graphene was first made by peeling graphite with scotch-tape, and few years later it became possible to synthesize graphene in wafer-scale. The transfer of the graphene layer in the wafer-scale has been developed and suitable materials for metal and dielectrics have been found. In the span of ten years, the GFET has gone from a single transistor in the lab to an integrated circuit [49]. Despite the progress in graphene transistors, there are still many issues that need to be solved before graphene FET has commercial potential. The greatest challenges in graphene electronics are • fabricating defect and impurity free graphene in large scale • transferring the perfect layer of graphene on top of a desired substrate • depositing dielectric material on a layer of graphene without destroying the performance • band gap to turn the channel off • current saturation is required for good analog performance • graphene-metal contact resistance. The first issue has been solved at least partly, CVD- and SiC-graphene show excellent electron transport properties, although the best performance is still achieved with individual mechanically exfoliated graphene flakes [50]. New physics can be probed with graphene flakes, but exfoliated graphene will never be used in commercial products. Even if perfect, defect-free large area single layer graphene could be fabricated, the layer must be transferred on top of a substrate (except SiC-graphene where SiC acts as the substrate). Current methods involve a spin-on dielectric, such as PMMA, deposited on graphene to support the layer while the growth substrate metal is etched away [22]. The transfer method leaves resist residues on graphene and the layer may bend or fold in the process. Dielectric deposition on top of graphene has proven to be problematic as well. First, any dielectric in close proximity to graphene will change the electronic properties. Second, most common methods of dielectric deposition usually harm graphene. Finally, the graphene-metal contact resistance has proven to be difficult to engineer. The contact-resistance is absolutely detrimental to all graphene electronics applications, and special attention to this topic has been paid in this thesis.

12

3.1

Graphene Transistors

Graphene transistor research has trod the familiar paths of silicon and III-V semiconductors. The first graphene device to exhibit the field-effect was published by two different groups within a few months of each other, de Heer’s group [13] and Geim’s group [1]. The latter group received the Nobel physics prize in 2010 for their discoveries. The first graphene transistor was a marriage of convenience; the easiest way to fabricate such a device was to transfer a flake of mechanically exfoliated graphene on top of a highly doped silicon wafer with SiO2 acting as gate oxide and deposit metal contacts to the flake of graphene. Nowadays, the fabrication of graphene has been developed to reach wafer-scale with both chemical vapor deposition (CVD) [22] and epitaxial SiC-graphene [13]. While most research groups have focused on trying to replace the silicon channel with graphene and designing graphene field-effect transistors, some groups have come up with different ideas for transistors. Graphene transistors named BiSFET (bilayer pseudospin field-effect transistor) [51], SymFET (symmetric tunneling fieldeffect transistor) [52] and GBT (graphene base hot-electron transistor) have been proposed in literature [53]. The following sections will describe different types of graphene transistors. Some transistor types, such as BiSFET and SymFET, are purely theoretical and have not been experimentally demonstrated due to stringent requirements for device fabrication. Graphene field-effect transistors and graphene-base transistors have been simulated and experimentally demonstrated by many groups. The focus in the following sections is mostly on GFETs and GBTs while the more exotic transistors are quickly reviewed for generality. 3.1.1

Graphene MOSFET (GFET)

Graphene field-effect transistor (GFET) was the first demonstrated graphene electronic device [1]. The extremely high mobilities of the first device inspired researchers to further develop and hone GFET technology. GFET is basically the same structure as a typical MOSFET. The difference is that instead of silicon the channel is made of graphene. A photograph of a chip with several CVD grown GFETs is shown in Fig. 4. The chip was fabricated in Micronova by W. Kim. The graphene channel can be either a single graphene layer (SLG), bilayer graphene (BLG), few layer graphene (FLG) or even graphene nanoribbon (GNR). The characteristics of the GFET differ greatly with different graphene channel. SLG and FLG are semi-metals and have no band gap, though BLG and GNR have a small yet usable band gap. The number of graphene layers can be deduced from Raman spectroscopy [54]. The study of graphene with Raman spectroscopy has become something of an art in itself. For example, the purity of graphene can be deduced from the relative heights and locations of the Raman peaks [54]. An example of a Raman measurement that I made of a CVD-grown graphene sample is shown in Fig. 5. The transport properties of graphene are affected by graphene quality, interfaces of the oxide and substrate and the metal contacts [55]. Graphene has a large sur-

13

Figure 4: CVD graphene FETs fabricated at Micronova by W. Kim.

Figure 5: Raman spectra of CVD grown graphene. The location and relative heights of the peaks suggest a dirty sample. face area which makes it susceptible to ambient environment. Sensor applications make use of the many ways that the surrounding environment affects the electrical properties of graphene, e.g. graphene can be used simultaneously as touch sensor and humidity sensor [56]. Graphene quality is determined by the fabrication process and technological advances will improve graphene quality in the coming decades. The ambipolar field effect can be explained by a 2D metal with a small overlap between valence and conductance bands [1]. The ambipolarity of graphene makes it possible to operate a graphene transistor with either electrons, holes or both simultaneously. Graphene bandstructure allows the conduction to shift from electrons to holes by changing the Fermi level. Graphene differs from semiconductors because as semimetal graphene does not require impurity doping to conduct electricity. Graphene field-effect is often referred to as self-doping in which the electric field effect allows the charge carrier type and concentration to be controlled with an external electric field. A graphene field-effect transistor is constructed from substrate, graphene layer as the channel, dielectric layer and source-drain electrodes and top/back gate electrode. Figure 6 shows an example of a two gate-finger structure that is preferred for

14 RF measurements due to the symmetry of the device which minimizes the effects of fringing fields. GFETs commonly have both a top- and a global bottom gate. Having two gates allows control over the graphene under the source and drain contacts [57]. The global back gate is used to dope the graphene under the contacts which significantly decreases the overall series parasitic resistance. This improves the operation of the GFET since the source- and drain-series resistances will be minimized. Many of the early GFETs had only a global back gate because it was much simpler to fabricate. The source and drain series resistances have proven to be the greatest obstacle in GFET technology [55] [40] [42]. The series resistance can be minimized by reducing the contact resistance and by using a self-aligned gate structure in which there is practically no ungated channel. The larger issue for GFET operation is the contact resistance. Although, it is possible to have an ohmic contact between a metal and graphene [40], in practice p-n/n-p-junctions often form between contact and graphene channel [58]. The perceived asymmetry between hole and electron transport may be due to the contacts changing from p-p-p junction to p-n-p under gate modulation. Typical metals used for contacts are Ti, Pd, and Ni, Pt [59]. A general guideline for choosing contact metals is to ensure that the contact is ohmic, and secondly to choose such a metal that its work function is as close to the semiconductor band gap as possible, though Fermi-level pinning should be avoided. Contacts can be deposited with e.g. electron beam lithography (EBL) [36]. A recent study by Liu et al. [60] shows that contact resistance is affected by the processes used in fabrication. For example, sputtering leads to larger contact resistance than electron beam. The higher contact resistance caused by sputtering is possibly due to carbon vacancies in the graphene lattice. The choice of the substrate and gate dielectric is as important as the metals. As for any MOSFET, the gate dielectric should be as thin and uniform as possible with a high dielectric constant, i.e. high-κ. The gate oxide and the substrate should be chosen such that the interaction with graphene is minimized because graphene transport properties are easily changed by the surrounding environment. In principle, the substrate can be chosen almost arbitrarily; graphene can be transferred on top of any material. Although, graphene can be transferred on top of any substrate, the electrical transport will be greatly affected by the substrate. Unlike mechanically exfoliated graphene or CVD graphene, epitaxial SiC-graphene grown on SiC cannot be transferred at all. Graphene is hydrophobic and chemically inert which makes atomic layer deposition (ALD) very difficult. High-κ dielectric deposition with ALD is not straightforward; alumininum or other seed material is deposited on top of graphene first to create nucleation centers [22]. However, ALD deposition damages the pristine graphene surface. HfO2 and Al2 O3 are commonly used as gate dielectrics, but the research focus is turning towards other 2D materials with hexagonal lattice structure, such as, hexagonal boron nitride hBN [61] [34] [62].

15 Gate Source

Gr

Insulator Drain

SiO2

Gate Gr

Source

Si Figure 6: A double-gate two gate-finger GFET. 3.1.2

GFET Characteristics

This chapter will discuss the characteristics of GFETs, especially regarding the different operation regions and the ambipolarity arising from the electronic band structure of graphene. The GFET operation regions can be explained through the quasi-Fermi level positions in the channel. Typical GFETs have four terminals that are used to bias the device. A doublegate two gate-finger GFET is shown in Fig. 6. GFETs based on CVD graphene are often built on highly doped bulk silicon wafers which have SiO2 layer on top. The highly doped silicon is then used as global back-gate. Top-gate controls the carrier concentration in the channel. Generally, a positive top-gate voltage changes the ambipolar channel to n-type and negative top-gate voltage to p-type channel. This is a simplification because the charge neutrality point, Dirac point, is not always at zero top-gate voltage, but may change with process variation. The back-gate is used to dope the graphene under the metal contacts and the ungated graphene. Back-gating offers an additional degree of freedom in controlling the bias point of the GFET, although the back-gate is an optional feature. GFETs have an unusual property called charge neutrality point, often referred to as Dirac point or minimum conductance point, which is characteristic to graphene. Charge neutrality point is akin to the threshold voltage of MOSFETs with the difference that in graphene the conduction never quite turns off. The sheet resistivity of graphene was found to have a peak of a few kOhms and decays to some hundreds of Ohms with changing the gate voltage [1]. Graphene resistivity ρ can be described by the classical equation ρ−1 = σ = nqµ (12) where n is the doping concentration, σ conductivity and µ the mobility of graphene. Equation (12) applies quite well for large-area graphene and non-ballistic samples at low electric fields. The resistivity peak is located approximately at zero gate voltage in pure graphene, and the closer to zero the Dirac point is, the better the sample of graphene. The minimum conductivity in graphene is a multiple of the conductance quantum Gq = 2q/~ [63]. The exact value of the minimum conductance in graphene is difficult to probe because it requires extremely pristine graphene sample with very little perturbations from the surrounding environment [63]. The minimum conductivity point in graphene is affected by many factors, short-range disorder, ripples in graphene and the presence of charged impurities [64] [33].

16 The Dirac point location is affected by many things, such as the difference between the work functions of the gate and the graphene, doping (electrical or chemical), and type and density of charges at the interfaces at the top and bottom of the channel. The Dirac point changes with adsorbed water or other ambient adsorbing molecules [65]. Crystal lattice deformations may change the Dirac point, although crystal defects cause only small shifts in the charge neutrality point with respect to applied gate voltage [66]. Intentionally caused lattice defects were found to significantly reduce the minimum conductivity as well as mobility via scattering by midgap states [66]. Charged impurities have been found to have significant role in graphene conductivity. Charged impurity scattering predicts the conductivity as [64]: σn = Cq|

n nimp

| + σres

(13)

where C is a constant and σres is the residual conductivity at zero charge density. In a sample with low charged impurity concentration, the conductivity with respect to gate voltage is sublinear, whereas for high charged impurity concentration the dependence is linear and Eq. (13) describes the conductivity well. Also, the more impurities in graphene, the more the charge neutrality point is located to either left or right of zero gate voltage, i.e the DP location of a ’cleaner’ graphene sample. The direction of the DP shift to left or right depends on what type of impurities are present, e.g. K-doping shifts the DP to the left [64]. The charge neutrality point is also affected by short-channel effects [67]. The drain potential influences the channel potential, and the gate control is weak in short devices. Thus, the gate needs to apply more opposite voltage to reach the minimum current point. Figure 7 shows an example of a measured gate- voltage drain-current curve for a CVD-graphene FET fabricated at Micronova by W. Kim which I measured. This particular transistor has the Dirac point quite close zero gate bias, which indicates low unintentional doping. The transport curve in Fig. 7 is asymmetric, resulting in different mobility for electrons and holes [68]. The charge neutrality point can be manipulated in a GFET with two gates, a back gate and a top gate [69]. Interestingly, the graphene under the contacts can be doped by the back gate resulting in a shift of the location and magnitude of the current at DP [69]. Although, the shift with back-gating is small, it gives hope for aggressive channel length scaling in GFETs for gating can extend beyond the channel region [69]. Unlike Si-MOSFETs, GFETs can change by applied top-gate voltage from unipolar n-type channel to p-type. Under certain conditions, the channel can also be ambipolar with both electrons and holes contributing to the current. The conduction of electrons (holes) in the graphene channel can be explained with quasi-Fermi levels and the concept of Dirac point. The three conduction regions are portrayed in Fig. 8. We assume that VDS is positive in all conduction regions. When the gate bias is high, the quasi-Fermi level is above the Dirac point in the channel, and the conduction is by electrons injected from the source (region 1). The situation is reversed for holes (region 3); when the gate bias is low, the quasi-Fermi level is below the Dirac

17

Figure 7: A W/L = 50/1 µm GFET drain current as a function of gate voltage. point. The channel becomes ambipolar (region 2) with electrons injected from the source and holes from the drain recombining in pairs in the channel, when the gate bias is such that the channel shifts from region 1 to 3. GFETs have four distinct operation regions [72] 1. Linear region 2. Quasi-saturation region 3. Negative-differential resistance region 4. Second linear region The operation regions are depicted in Fig. 9 denoted with Case 1. If CT G >> CBG , the effective gate voltage on the channel is [73] Vef f = Qtot /Ctot ≈ VGS,top + VGS,BG ·

CBG CT G

(14)

When VGS,BG is the same polarity as VGS,top the channel-contact junction changes to unipolar and thus reduces the series parasitic resistance [74]. According to [73], higher metal work function of the S/D-contacts favors p-conduction, which results in asymmetry between electron and hole conduction. In this situation a negative VGS,BG increases hole doping in the graphene under the metal contact reducing the contact resistance. In electron dominated transport, the contact resistance is determined by pn-junction at the interface. With short channel GFETs the impact of the contact resistance is expected to be more pronounced as the contact resistance does not scale down with channel length scaling.

18 1 Gate Source

Drain

Gr

2 Gate Source

Drain

Gr

VDS >0 3 Gate Source

Gr

Drain

Figure 8: Quasi-Fermi level in graphene for different top-gate bias. Figure drawn after [70] and [71]. GFETs widely exhibit meager intrinsic gains, which is defined as A = gm /gds . There are several reasons for the low gain, but one of the obvious ones is biasing. Proper biasing of GFETs is especially important for graphene RF devices. The effect of bias conditions for a GFET with a structure as in Fig. 6 was studied in [73]. The intrinsic gain was found to improve by 3-4 times as compared to a GFET with no back-gate bias [73]. Furthermore, the cut-off frequency and maximum frequency of oscillation are also vastly improved by proper bias. The improvement in intrinsic gain and cut-off frequency is due to two main factors, the reduction in output conductance gds and the series parasitic resistance RS (RD ). These two effects will be discussed in detail. Minimizing the series para-

19

Case 2 4. ID

2.

3.

Case 1

1.

VD Figure 9: Operation regions of a GFET. Case 1 assumes no full current saturation while case 2 supports the hypothesis of a full current saturation. The x- and y-axis scales are arbitrary. sitic resistance is in principle straightforward; the metal-graphene contact resistance needs to be minimized. As discussed in Ch. 2.4 and 5, Rc has proven to be difficult to engineer. Achieving high intrinsic gains requires gds to be minimized as well. Output conductance is defined as the derivative of the drain current with respect to the derivative of the source-drain voltage. Thus, the question of minimizing output conductance is reduced to achieving current saturation in GFETs. 3.1.3

Current Saturation

The saturation of the drain current is important for analog amplifiers which operate at the saturation region of a transistor. When a transistor is in saturation, it is said to operate as an ideal current source, i.e. the output current is constant for a large range of voltages. Without current saturation, a GFET is only a voltage controlled resistor with limited use for any electronic applications. Graphene channel has no ’pinch-off’ effect in the same way as a semiconducting channel does. As a result, the scientific community is debating if graphene would show current saturation at all. Most researchers claim that current saturation exists, but is influenced by charge trapping effects and dielectric material [70] [75]. GFETs often show quasi-saturation, i.e. not full saturation, which is reported to be caused

20

Figure 10: DIDS in a top-gated GFET with L=1 µm and W=50 µm. Drain voltage ranges from 0.5 V (lowest curve) to 2 V (highest curve). by the quasi-Fermi level crossing the Dirac point in the channel. It has also been suggested that contacts may cause saturation-like behaviour in GFETs [76]. Two types of current saturation have been reported for GFETs in the literature: optical phonon limited velocity saturation [70] and drain induced dirac shift (DIDS) which is also referred to as carrier density gradient [77]. Figure 10 shows an example of DIDS in a long channel GFET. The GFET was fabricated by W. Kim and measured by me with a semiconductor parameter analyzer. The DIDS is somewhat weak in Fig. 10, considering that the drain voltage in the highest trace is 2 V. Current saturation in GFETs was first reported in [70] in which the current saturation was attributed to carrier density gradient and not phonon scattering. Figure 9 shows an imaginary example the two cases of current saturation. The curve denoted with Case 2, shows the phonon scattering induced current saturation where the current saturation is full and the output conductance has a minimum over a large range of bias voltages. Case 1 shows the ’pseudo-saturation’ which is attributed to the DIDS or carrier density gradient in the channel. In this case, the drain current increases linearly (1.) first and reaches a partial saturation (2.). In the third region, the current may show a ’kink’ or even give negative differential resistance [72]. Finally (4.) the drain current continues to increase. An example of this ’pseudo-saturation’ is shown in Fig. 11. The GFET in this figure is the same as in Fig. 10. The current slightly saturates when the DP enters the channel. The question is whether Case 1 type of saturation is enough for real transistor applications. The problem in partial current saturation is that the range of bias points where the current is saturated, is rather small which leaves a small window for electronics design. Moreover, there is still some controversy around current

21

Figure 11: Carrier density gradient induced current saturation effect in a top-gated GFET with L=1 µm and W=50 µm. saturation in graphene transistors regarding phonon limited velocity saturation. The debate around current saturation in GFETs has its roots in the semimetallic nature of graphene itself; can a metallic transistor show current saturation and what would be the mechanisms leading to this phenomenon? The jury is still out for deciding on this question at the time of writing this thesis. The dilemma is that only few groups have reported current saturation in experiments suggesting that the theory may be incomplete. Also, the mechanism causing current saturation is not always clear. For example, few of the articles in which current saturation is achieved are in room temperature [78, 75, 79, 77], and in many cases current saturation is found only in low temperature [70], [31]. Submicrometer GFETs with extremely thin dielectric, effective oxide thickness (EOT) of 1.75 nm, have shown clear current saturation as well as high DC gain (34), 11dB voltage gain and even power gain [75]. The improved electrostatic control is attributed as the main reason for current saturation [75]. Surface potential based model simulations show that thin EOT improves the transistor operation by reducing the impact of thermally excited carriers, by accelerating the carrier depletion due to strong quantum capacitance limit and by reducing the influence of interface trapped charges [75]. In the low source-drain bias, the carrier transport of GFETs follows the Drude model. In principle, saturated carrier velocity is reached when electron (hole) drift velocity is large enough to promote inelastic collisions with phonons. Current saturation in the high-field limit can be described with the Boltzmann equation when all scattering processes are taken into account [31] −qE · ∇fkα imp imp0 LA LO SO = Scol + Scol + Scol + Scol + Scol ~

(15)

22 where the distribution function fkα is time independent and spatially uniform. Equation (15) has been found to describe the velocity saturation in graphene quite well [31]. The collision matrix Scol considers longitudinal acoustic (LA) and longitudinal optical (L0) phonons of graphene. The surface optical (SO) phonon of the substrate as well as the charged and neutral impurities are also added to Scol . Scattering from the substrate and other dielectric surface optical phonons dominates the high-field transport and heat dissipation [31]. Over 95% of the power dissipation in the highfield occurs directly through SO phonons [31] and the high saturation velocities are in turn due to the efficient energy dissipation which drops the electron temperatures. Furthermore, the carrier drift velocity is well predicted by a simple model that only includes the instantaneous emission of optical phonon. To promote current saturation, several steps can be taken; less charged impurities and purer samples yield current saturation at lower electric fields [80] [31]. Also, the importance of the SO phonon raises the question of substrate material choice. Recently, different substrates have been demonstrated for GFETs, such as hexagonal boron nitride (hBN) [34] and diamond-like carbon [81] [82]. Contrary to the experiments and modelling in [31], [80] claims that full current saturation is not achievable in graphene and that incorporating SO phonons to the Boltzmann transport makes the agreement between experiment and theory worse. Extrinsic factors such as the contact resistance and impurities may play a big role in masking the intrinsic properties of the transistor. The reasons for not detecting any current saturation in a GFET can be due to the joint effect of at least the following: 1. Poor quality of graphene, i.e. bad sample 2. Non-optimal device structure 3. High contact resistance 4. Too thick gate oxide, poor gate control of the channel 5. Non-optimal bias, i.e. no separate back-gate and top-gate 6. Trapped charges at substrate and oxide interface Especially trapped charges have been proven to be a problem for the accurate measurement of the intrinsic transistor properties [83] [84]. GFETs suffer from fabrication process related issues with trapped charges in the high-κ oxide. The trapped charge issue was the same in early high-κ oxides in MOSFETs. The effect of the trapped charges on characterization can be mitigated by the use of a pulsed IV-measurement, which is a standard semiconductor characterization method. Although, the use of a nanosecond pulse-IV measurement solves the issue from characterization point of view, the process issues need to be solved for actual electronic applications to eventually emerge.

23 3.1.4

Channel Length Scaling

State-of-the-art GFETs are still rather large compared to Si-MOSFETs, yet the trend has been to scale the GFET channel length down to achieve best performance [85, 2]. Downscaling the channel mostly affects the transconductance, gm by increasing it. Another way to achieve higher transconductance is to improve the gate control over the channel, which usually means thinning the gate oxide. Since gate oxide deposition in general has been problematic in GFETs, the straightforward way to improve gm is to shorten the transistor. Improving gm is important for all electronics applications, but especially for analogue circuits where a higher cut-off frequency is desirable. Cut-off frequency, fT , is defined as the frequency at which the current gain becomes unity. Transistor cut-off frequency is directly proportional to gm according to equation fT = gm /(2πCG ) where CG is the gate capacitance. GFETs follow the same scaling trend as MOSFETs; the intrinsic current gain decreases with increasing frequency as 1/f [85]. Furthermore, GFET fT is strongly dependent on bias conditions with a relatively narrow peak with respect to gate voltage. GFETs were found to follow a scaling rule f ∝ 1/L2G [85]. In theory, shortening LG should increase fT , but in practice the short channel effects come into play. GFETs are not immune to the hazards of miniaturization. Short-channel effect (SCE) is an umbrella term for several phenomena which occur in a transistor when the channel length is down scaled. The effects are brought along by the drain and source coming closer together thus strengthening the electric field along the vertical axis. SCE will become an important research issue with miniaturized GFETs. Very little experimental data is available for SCE in GFETs [86]. SCE in short-channel ballistic GFETs has been studied via non-equilibrium Greens function (NEGF) simulations in [87] [88]. The simulated effects of SCE are shift of the Dirac point and current-voltage oscillations. Ab initio quantum simulations show that the intrinsic voltage gain and the intrinsic fT are improved by scaling the GFET below 10 nm [89]. The improvement is caused by band gap opening in graphene and enhanced current saturation. The ideal band gap for a low noise amplifier (LNA) is extensively analyzed in [90] and the compromise value is found to be around 100 meV. Miniaturizing GFETs have other negative effects related to the short channel. Although the performance of the intrinsic transistor may be improved with a short channel, some effects such as the contact resistance, do not scale with channel length. Furthermore, channel length scaling for GFETs does not improve the overall device performance unless the contact resistance is minimized. The smallest realized gate lengths for GFETs are in the sub-100 nm range with the impressive performance of cut-off frequency of 150 GHz with 40 nm GFET, although the maximum frequency of oscillation is only in the range of tens of GHz [81]. The use of self-aligned nanowire gate has resulted in a 140 nm GFET with 300 GHz cut-off frequency [91]. Ab-initio simulations show that GFETs with sub-10 nm gate lengths may reach cut-off frequency in the few THz [89]. Power gains reaching 20 dB at 1 GHz have been demonstrated with epitaxial SiC-graphene transistors

24 Vg,p

Vp Insulator Insulator

Gr Gr

Insulator Vn,p

Vn

Figure 12: Schematic of a BiSFET or a SymFET after [51]. [50]. GFETs have also been demonstrated with flexible substrates with performance that surpasses the competing organic FETs [92]. The state-of-the-art has gone from single transistors to full graphene-based integrated circuits. The first GFET based IC was a broadband radio frequency mixer at 10 GHz [2]. A more recent graphene IC demonstrate an RF receiver at 4.3 GHz carrier frequency with three cascaded GFETs [49].

3.2

BiSFET

Although large area GFETs have been most thoroughly investigated by means of theory and experiment, several more exotic transistors have been proposed. Exotic in this context simply refers to the operation principle of the transistors, which is not necessarily based on the field-effect. BiSFET is short for bilayer pseudospin field-effect transistor. A graphene based BiSFET was first suggested in [51]. BiSFET is a completely different type of transistor that is based on two semiconducting layers in close proximity. The operation principle of a BiSFET differs from a MOSFET and BiSFETs could be used to create logic gates with very small power consumption. Simulations in [51] show that the average energy consumed per clock cycle for a BiSFET inverter is only 0.008 aJ at 100 GHz, whereas current CMOS consumes an average of 100 aJ per switching at 5 GHz. Naturally, simulations that do not take into account the huge parasitic contact resistance or other effects may be quite off the target. The structure of the BiSFET is in principle simple; two layers of graphene separated by a very thin dielectric that acts as a tunnel barrier. BiSFET structure is shown in Fig. 12. The top layer is n-type and bottom p-type (or vice versa) with equal charge carrier concentrations. The n- or p-doping can be achieved e.g. with gates to both layers. The idea is to form a electron-hole-pair condensate to achieve a controllable tunneling resistance [51] [93]. The equivalent circuit model of BiSFET is shown in Fig. 13. The I-V characteristics of the BiSFET are qualitatively explained as  I≈

G0 (Vp − Vn ) ±G0 Vmax exp(1 − |Vp − Vn |/Vmax )

if − Vmax < Vn − Vp < Vmax everywhere else

where G0 is the conductance per unit width, Vmax is the maximum voltage at which the condensate is formed and Vn and Vp are the biases that control the interlayer voltage, and thus the tunneling current.

25 Cg,p

Cq

Vp

Vg,p Cil

I(Vp , Vn ,Vg,p , Vg,n )

Vg,n Cg,n

Cq

Vn

Figure 13: Equivalent circuit model of a BiSFET after [51]. The stringent requirements for the dimensions of the transistor and interface quality are the downside of this design. Furthermore, it is the reason why BiSFET is currently a theoretical concept. The need for high quality dielectric with EOT 1 nm is quite strict. Additionally, the quality of the graphene layer itself must be excellent. The question arises, is a BiSFET even viable if an extremely thin dielectric is placed between the two layers. It is a well-known fact that graphene electrical properties are easily changed by the surrounding environment, in this case the dielectric. The feasibility of the BiSFET remains to be assessed when fabrication technology is advanced enough to produce these devices.

3.3

SymFET

SymFET stands for symmetric tunneling field-effect transistor. SymFET was first proposed in [52]. SymFET schematic looks exactly like a BiSFET. In fact, SymFET was developed after the proposal for the BiSFET, but the physical operation principle is somewhat different. The schematic for a SymFET is shown in Fig. 12. SymFET operation relies on a tunneling current from n-type graphene to p-type graphene that is controlled with chemical doping and applied bias [52]. Unlike the BiSFET, SymFET does not rely on many-body excitonic condensate to induce a controllable tunneling current. In a SymFET the Dirac points of the n- and p-type graphene layers align at a certain interlayer voltage which allows a large interlayer tunneling current to flow. This is expected to happen because the energy and momentum are conserved for all electron energies between the quasi-Fermi levels of the two layers. The resulting IV-trace of a SymFET is a lorentzian peak, i.e. the SymFET IV-characteristics are very nonlinear. The nonlinearity is expected to increase as the rotational symmetry between the graphene layers is increased. There is currently no mass production technology capable of controlling the rotational symmetry of graphene layers [52]. From a circuit design point of view, an inverter where the on-off states are relatively sharp peaks, does not sound very appealing. Process variation may cause the on-off states to be misinterpreted and the circuit would require some method of compensation for possible process variations. The nonlinear I-V curve of the SymFET could be used in other ways; the SymFET has been suggested to be used as frequency multiplier [52]. The SymFET is predicted to be very fast, but no sim-

26 ulations of the speed is available at the time of writing this thesis. The SymFET operation should withstand temperature variation unlike the BiSFET which operates at a certain temperature. However, the tunneling current through a SymFET depends on the thickness of the dielectric layers unlike the tunneling current through the BiSFET. The practical issues for SymFETs are much the same as for BiSFETs. The need for extremely thin and high quality dielectrics, high quality graphene and low contact resistance are the reasons why neither transistor has actually been fabricated.

3.4

Graphene-base Hot Electron Transistor (GBT)

The disappointment in the development of GFET has motivated the invention of several different graphene transistor schemes. The most promising transistor that uses graphene is currently graphene-base hot electron transistor (GBT). GBT was suggested in [53] and MoS2 base hot-electron transistor in [94]. A similar structure was demonstrated in [95] with the exception that instead of just one graphene layer acting as base, the structure has two sandwiched graphene layers. The operation principle is nonetheless similar in both [53] and [95], i.e. barrier controlled tunneling. The GBT is shown in Fig. 14. The GBT is similar in structure to hot-electron transistor or a triode. The GBT has an emitter, emitter-base insulator (EBI), base, base-collector insulator (BCI) and collector. The direction of the current is vertical, from emitter to the collector, differing from the lateral current transport in GFETs. GBTs are barrier controlled devices, but the purpose of the graphene layer is different in GBTs than in GFETs. Although, graphene does not have a bandgap in the lateral direction, it does have a gap in the ’vertical’ direction [53]. Graphene can be used as the control electrode. The GBT has two states, on and off. The transistor is on when hot carriers from the emitter tunnel via Fowler-Nordheim tunneling through the EBI-base-BCI to the collector. Fowler-Nordheim tunneling, i.e. field emission, is a quantum mechanical process in which charge carriers tunnel through a barrier in the presence of a high electric field [96]. In the off-state carriers do not have enough energy to tunnel through the barriers. The carrier transport through the graphene base can be ballistic offering a very high fT , possibly even in the THz-range. The on-off ratio of a GBT was 105 in a GBT demonstration, although the ratio can be potentially even higher [97]. Graphene is used as the base material because it is just a single layer of atoms with high conductivity unlike with bulk metals which become very resistive when thinned to few atomic layers [98]. The base thickness is related to the transit time and high gain [97]. To reach terahertz cut-off frequency, GBT structure needs to be optimized carefully, e.g. in [53] the simulations show that the EBI needs to be 3-5nm thick and energy barrier less than 0.4 eV. Further speculation about the optimized structure is pointless, as the models used in [53] and [98] are too simple to make accurate predictions. The common-base current gain α is defined as α = IC /IE

(16)

27

Emitter Base

EBI Graphene

Base

BCI

Si

Collector

Figure 14: Schematic of a graphene-base transistor [97]. The current gain describes the fraction of charge carriers injected from the emitter that reach the collector after scattering and reflections in the base or the insulator interfaces [97]. Experimental GBTs have shown α-values in the range of 0.03-6.5% [97][99]. The demonstrated α-values are quite moderate, but optimizing the GBT structure may yield much higher current gains. In fact, early hot-electron transistors had similar current gain ratios as GBTs [100] and more recent ’beyond-Moore’ transistors have current gain in the same range [101]. The quality, thickness and material parameters of the tunneling barriers are key to improving α. Additionally, optimizing the geometry of the vertical structure will improve α [97]. The advantage of GBT is the high on-off ratio, speed and possibility of current saturation [53]. However, only the high on-off ratio and current saturation has been experimentally demonstrated [99] [97]. Superficially, GBT seems like a good way to make use of graphene properties, but the question arises why there have been so few publications on GBTs. No RF measurements or simple circuits have been demonstrated yet. The issue is likely to be found in device fabrication. The GBT as a structure is more complicated than a GFET with two dielectric layers which require precise thickness control.

3.5

Suspended-channel GFET

A graphene-field effect transistor can be structured so that graphene is suspended between two metal contacts, namely source and drain. The metal gate in this structure is below the suspended graphene channel. A suspendend channel GFET is depicted in Fig. 15. At first glance this GFET seems silly from the electrostatic point of view since air is not a good dielectric and would yield very poor control over the channel. The advantage of this suspended-channel GFET is that in vacuum conditions the device acts as a nanoelectromechanical system (NEMS) [102, 103, 104, 105, 106]. Graphene-NEMS holds much promise for resonator applications such as such as electrical filters [107]. Filters in mobile applications are often the largest component on the chip. Also, each mobile communication band requires their own filter because

28 Graphene Drain

Source Gate Substrate

Figure 15: Graphene FET-NEMS hybrid. the filter operation frequency is not tunable. Mobile communication standards are moving towards higher frequencies, where the traditional surface acoustic wave and bulk acoustic wave filters are no longer viable options. Graphene-NEMS based filters would potentially have frequency range in the GHz-range and tunable frequency range with high quality factor (over 10 000). Moreover, graphene is extremely thin which allows for much smaller resonators and thus filters. The gate in such a device has two purposes, electrostatic actuation and charge carrier doping. In principle, it is possible to achieve current gain and induce a motional current at the same time. The device acts then as a NEMS resonator with current amplification properties. An equivalent circuit for a graphene NEMS-FET is shown in Fig. 16. The transconductance gds is a function of the gate voltage and the motional current induced by the motion of the suspended channel. The capacitances C0 are the parallel plate capacitors of the channel-air-gate structure. Several such suspended GFETs were fabricated by collaborators in Aalto, ICN Barcelona and TU Delft and measured at our laboratory. The measurement of a graphene NEMS is described in [108], and is a standard procedure for MEMSresonators. Unfortunately, the high performance expectations of a suspended channel GFET/NEMS hybrid could not be met with the current technology. The stateof-the art resonance frequency for graphene NEMS resonator is still in the range of 100 MHz [107] [108] [106]. The device fabrication and especially the control over the mechanical properties, i.e. initial tension and Young’s modulus, turned out to be extremely difficult. Furthermore, measuring the suspended GFETs in industrial grade vacuum (10−4 mmbar) did not give meaningful results. The reason for the poor success is manifold. First, the air dampening in industrial grade vacuum was too high for the nanosize NEMS resonator. Secondly, the parasitics of the measurement environment may have completely masked the weak signal from the NEMS even though calibration was performed. Thirdly, the contact resistance between the source/drain contacts and graphene was found to be very high, between hundreds of kOhms to megaOhms, making the impedance level of the NEMS high as well as dominating the current transport in the channel. Towards the end of the project, weak resonances were detected in Aalto Low Temperature Laboratory in cryonic temperatures and very high vacuum. In the real world this type of hybrid transistor-NEMS technology is not feasible.

29

G

C0 /2

RD

D GDS (VDS -VG )

Cpg C0 /2

GDS

S

Cpd

RS

Figure 16: Equivalent circuit of a suspended-channel GFET after [109]. To be able to literally take the device out of the laboratory environment, the hermetic packaging technology would need to be able to reach those extreme vacuum levels and device processing would need to have the ability to control the mechanical properties of the structure, which is currently not possible. Yet, the greatest hiccup may still be the large contact resistances resulting in high insertion loss for filter applications. A single layer of graphene alone may not be ideal for a mechanical resonator, but graphene has been successfully demonstrated as a conductive coating for silicon nitride based resonators with the resonance frequency a meager few MHz, but with quality factor exceeding 105 [110].

30

Figure 17: A chart of transistor model types.

4

GFET Models and Simulations

Integrated circuit (IC) design is not possible without computer simulations. A modern IC contains millions of transistors. The operation of an IC is described by a number of device models and equations which describe the connections between elements. Each device model consists of a large number of equations describing the operation in each bias point. A circuit simulator solves the resulting large number of equations in thousands of operation points, which makes simulations both time and resource consuming. In order to design ICs simple yet accurate models are needed. GFETs are often evaluated only as a single transistor which may mislead in interpreting how GFETs will work in actual circuits. To evaluate GFET behavior on a system level, accurate models for DC, AC and transient operation are needed. Transistor electrical models can be divided roughly into three groups; physics based models, empirical models and table models [111]. The first model group is used for transistor and process development. A physical transistor model can be either analytical with closed form expressions or numerical. The latter model type is usually computationally heavy and includes a detailed 3D description of the transistor. A 3D model of a MOSFET will solve the Poisson equation coupled with drift-diffusion equations. Additionally this group would also hold non-equilibrium Green’s function method (NEGF) and other quantum mechanical models used for ballistic transistors. 3D technology computer aided design (TCAD) models are accurate, but complex and require the user to be well acquainted, if not an expert in the field, to use them. Although the results of a 3D TCAD model are accurate, the interpretation may be difficult and rule-of-thumb calculations are not possible. A 3D TCAD model is best suited for fabrication process optimization and the development of new device structures. A physical transistor model is desirable because it has

31 true predictive power, e.g. if the transistor structure is changed in any way, a physical model can predict the performance outcome. The development of a physical transistor model is slow which is a disadvantage in the fast paced electronics industry. Empirical models in all simplicity are based on curve-fitting. Generally, empirical models are only as good as the measurement data. If the data that the model is based on, does not represent the device accurately enough, the model is of little use to a circuit designer. Most of the model parameters in empirical models have no physical meaning, thus the model cannot be applied for process or new device development. Modern empirical model may include artificial neural networks (ANN) combined with X-parameter measurements thus providing a quick and comprehensive modeling tool [112]. ANNs are in simple terms univariate nonlinear processing elements joined by weighted sums. ANNs are smooth nonlinear functions which weights can be trained against robust measurement data. Table model, like the name suggests, consists of a set of tables of the drain current vs. the bias voltage. Table models have limited predictive power. Nonetheless, table models are useful in situations where no good physical model is available. Like empirical models, table models are only as accurate as the measurement data that the model is based on. A table model can also be based on values from a numerical 3D TCAD model. Table and empirical models are quick to develop in contrast with physical models [111]. Regardless of the model type, circuit design requires simple non-recursive, yet accurate models. The requirements of simplicity and accuracy are contradicting, since accuracy is often achieved with added complexity. The circuit level model should not only incorporate an IV-model, but also accurately model the charges (or rather, capacitances) under large- and small-signal conditions. The model should also be valid over a wide range of frequencies. This kind of a model is referred to as compact model. Compact models may be either physical, empirical or even table models. Often, a compact model is semi-empirical or may use tables in certain operation regions. The goal of a compact model is to provide a tool for (analog) electronic circuit design. A compact model should have an analytic closed-form expression for the transistor drain current. The small-signal model parameters can then be determined by differentiating the drain current. The drain current should preferably be at least twice differentiable because RF noise and linearity performance metrics, such as, third order intercept points (IIP3) require a continuous second derivative. Furthermore, circuit simulators, such as ELDO, do not allow recursive mathematics, which places a restriction on compact models [111]. Many physics based models of GFETs have been published and even more atomistic, or quantum mechanical near equilibrium Green’s function (NEGF) models. While these models offer often quite accurate description of the device behavior, they are not suitable for circuit design. One should bear in mind while evaluating the different models that the complexity of the model is no guarantee of accuracy. Furthermore, no model is accurate under all operating conditions, and the designer needs to choose the right model for the task at hand. However, a well-behaving model should warn the user when it is

32 used outside of model range. In the following sections, two GFET model groups are reviewed; physical and compact models. Table and empirical model are neglected here because such models are not widely used or published for graphene transistors. Few physics based models that will not be reviewed here, that should still be mentioned are Scott charge based model [113], Champlain hybrid-π small-signal model [114] [115], Han surface potential based model for submicron GFETs [75], Hu quasi-ballistic transport model [116], Zebrev semi-classical drift-diffusion based small-signal model [117], Holland self-consistent quantum mechanical model [118] and Umoh compact model [119]. I will also discuss various methods of GFET measurements and parameter extraction towards the end of this chapter. Accurate and reliable parameter extraction from measurements is the first building block of any model.

4.1

Physical Models

Simple physics based transistor models typically emerge first, as such models strive to qualitatively explain the operation of a device, while model accuracy can be improved with time or by implementing the model as a 3D TCAD. Physics based models come in many forms, they may be simple or extremely complex. Although analytic closed-form solutions are preferred, often these models require numerical solutions or self-consistent iterative solutions. Physics based models offer insight to the operation of a device and are often the basis on which compact models are built. The first GFET models strove to qualitatively describe the operation of the transistor. The very first GFET model was published by the Nobelists Geim and Novoselov in 2004 [1]. Their focus was not on modeling, but the in the demonstration of the existence of two dimensional crystals, and furthermore, a field-effect device made of a metal! Nonetheless, [1] describes the charge density and resistivity of a GFET with a standard Drude model and is the first step towards GFET modeling. The next logical step was to fabricate more GFETs and try the drift-diffusion model for GFETs, since the devices operate far from the ballistic limit. The early GFETs were in the tens of micrometers in width and length, which makes operation in the ballistic region impossible. The amount of published work on graphene field-effect devices after the initial paper in 2004 [1] has grown almost exponentially. I have chosen to summarize the most influential published papers on large-area GFET physical modeling for the following sections. Some of the equations in the articles is omitted for the sake of brevity. 4.1.1

Ryzhii Model

One of the first physics based model was published by Ryzhii et al. model [120]. The model provides qualitative understanding of thermionic and tunneling transport in GFETs. According to Ryzhii et al. GFETs are barrier controlled devices in much the same way as silicon or III-V semiconductor devices. GFETs have a top-gate which controls the channel current through a barrier under the top-gate. The region under the gate is either n- or p-doped depending on the sign of the voltage, while the

33 access region is vice versa, e.g. n (access)-p(under gate)-n(access). The current is associated with the electrons (holes) that hop over the barrier (thermionic emission) and the ones that experience inter-band tunneling at the n-p or p-n junctions. Ryzhii et al. article is concentrated on GNR FETs even though the same rules apply for large area GFETs. Ryzhii et al. model is computationally heavy and hard to implement due to the large number of equations. The model is not validated against experimental data. 4.1.2

Meric Model

Long-channel large area GFETs, i.e. Lg >Lmf p , channel current can be most conveniently modelled with drift-diffusion model. Early models are based on the driftdiffusion equation. One of the first drift-diffusion models for GFETs was presented by Meric et al. [70],[61], [83]. Current saturation in GFETs was first reported by [70], where the current saturation was found to be caused by velocity saturation via optical phonons in the substrate interface. The velocity saturation was found to be dependent on sheet charge-carrier concentration. Meric el al. [70] were the first to describe the kink-effect in the GFET IV-trace. The kink is caused by the Dirac point entering the channel at which point the channel shifts from being unipolar to ambipolar. The recombination of holes and electrons in the ambipolar regime creates a pinch-off in the channel because no energy is released by the process. Meric et al. [70] model the carrier concentration n(x) in the channel as a function of channel potential V (x) q (17) n(x) = n20 + (Ctop (VGS,top − V (x) − V0 )/q)2 where V0 = VDP,top +

CBG (VDP,BG − VGS,BG ) Ctop

(18)

where n0 is the minimum carrier concentration, Ctop , CBG is the top/back-gate capacitance, VDP,top , VDP,BG are the Dirac points with respect to the top- and the back-gate. The location of the kink, i.e. the pinch-off region is approximately located at V ds ≈ VGS,top − V0 . The top-gate capacitance Ctop is the series combination of the oxide capacitance and the quantum capacitance Cq that arises from the DOS of graphene. Cq Cox Ctop = Cq + Cox p where Cq = n/π · q 2 /vF ~

(19) (20)

where Cox is the geometrical oxide capacitance and vF is the Fermi velocity of graphene. Cq is a function of the carrier concentration, but often an average value for Cq can be assumed without much loss in accuracy. The channel current can then be expressed by a well-known equation for drift-

34 current W ID = L

ZL qn(x)vdrif t (x)dx where

(21)

µF E E 1 + µF E E/vsat

(22)

0

vdrif t (x) =

where vsat is the saturation velocity of charge carriers, E is the electric field, and µ is the low-field field-effect mobility. The model assumes that the saturation velocity vsat is expressed as vsat = vF (~Ω/EF ) where ~Ω is the optical phonon energy. The drift velocity model was changed in [83] to Thornber’s equation. vdrif t (x) =

 1 β 1 β −1/β + µE vsat

(23)

where β is an empirical factor (typical value for GFETs is 2), and µ in this case is the zero-field mobility. 4.1.3

Thiele Model

Another early transistor model for GFETs is by Thiele et al. [28]. Thiele et al. model was published two years after Meric et al. and aims to describe both IV- and smallsignal characteristics of GFETs. This model describes the channel current using the same drift-diffusion model as Meric et al., though the derivation in this paper is more rigorous, the interested reader is encouraged to go through the derivation [28]. Thiele et al. model aims to qualitatively describe GFET behavior through a quasianalytical approach. The density of states and quantum capacitance is modeled analytically, but the main contribution is the addition of a soft saturation behavior and charge model of the channel. The drain current model is the in principle the same as Eq. (21). The main difference to Meric et al. model [70] is in modeling the velocity saturation. Thiele et al. model vsat by adding an empirical correction to the formula: vsat =

Ω (πnsh

)0.5+AV 2 (x)

(24)

where A is an empirical factor of the order of 10−3 . The carrier concentration in the channel is calculated from the net channel charge density Qsh which is given by Z 1 Qsh = − Cq dVCH = − Cq VCH (25) 2 from which follows 1 qnsh = Qsh = | − Cq VCH | (26) 2 The Vch as a function of the local potential in the channel V (x) can be solved using circuit laws from Fig. 18.

35

CBG

Cox,top Cq Cq Vch (x)

Vch (x)

VGS,top

VGS,BG V(x)

Figure 18: Metal-insulator-graphene circuit according [28]. The small-signal model uses the typical hybrid-pi model for GFETs. The capacitances CGS and CGD are as shown in Fig. 32. The transistor small-signal parameters are defined as for any MOSFET with the following formulae dId gm = (27) dVGS,top VDS =const. dId (28) gds = dVDS VGS,top =const. dQch (29) CGS = − dVGS,top VDS =const. dQch CGD = − (30) dVDS VGS,top =const. The net channel charge Qch is given as ZL [NA − ND ]dx

Qch = qW

0 VDS Z

(NA − ND )

= qW



(31) qnsh µW µ + ID vsat

 dV

(32)

0

where NA and ND are the local hole and electron sheet densities. Following from the small-signal model, the transistor cut-off frequency can be calculated as gm fT = (33) 2π ((CGS + CGD )[1 + gds (RS + RD )] + CGD gm (RS + RD )) The cut-off frequency is considerably lowered by RS and RD which are affected by the graphene-metal contact resistance. Besides gm , the transistor drain conductance gds has a (negative) impact on the cut-off frequency. The drain conductance for GFETs is typically quite large.

36

4.2

Compact Models

Compact modeling can be quite challenging due to the conflicting goals of model accuracy and simplicity. Compact model development is always on-going as SiMOSFETs are aggressively scaled down to nanometer dimensions and new phenomena must be added to the existing models to reach high enough model accuracy [121]. Si-MOSFETs have been successfully described by models, such as the BSIM (Berkeley Short-channel IGFET model), BSIM3 and BSIM4, for the past 20 years. As the MOSFET technology has advanced to multi-gate and UTB transistors, the compact models have been modified to describe the operation [121]. The progress in MOSFET compact modeling can directly benefit GFET compact model development. The practice is evident in the models that are presented in this section, after all, there is no point in reinventing the wheel again. Compact models can be divided into three categories [111]: physical models, empirical models and table models. Physical models are the most common type of a compact model and the most useful compact model type. Empirical models are also common, but are only as good as the measurement data, since modeling is based on sophisticated curve-fitting. Table models are useful only when no physical model is available, e.g. when the device is under development. Table models have no prediction capability outside of the range of parameter space of the measured device. The different bias points are interpolated, and extrapolation can be used for prediction, although the results are likely not accurate. The benefit of a tablebased model is that it is quick to develop, whereas physics-based or empirical model would take more time. Physics based compact models can be complicated; a good MOSFET model may have over 40 parameters for all different operating regions [111]. Physics based compact models are able to predict the device behavior even when some of the device parameters change, whereas table or empirical models cannot. Regardless of the model category, a compact model aims towards simple equations to reduce computation time. Thus the use of transcendental equations and functions, such as the exponential or logarithm, should be avoided [121]. Besides avoiding computationally heavy functions, compact models should have parameters which link to actual physical phenomenon and have predictive power. Moreover, a complete compact model should describe the IV-characteristics, large-signal and small-signal with an adequate level of accuracy. In this section, only large-area gapless graphene models are presented. All models use the gradual channel approximation and thus are not applicable to very short channels, with the exception of the MIT virtual-source model for GFETs. GFET ambipolar conduction is something of an issue in most models, and the effect is widely ignored. Of the models presented here, only VS-model takes properly into account the ambipolar operation. In principle, graphene valence and conduction bands are perfectly symmetrical. This means that the electrons and holes have the same effective mass, and conduction of should be symmetrical. This simplification is not always valid, depending on accidental doping, number of monolayers, etc. Another phenomenon that is neglected in most models is the back- or top-gate mod-

37 ulation of the contact resistance. Furthermore, the charge modeling of the GFET varies greatly. With very little comparison to experimental data, the validity of the models is questionable. For example, only one of the models (Habibpour model) was validated for large-signal operation. The scarcity of actual good working GFETs may be the cause of insufficient model validation. Yet another question that I still consider open, is the current saturation of the large-area GFET. The prevailing way of modeling current saturation in GFETs is by surface optical phonons. Few models (which) take into account the pinch-off-like characteristic of the GFET channel which leads to a pseudo-saturation in the channel. 4.2.1

Jiménez Model

One of the very first, or even first, GFET models that can be called compact, was published in 2011 by Jiménez and Moldovan [122]. Although, this model incorporates only an IV-model of a FET, it still took important steps into the direction of a simple GFET model with predictive power. Their model is heavily based on the work of Meric et al. [70] and Thiele et al. [28]. The contribution of Jiménez model is in the way they solve the equation for current Eq. (21). Earlier models had no analytic solutions and required iterative numerical methods to solve. Jiménez model was the first to present an analytic solution. The solution does, however, involve the use of log-function. The solution begins with the manipulation of Eq. (21) by changing the integration variable from dx to dVCH and solving the new integral limits Vcd and Vcs to give the following integral: RV qµW Vcscd nc (VCH ) dVdVCH dVCH R (34) ID = Vcd 1 dV L + µ Vcs vsat (VCH ) dVCH dVCH The voltage drop VCH over Cq can be solved from Fig. 18 together with the assumption that Cq = k|VCH | = (2q 2 /π)(q/(~vF )2 ). The integrating variable VCH is solved based on Fig. 18. −(Ctop + CBG ) + ... ±k p (Ctop + CBG )2 ± 2k [(VGS,top − VDP,top − V )Ctop + (VGS,BG − VDP,BG − V )CBG ] ±k (35) VCH =

(36) Plugging the derivative of Eq. (35) with respect to V and integrating the resulting

38 integral, an explicit expression for the drain current can be written as     k k2 W 3 3 4 4 sgn(Vcd )Vcd − sgn(Vcs )Vcs qn0 Vds − V − Vcs − ID = µ Leff 6 cd 8(Ctop + CBG )

Leff

(37)   q q 2 kVCH s k √ ( + n0 + kV2qCH n log 2 0 2 2q 2q π VCH kVCH q =L+µ + n0 − − k Ω 2 2q 2 2q ! )Vcd  2  23 3 kVCH 2q 2 × + n0 − sgn(VCH ) − n0 3(Ctop + CBG ) 2q Vcs

(38) Equation (??) is indeed simple enough for circuit simulators, although the determination of Lef f requires the use of log-function. Nonetheless, Jiménez model is continuous and differentiable, which is extremely important for compact models. Charge and capacitance modeling is provided in a later article [123], but the derivation is lengthy and will be ignored here. In [123], the drain current is differentiated and charges computed based on the Ward-Dutton’s linear partition scheme. 4.2.2

Wang Model

MIT virtual-source model was originally developed for MOSFETs [124], and the model is applied for GFETs in [71]. The virtual-source model describes the transistor as a barrier controlled device. The VS-model was developed to gain insight into short-channel MOSFET performance [124]. The name of the model comes from the concept of virtual source, i.e. the location of the top of the energy barrier in a MOSFET. The carrier velocity at the top of the barrier is related to ballistic velocity [124]. The VS-model and Wang model adaptation are both based on device physics, but are in essence empirical. In simplest form, the original virtual source model for MOSFETs describes the transistor current as W µeff Qn (0)VDS L = W Qn (0) hυ(0)i = W Qn (0)υSAT υ L = SAT µeff

IDLIN = W Qn (0) hυ(0)i =

(39)

IDSAT

(40)

VDSAT

(41) (42)

where Qn (0) is the virtual source, i.e. Qn (0) = Cinv (VGS − VT ), and υ is the electron velocity at the virtual source. VDSAT is the voltage where the two currents are equal, that is the voltage at which the transistor reaches saturation. The two equations for drain current can be combined by using an empirical function FSAT which in this

39 model is given by FSAT (VDS ) = 

(VDS /VDSAT ) β

1 + (VDS /VDSAT )

 β1

(43)

The effect of the empirical function FSAT is illustrated in Fig. 19. The resulting equation for the drain current is then  (44) ID = W Qn VGS, VDS FSAT (VDS ) υSAT Wang et al. [71] virtual source model adapts the original model for GFETs. From the equations for drain current (45)-(57), it is obvious that the treatment for the GFET is the same. The difference from the original VS-model is that the energy barriers need to be corrected to fit graphene and the different operation regions need to be taken into consideration. Like the original VS-model, the GFET VS-model strives for simplicity and intuitive understanding of the device [71]. VS-model is expected to apply well for submicron GFETs, although the model is applicable for long-channel GFETs also. Wang model describes the IV-characteristic of a two-gate GFET, i.e. back-gate and top-gate. The model has three operation regions; electron conduction, hole conduction and ambipolar conduction. The transistor channel is dominated by electrons when the quasi-Fermi level is above the DP and vice versa for holes. The channel is ambipolar when the transition between n- and p-type occurs and the DP is between the source and drain in the channel [71]. The charge carrier mobility in this model is considered as a fitting parameter. The input parameters are the transistor structure size and material choices. The VS-model doesn’t distinguish between different saturation mechanisms. Therefore no substrate or top-gate dielectric surface phonon energies are required for modeling. The model is relatively simple, yet implementing three operation regions with separate equations for each region may cause some difficulties. The model is only a current-voltage model, thus no large-signal modeling is included [71]. Since Wang model has three separate equations for the drain current, derivatives of the current won’t be continuous. This is a drawback for the model. The virtual-source model has been found to apply reasonably well even for short-channel FETs and ballistic FETs [71]. For ballistic FETs, some of the model parameters require new interpretation, but the agreement with experiments is nonetheless good. Moreover, the model is able to give insight also for ballistic transistors. Wang et al. model is one of the few that includes a series parasitic resistance that is modulated by the back-gate [71]. The VS-model has altogether 11 fit parameters which is a relatively small amount. Wang model for GFETs is quite straightforward although some iterative methods are needed for the model to work. However, Wang et al. claim that their model is numerically efficient [71]. This is because iteration is only required to find in which operation region the GFET is biased and no exp- or log-functions are used. Operation region 1 In operation region 1, only electrons are present in the channel. The GFET acts like a n-type MOSFET, and the equations for current are similar to the original

40 IDLIN IDSAT

IDS (VDS ) ID

VD Figure 19: Virtual source model. Figure drawn after [125]. VS-model [124]. The virtual source electron charge density QVES, e is taken from the C-V-relation used for Si MOSFETs. The voltages used in the equations below are internal voltages, ie. RS and RD must be subtracted. The GFET behavior with only electrons in the channel, is governed by the set of equations: ID, I /W = QVES, e vVES, e Fs   VGS,top − Vt, e QVES, e = Ctop mVT ln 1 + exp mVT Vt, e = V0 + ∆V CBG (VDP,BG − VGS,BG ) V0 = VDP,top + Ctop VDS /VDSAT Fs =  1/β 1 + (VDS /VDSAT )β Imin =

VDS VDS = Rp LG /µef f · W · Qmin

(45) (46) (47) (48) (49)

(50)

where m and β are empirical factors, VT = kB T /q is the thermal voltage and Vt,e are the effective threshold voltages for electrons or holes. Equation (48) is the same as Eq. (18). ∆V accounts for the difference between V0 and Vt,e . Here Imin is the minimum current in the channel caused by the minimum charge Qmin in the channel that cannot be modulated [71]. By symmetry, operation region 3 has the same variables as operation region 1 with the difference that instead of electrons, the channel charge is carried by holes.

41 Operation region 2 Operation region 2 is the most complicated one because both holes and electrons are present in the channel. The ambipolar conduction is described by the following equations In = QVES, e vVES, e Fs, e W Ip = QVHS, h vVHS, h Fs, h W Vnd /VDSAT, e Fs, e = (1 + (Vn /VDSAT, e )β )1/β vVES, e Ln VDSAT, e = µ Vpd /VDSAT, h Fs, h = (1 + (Vp /VDSAT, h )β )1/β vVHS, h Lp VDSAT, h = µ

(51) (52) (53) (54) (55) (56)

where In and Ip are the electron and hole currents which must be equal for current continuity. Vnd and Vpd are the voltage drops over the n- and p-parts of the channel. The current in the channel is evaluated either by In or Ip depending on the relative saturation levels of electron and hole sections. To illustrate, if Fs, h > Fs, e , then ID, II = ID, e,II and vice versa. Operation region 3 Operation region is basically the same as operation region 1, with the exception that the current is carried by holes instead of electrons.

ID, III /W = QVHS, h vVHS, h Fs   −VGD,top + Vt, h QVHS, h = Ctop mVT ln 1 + exp mVT Vt, h = V0 − ∆V

(57) (58) (59)

Imin needs to be added to drain current in hole conduction in the same way as in region 1. The empirical function Fs is also the same as for electrons. Calculating operation region In order to use the Wang model, the operation region must be determined. The calculation requires the use of internal voltages, thus the process is iterative in nature. In all regions of operation Imin has to be added to the the calculated current [71]. The terminal voltages need to be internal voltages.

42

Ln + Lp = LG Vn + Vp = VDS Vt, h + Vt, e VT GX = ⇒ −(VGD + Vp ) + Vt, h = (VGS,top − Vn ) − Vt, e Vn Vp = Ln Lp LG Ln = VGS,top −(Vt, e +Vt, h )/2 1 + (Vt, e +Vt, h )/2−VT GD

(60) (61) (62) (63) (64) (65)

where Ln and Lp are the lengths of the electron and hole channel, respectively. Equation (65) is the result of combining Eqs. (60)-(64). Equation (64) assumes a linear potential drop across the channel when the device is in the ambipolar region. The operation region is determined by the location of the recombination point X, i.e. charge neutrality point. If VDS > 0, the values for Ln and Lp can be calculated and there are three possibilities 1. Lp is negative and Ln > LG : operation region 1 2. Ln is negative and Lp > LG : operation region 3 3. 0 < Ln ,Lp < LG : operation region 2 4.2.3

Habibpour Model

Habibpour semi-empirical model is quite comprehensive because it is a large-signal model, whereas earlier models concentrate on only small-signal behavior. Habibpour model is also the only model that includes validation of the large-signal model against S-parameter measurements [126]. The small-signal model is the classic FET hybridπ small-signal model as shown in Fig. 32. Habibpour model takes into account that electron and hole branch mobilities are not equal and that the contact resistance in S/D-terminals may be different, especially in short channel GFETs. The model is set apart from the other GFET models by the fact that parameter extraction methods are presented as well. The parameter extraction uses both DC and Sparameter measurements to find the extrinsic parasitic elements and de-embed the source-drain resistances from S-parameters. The charge-voltage relation is a square-root equation. Habibpour model provides a closed form solution which can be implemented in a circuit simulator. The drain current modeling begins from the same drift equation, Eq. (21), as the majority of the models existing for GFETs. The charge carrier concentration along the channel n(x) is modeled according to [127]. The drift velocity modeling slightly differs from other GFET models discussed in this thesis, and is modeled as µE(x) (66) vdrift (x) = r  m µ|E(x)| m 1 + vsat

43 where m is a fitting parameter. The drain current equation is compiled of several equations for the different operation regions with a step function Θ [126] ID = Ids1 Θ(VGS )Θ(VGD ) + Ids2 Θ(VGS )Θ(−VGD ) × Ids3 Θ(−VGS )Θ(VGD )... + Ids4 Θ(−VGS )Θ(−VGD ) (67) In order to use the model, the user needs to calculate which operation region of the GFET is valid. The different operation regions are as illustrated in Fig. 8. There are four different regions: 1) electrons are majority carriers in the channel, 2) and 3) both electrons and holes are in the channel, and the electrons and holes are at either S or D ends depending on the terminal voltages, and finally 4) the majority carriers are holes. The equations for the four operation regions are given below and denoted with Ids1,2,3,4 . q q W µe × (VGS Q20 + (CVGS )2 − VGD Q20 + (CVGD )2 Ids1 = q −VGD | m 2L m 1 + ( µe |VGS ) Lvsat p Q2 + (CVGS )2 + CVGS + Q20 /C ln p 20 ) Q0 + (CVGD )2 + CVGD (68) W ¯ W µe V0 Q0 µh V0 Q0 Ids2 = q f (Vgs , 0) + q f (0, V¯gd ) (69) µe |VGS −VGD | m L µh |VGS −VGD | m L m m ) ) 1+( 1+( Lv sat Lv sat µh V0 Q0 W ¯ µe V0 Q0 W Ids3 = q f (Vgs , 0) + q f (0, V¯gd ) (70) µh |VGS −VGD | m L µe |VGS −VGD | m L m m 1+( ) 1+( ) Lv sat Lv sat µh V0 Q0 W ¯ ¯ Ids4 = q f (Vgs , Vgd ) µh |VGS −VGD | m L m 1+( ) Lv sat

(71)

where f (V¯gs , V¯gd ) can be described as p p √ 1 √ 1 f (x, y) = (x 1 + x2 − y 1 + y 2 ) + (ln(x + 1 + x2 ) − ln(y + y 1 + y 2 )) (72) 2 2 with V¯gs = VGS /V0 , V¯gd = VGD /V0 and V0 = Q0 /C = qn0 /C. C stands for the gate capacitance per are C = (Cgs + Cgd )/(LW ). Continuous higher order derivatives are needed for certain simulation techniques, such as harmonic balance and transient analyses [126]. Thus the step function in Eq. (67) needs to be replaced by an approximate continuous function. Habibpour et al. chose a hyperbolic tangent for this purpose. With differentiable equation for the drain current, the intrinsic

44 transconductances in the operation regions can be calculated as follows [126] q  q µe,h W 2 gm1,4 = r V02 + VGS (73) − V02 + (VGS − Vds )2  m L × C µ |V | e,h ds m 1 + Lvsat q µe,h W W µh,e 2 2 gm2,3 = r m L × C V0 + VGS − r m L   µ |Vds | µ |Vds | m m 1 + e,h 1 + h,e Lv sat Lv sat q (74) × C V02 + (VGS − Vds )2 Habibpour model takes into account the asymmetry between electron and hole conduction with an empirical formula. The source and drain series resistances are modeled as Rs = Rs0 + Rext (VGS , VGD ) Rd = Rd0 + Rext (VGS , VGD ) 1 + tanh(VGS /V2 ) 1 + tanh(VGD /V2 ) Rext (VGS , VGD ) = · Rexto 2 2

(75) (76) (77)

where Rext (VGS , VGD ) describes the carrier dependency of the source/drain series resistances, Rexto is an extra resistance that appears in the channel when majority carriers are electrons and V2 is a fitting parameter. 4.2.4

Frégonèse Model

Frégonèse large-signal model is based on the quasi-analytical Thiele model [128] [129]. Frégonèse model has an improved charge model and the model equations from Thiele model [28] are modified to be compatible with electrical circuit design simulators, such as SPICE. The charge model includes the DOS of graphene. Another improvement to earlier models is the addition of charge puddle modeling [128] which makes the model agree better with measurements. The model was verified against DC-data from literature in [129] and a LNA was simulated using the model in [128]. The modeling effort in [129] is divided into three parts. First the metal-insulatorgraphene structure is modeled as in [28]. Second the results are used to obtain a result for the drain current. Finally charge modeling is incorporated. The equivalent circuit of Frégonèse model is shown in Fig. 20. The derivation begins from the equivalent circuit in Fig. 18. The only exception here is that Frégonèse et al. do not assume two separate gates, but only one gate. This slightly changes the equations of Thiele et al. model to following:   q2 |VCH (x)|VCH (x) + NA − ND Qsh (x) ≈ q − π(~vf )2   γ = q − |VCH (x)| VCH (x) + Nf q

(78)

45 where γ = q 3 /(π~vF )2 and all voltages are internal. Using Kirchhof’s law to determine VCH (x) from Fig. 18 gives a quadratic equation (CT G ) (VCH (x) − VGS + V (x)) − γ |VCH (x)| VCH (x) + qNf = 0

(79)

The solution to Eq. (79) is plugged into Eq. (78) to get the bias dependent mobile carrier charge Qnet (x) = Qsh (x) − qNf . The equation for drain current is in principle the same drift current as given in [28], but the residual carrier density npuddle induced by spatial inhomogeneity is added into the calculations R VDS (|Qnet | + qnpuddle )dV (80) ID = qµW 0 RV L + µ 0 DS 1/vsat dV npuddle = ∆2 /(π~2 vF ) Ω vsat = p π|Qnet (x)|/q + npuddle

(81) (82)

where ∆ is the spatial inhomogeneity within the graphene layer with electron and hole puddles being equal in size and Ω is the relevant optical phonon frequency. Saturation velocity vsat ignores any second order effects. Equation (80) can be further simplified by taking an average value for vsat with assuming an average charge in the channel by V (x) = VDS /2. It should be noted that the numerator of Eq. (80) has an analytical solution which can be directly inserted in a circuit simulator. The large-signal model is derived from the total charge in the channel Z L (Qnet (x) + qnpuddle )dx (83) Qch = W 0 Z VDS 1 β ( |Vch |Vch + npuddle )dV (84) ≈ qW EAV 0 e  −1 (|Qnet,av | + qnpuddle )µW µ EAV ≈ + (85) ID vsat,av where EAV is the average electric field in the channel. The channel charge can be solved analytically (full solution is available in [129]). The gate-source and drainsource capacitances can be solved from according to Eq. (30) and (29) as the derivative of the total charge. 4.2.5

Rodriguez Model

Rodriguez large-signal model [130] is based heavily on Frégonèse model. It is a simplification with analytic closed form equations which can be used for rule-ofthumb performance calculations. Furthermore, the model was used to calculate and simulate the harmonic and intermodulation distortion performance of GFETs [131]. They found that the transconductance nonlinearity is the main source of distortion

46 Dext

Cpar

RD D CGD Gext

G RG

Ids S

CGS RS

Cpar

Sext

Figure 20: Large-signal equivalent circuit accorging to [129]. in GFETs [131]. Rodriguez model validation was against the full Frégonèse model and measurement data from literature [130]. The drain current is modeled after Eq. (80). The assumptions that were made in Frégonèse model also apply for Rodriguez model. Few additional assumptions have been made in Rodriguez model to further simplify the drain current (Eq. (80); the drain current solution is simplified by determining which terms dominate for typical GFET technology parameters and by assuming that Qnet,av = CT G (Vef f − VDS /2 qN where Vef f = VGS + CT Gf . The drain current is then given by equation ID '

µWCT G (Veff − VDS /2) q p µ πCT G L + Veff − VDS /2 VDS Ω e

(86)

The simplification of the drain current comes with the cost of limited applicability of the model to GFETs, ie. the model doesn’t work in all possible operation regions or for all technology parameters of the GFET. The transconductance is calcuted from Eq. (86) for the drain current as δID |V ,const. δVGS DS   ID = × Veff − VDS /2

gm =

1 ID 1− 2 WΩ

r

π 1 p e × CT G Veff − VDS /2

! (87)

47 Similarly, the drain conductance is calculated from Eq. (86) go =

δID |V δVDS GS,const.

(88) 

=

Veff



µ Ω

q

πCT G e



1 ID  L ID  × − + + p − VDS /2 2 µWCT G VDS 2 4 Veff − VDS /2

(89)

The small-signal model is essentially a hybrid-π model. The small signal model ≈ VLDS and Qch ≈ simplifications that were made to Frégonèse model EAV ≈ dV dx WCT G will yield VDS Veff − VDS EAV 2 Qch ≈ CT G WL (Veff − VDS /2) δQch CT G WL = Cgd = − δVDS VGS,const. 2 δQch = CT G WL Cgs = δVGS VDS,const.

4.3

(90)

(91) (92)

Models Summary

I have chosen to review three physical models and five compact models in the previous sections. The models were chosen based on how useful I deemed the model to be from electronic circuit design perspective. Ryzhii model is to my knowledge, one of the very first GFET models, but it is too complicated for circuit design use. Meric and Thiele models are quite similar in many ways, but Thiele model incorporates charge modeling whereas Meric model does not. Both models require iterative methods to find the solution for the drain current. Because solving the drain current requires numerical methods, no quick rule of thumb calculations are possible. Meric model was implemented in Matlab, because Matlab allows to iterate the solution. Figure 21 shows the results for a typical GFET with no RS and a significant resistance. The GFET parameters that were used in simulation are shown in Table 2 Jiménez compact model was based on the modelling efforts of Meric et al. and Thiele et al. Jiménez modeling contribution is mainly in providing an analytical solution to the drain current equation. In a later article, charge modeling is added to Jiménez model [123]. Wang VS-model is more empirical although the basic building blocks are based on physics. Wang model makes only few assumptions of the GFET device physics when compared to e.g. Meric model, yet Wang model manages to reproduce the correct device operation. Wang model was the first to properly take into account that the series resistances are a function of terminal voltage. Habibpour model is the most comprehensive model so far. Habibpour model is a large signal model which has been validated against S-parameter data. None of the previous models presented model validation against S-parameters. Moreover, Habibpour et al. article addresses the parameter extraction, which had thus far been overlooked.

48 Frégonèse model improves upon the Meric and Thiele models by adding the residual charge caused by spatial inhomogeneity and by finding a relatively simple analytical solution for the drain current. The drain current solution is however quite lengthy and piece-wise continuous. Rodriguez et al. continue the simplification process of Frégonèse et al. further, so that the model is simple enough to allow quick performance calculations. Neither Frégonèse nor Rodriguez model is validated against S-parameter measurements. The Fregonese model was implemented in Matlab to test the behavior of the model. Figure 22a plots the results of a theoretical large area GFET with Al2 O3 as substrate and gate dielectric. The simulation parameters are shown in Table 2. The simplifications in the model equations for current and total channel charge make it very easy to implement in any simulator, although the number of equations is quite high. Also, model implementation is very straightforward because no self-consistent solution or iterative method is needed. The model assumes very aggressive saturation for the current at very low drain bias. The simulated GFET is also assumed to be perfect with no contact resistance or accidental doping. The model does have a flaw; the simplifications lead to situations where the model gives imaginary drain currents. This is due to the square-root term in the solution of Eq. (79). Table 2: The technology parameters of the example GFET.

Fig. RS /RD

µ

Vth

r

tox

L

W



22a 0 22b

1 m2 /Vs

0

7.5

20 nm

1 µm

50 µm

0.054·q 55 meV

21

1 m2 /Vs

0

7.5

20 nm

1 µm

50 µm

NA

0-20Ω



55 meV

The Rodriguez model was implemented in Matlab. The model is based on Frégonèse model, thus the expected behaviour is the same for both models. Figure 22b plots the results of a theoretical large area GFET with Al2 O3 as substrate and gate dielectric. The simulation parameters which are the same for Frégonèse model simulation, are shown in Table 2. This model is by far the least complex of the IV-models presented in this section. Although Frégonèse model is analytical and simple, Rodriguez model is one step further in terms of model simplicity. Current saturation, like in Frégonèse, is almost aggressive and happens at very low bias. Naturally, adding series parasitic resistance and accidental doping will change the situation to more realistic. Furthermore, similarly to Frégonèse model, the drastic simplification of the drain current equation lead to situations where the model gives imaginary drain currents. This is also due to the square-root term in the solution of Eq. (79). None of the modeling articles reviewed in this text quantify the model errors.

49

(a) RS = 0 Ω

(b) RS = 20 Ω

Figure 21: a) I-V graph of a GFET simulated with the IV-model of Meric et al. [70] with Rs = O. The legend shows the top-gate voltage. b) I-V graph of a the same GFET simulated with a Rs = 20 Ω. The legend shows the top-gate voltage and the arrow shows the growth direction of gate voltage. The saturation velocity was assumed to be vsat =5e5 m/s

(a)

(b)

Figure 22: a) I-V graph of a GFET simulated with the Frégonèse IV-model. b) I-V graph of a GFET simulated with the Rodriguez IV-model. The legend shows the top-gate voltage and the arrow shows the growth direction of gate voltage. Furthermore, few of the models mention anything about computation efficiency. Thus, model comparison is not available in literature. Parameter extraction is discussed only by Habibpour et al. [126]. In our work we have typically used a simple voltage controlled resistor with series parasitic resistance in series to describe the DC characteristics of the GFET. Our other approach has been to simply extract the transconductance and drain conductance from DC measurements and combine that information with contact resistance values from curve-fitting to VGS − ID -trace. We have also measured scat-

50 tering parameters of GFETs and extracted the parameters according to hybrid-π model [3].

51

4.4

Parameter Extraction from Measurements

Any model is ever only as good as the data it is based on. Accurate, consistent measurements are the basis of successful parameter extraction. Ideally, most of the parameters are extracted self-consistently to prevent errors in early stage extraction from multiplying in secondary parameters. Decades of MOSFET parameter extraction from measurements has turned into a form of art, where accumulated knowledge has led to efficient practices. However, parameter extraction for GFETs is not a well-established practice. Often, one has to make measurement and parameter extraction decisions based on contradicting results in the field and pick a method that seems the best. The reason for lack of clear extraction method is nonetheless simple, graphene device physics is not yet fully understood, thus the interpretation of results and choice of best methodology is not based on consensus in the field. Although the lack of standard measurement and parameter extraction methodology is a hindrance to modeling, the fabrication related issues in GFETs are a larger problem. GFETs suffer from many issues, such as ID -VG curve instability, often referred to as hysteresis, interface charge traps and unintentional doping from water molecules [23]. Most of these issues can eventually be solved, but in laboratory samples some contamination is unavoidable because samples travel in and out of the clean room environment. The measurement and parameter extraction methods that are important for compact modeling are reviewed in the following sections. The chapter is organized as follows: continuous direct current measurements are discussed first, followed by pulsed-IV measurements, series parasitic resistance extraction methods and scattering parameter measurements are discussed thereafter. The focus is mostly on DC measurements which are the foundation for all models and further measurements. 4.4.1

DC-Measurements

DC-measurements are the backbone of GFET characterization. The transistor ID VG -curve is first measured to determine the operation points of the GFET. The next step is to measure the ID -VDS -curve with different top-gate voltages. There is a commonly known issue in continuous DC measurements of GFETs; hysteresis. This effect is explained first, followed by a description of the measurements. Hysteresis is often found in continuous DC-measurements of GFETs. This hysteresis may refer to two things in DC characteristics: • the shift of the GFET VGS - IDS trace along the horizontal, and the vertical axis when the gate voltage is swept from negative to positive (forward) voltages and vice versa (backward) • the movement of the VGS - IDS trace along the x-axis between consecutive forward sweeps Hysteresis in forward-backward sweeps is especially prominent in continuous DC measurements when the backward sweep is immediately made after the forward sweep. The phenomenon is demonstrated in Fig. 23a.

52

(a)

(b)

Figure 23: a) GFET transfer instability in forward-backward gate-sweep. b) Two consecutive forward measurements with VDS = 0.5 V. The curve shifts to the right. Typically, one begins the DC measurements by sweeping the gate voltage in the forward direction, and the VGS - IDS -curve shifts to the left (or right) with each sweep until the ’movement’ stops. This hysteresis-like phenomenon is thought to be caused by residues from the GFET fabrication, such as PMMA. The solution for the latter type of instability is current induced annealing, i.e. relatively large current (up to several milliamperes) going through the channel cleans the device by burning adsorbates and other residues away [132] [133]. This type of transfer instability is shown in Fig. 23b. Hysteresis effect in GFETs is not completely understood, although much about the phenomenon is known. Hysteresis in DC measurements can be mitigated by the use of pulsed-IV measurement, which will not remove the underlying causes for hysteresis. Pulsed-IV measurements are necessary to avoid parameter extraction errors, e.g. Rc and mobility extraction from standard DC measurements may have large errors due to the effects of extrinsic factors, such as hysteresis or temperature [134] [35]. Furthermore, as GFET field-effect mobility is extracted from the slope of DC IV-curves, the mobility values can be underestimated due to hysteresis [35]. The high surface-to-volume ratio of graphene makes it vulnerable to environmental factors, such as unintentional doping, unstable and degraded performance [135]. Investigating the hysteresis in graphene is difficult because it is possible that there are several processes responsible for the effect, such as oxide defects, silanol groups on SiO2 surface, contamination and adsorbtion of molecules during fabrication, interface states etc. [134] [84]. Determining which process contributes and how much, is in practice quite difficult. Hysteresis is said to be caused by external electrochemical doping of O2 /H2 O redox couple [134]. Raman spectra has revealed that the SiO2 substrate can dope the graphene and thus cause hysteresis [134]. The interaction between graphene and the SiO2 was also reported to cause hysteresis in [136]. Hysteresis was investigated in [137] as a function of temperature. The hysteresis direction was observed to change

53 at low temperatures from clockwise to counterclockwise. Hysteresis mechanism was not resolved fully by the measurements, but charge trapping/detrapping at SiO2 interface was thought to be the main source of hysteresis [137]. Graphene hysteresis was investigated from the viewpoint of 1/f -noise in [138], where the charge exchange was found to influence the 1/f -noise. However, the time constants in the experiment suggested towards a chemical redox process, such as O2 + 2H2 O + 4e− ↔ 4OH− . Similar reactions have been found in diamonds and carbon nanotubes [138] which supports the hypothesis. Thus the low frequency noise in the graphene channel was found to correlate with chemical processes that generate charges instead of charge trapping via tunneling [138]. GFET hysteresis was studied systematically in [84]. The dominant hysteresis mechanisms discovered were charge trapping and interfacial redox reaction. The results are in line with previous studies. The slow interfacial redox reaction was found to contribute 13-22 % and the fast charge trapping process contribution was 78-87 % [84]. The solutions to eliminate hysteresis are to improve fabrication and cleaning procedures, use suspended devices, vacuum anneal or surface passivation [134] [35]. Surface passivation needs to be diffusion-resistant or hydrophobic to effectively block oxygen [35]. Vacuum annealing the sample has been reported to work only until the sample is brought back to ambient [135] which makes it less than ideal solution. The use of another substrate than SiO2 has also been suggested, e.g. hexagonal BN could be a better substrate for graphene [135]. Another approach is to use a hydrophobic substrate or use chemical treatments to mitigate hysteresis effects [135]. The DC traces are based on external bias voltages. These measurement sweeps are quick to perform on a semiconductor curve tracer, but the measurements I made were done with a homespun measurement set-up consisting of several power sources and current meters. The measurements were done with continuous signals due to a RC-filter that was used to prevent switching transients. The curve traces are measured directly on-wafer with microprobes attached to a vibration damped probe station. The probe station used in ECD laboratory is shown in Fig. 24. A typical measurement setup at ECD laboratory consists of a Advantest R6243 combined DC source and ammeter, RC-filter with time constant of 300 ms, an Agilent 8722ES vector network analyzer (VNA), a HP 34401A voltmeter, LC-filter with time constant of 0.1 ms, an Agilent 3458A ammeter and a HP 3245A DC source. The samples are probed with Cascade Microtech RF ACP40-GSG probes with 100-150 µm pitch. Labview is used to control the measurement equipment and collect data. Several parameters can be obtained directly from DC-measurements of GFETs if both VG - ID - and VD - ID are traced. Parameters which can be resolved from DC curve trace: • max current, min current at any DC point (primary) • saturation current (primary) • Dirac-point (primary)

54

Figure 24: On-wafer probing. • extrinsic drain conductance (primary) • extrinsic transconductance (primary) • intrinsic gain (primary) • series parasitic resistance (secondary) • mobility (secondary) • charge carrier density at DP (secondary) • estimation of fT,max (secondary) Primary parameters can be extracted directly from the data and secondary parameters can be extracted with the help of material parameters and knowledge of the device geometry. Transconductance and drain conductance are calculated by differentiating the IV-curve. Differentiation is a noise producing operation, and all parameters calculated based on differentiated parameters will have more noise. The following sections will explain how series parasitic resistance can be extracted or measured from separate test structures. 4.4.2

Pulsed-IV Measurements

Pulsed-IV measurements have been previously used for MOSFETs. Early high-κ dielectrics for MOSFETs had severe charge trapping and pulsed-IV has been used to measure these effects [139]. Electron traps are analogous to capacitors which charge and discharge very fast, within microseconds. Another phenomenon at play in MOSFETs is heating which may hinder the proper characterization of the transistor. Pulsed-IV has been suggested to be used for GFETs by many, e.g. [23, 35, 83, 133,

55 137, 140]. The reasons for using pulse-IV in GFET characterization are much the same as for MOSFETs although the effects of heating have not been as extensively researched. In a pulsed-IV measurement, both the drain and the gate voltages are pulsed, and the current measurement is done during the pulse on time. The idea is that the pulse is on for such short time that no charge trapping or self-heating effects would have enough time to change the device. Typical pulsed-IV set-up for GFET characterization has 500ns pulse width and period 100 µs [83]. The synchronization of the pulses is important for measurement accuracy, but since the measurement is standard in the industry, measurement equipment is readily available in the market. Triangular pulsed gate voltage has been reported to minimize the hysteresis [141] while the drain voltage is kept constant. This kind of a set up may be easier to build than a full pulsed-IV system, should there be no pulsed-IV systems available. Especially GFET transfer curves are affected by charge trapping effects, which can be solved by using pulsed-IV [35]. The difference between the standard DCmeasurement and pulsed-IV measurement results becomes more severe the more defective the graphene is [35]. GFETs commonly show no current saturation, and one of the reasons is trapped charges in dielectric interfaces [83]. Trapped charges act like capacitances which under continuous DC measurements charge and add to the current. Meric et al. report that current saturation is observed in small gate length GFETs, down to 130 nm, when both the gate and the drain voltages are pulsed [83]. However, resorting to standard DC measurement, the GFET device parameters would degrade as the channel length shortened [83]. In the same experiment the transconductance was found to be independent of channel length when measured with pulsed-IV. Pulsed-IV measurements have been reported to have very little effect on long channel GFETs, i.e. the gate length is longer than 1 µm [83]. Lee et al. even suggest that GFETs should only be characterized with pulsed-IV vacuum system due to the hysteresis effects caused by oxygen induced redox reactions [35]. A fundamental problem with hysteresis and masked current saturation is that, even though the effects can be eliminated with pulsed-IV measurements, a real world transistor will still suffer from those effects. While pulsed-IV is a solution to investigating the intrinsic behavior of the GFET and the extrinsic factors which affect it, eliminating these effects completely is still necessary for electronics applications. 4.4.3

Series Parasitic Resistance

DC curve traces of a GFET cannot distinguish between the intrinsic transistor and the parasitic elements in the GFET. Therefore, ways of extracting the series parasitic resistances are extremely important to find the intrinsic performance of the transistor. Series parasitic resistance in this thesis means the sum of the contact resistance and the ungated channel of a transistor. For GFETs, contact resistance may be very high, even roughly up to 80% of the total channel resistance. Graphene-metal contact resistance can be measured in several ways. In the following sections, I have chosen to review methods to determine the series parasitic resistance. All of the methods are well documented in literature. The most con-

56 venient way is to measure the IV-characteristics of a transistor and get the series resistance through curve-fitting. In this manner, the contact resistance cannot be separated from the ungated channel resistance, but it requires no additional measurements or measurement structures. Curve-fitting is quick, and yields results which are accurate enough for compact modeling. The second method requires no additional test structures, but at least three GFETs with different access lengths and LG . The contact resistance can be measured if several transistors with different gate lengths and access lengths are fabricated on the same die with the same process. The last method, transfer length method (TLM) requires a specific structure to be fabricated, and the actual contact resistance can be measured. TLM for the use of modeling is not very useful, since the series parasitic resistance of the specific GFET cannot be determined by TLM. Although, TLM will provide an estimate for the lower limit of contact resistance. TLM is most useful for device and process development and control, because the measurement of a TLM structure is quick and the influence of a single process variable on the contact resistance can be relatively easily measured. It should be noted that all of the above methods only work for diffusive transistor channels. In practice, nearly all large-area GFET have diffusive channels. To ensure that the transistor is not working in ballistic region, the transistor mean free path should be determined. As a rule of thumb for GFETs, the channel lengths longer than 500 nm are always diffusive. Other methods to check for ballistic channel, is to plot the field-effect mobility as a function of gate length or extract the virtual source velocity. If the mobility drops with LG , the channel may be ballistic [125]. This only works when there are several transistors with different gate lengths available. Finally, a method of calculating the intrinsic transconductance and output conductance is presented. The method does not rely on any transistor model, and the parameters are determined directly from the definitions. Another method to bypass the contact resistance altogether is to use the four-probe method, which will not be discussed here as it holds no significance for real transistor applications. In this text the contact resistance of the graphene-metal interface is denoted with Rc and the series parasitic resistance, i.e. the sum of contact resistance and the ungated channel resistance, is denoted with RS (source side) and RD (drain side). Typically it is assumed that RS and RD are equal. We will also assume that the resistance of the metal pads is extremely low compared to GFET resistance, and thus will not affect the measurements. 4.4.4

Curve-fitting

Curve-fitting is the easiest solution to find the series parasitic resistance for modeling purposes since no additional measurements or device structures are needed to apply curve-fitting. If the GFET channel is diffusive, RS can be extracted from VG -IDS

57 Table 3: Curve-fit results for graphene gated GFET with 14/54 µm L/W. The oxide material is Al2 O3 with 30 nm thickness.

RS [Ω]

1530

n0 [cm−2 ]

2.0 ·1012

µ [cm2 /V s]

440

curve using the following equations q ntot = n20 + n[(VGS − VDP )]2 √ ~vF πn qn VGS − VDP = + Cox q ˆ = RS + Rchannel = 2RS + Nsq R ntot qµ

(93) (94) (95)

where ntot is the charge carrier concentration, q is the elementary charge, µ is the ˆ is the predicted total conductivity mobility, vF is the Fermi velocity in graphene, R device resistance, RS is the sum of the contact resistance Rc and access resistance, and Nsq = L/W is the number of squares [127]. Eq. (93)-(95) allows an upper limit estimate of the contact resistance from a single current-voltage measurement, even though the effect of gate voltage on Rc is neglected here. The curve-fit method assumes that mobility is independent of the carrier concentration [35], which at low electric fields is approximately correct. The conundrum of curve-fitting is that any distortions or skews in the data can be fitted, even if the fit does not take all the physical mechanisms into account. For example, in a continuous DC-curve trace charge trapping may decrease the current, which in the curve-fit is translated to an increase in the contact resistance and overestimation of the mobility [35]. To mitigate the charge trapping effect, pulsed IV method is suggested. IV-curves of GFETs typically have some degree of asymmetry between the hole and electron branches which results in different mobility and RS for the branches. An example of a curve-fit for a GFET is shown in Fig. 25. The curve-fit results are shown in Table 3. The GFET in question displays some asymmetry. The series resistance is given for the whole device both in the figure and the table. 4.4.5

Access Length Method

The contact resistance can be determined directly from IV-traces of GFETs with different gate lengths LG [142] [143]. However, the method requires at least three different LG with two different access lengths LA to be fabricated. The total resistance RT is determined at a bias point far from the Dirac point, because the contact

58

Figure 25: Curve-fit result for the GFET in Table 3. The line is for the fit and stars for measurement points. and access resistance dominate there. For example, let us assume three GFETs with gate lengths LG,1 , LG,2 and LG,3 with access lengths LA,1 , LA,2 and LA,3 . The method requires that LA,1 = LA,3 . Then the following calculations can be done: ∆LG = LG,3 − LG,1 ∆Rtotal =

LG,3 Rtotal



(96)

LG,1 Rtotal

(97) (98)

total · LG from which the The total resistance can be expressed as Rtotal = 2RS + ∆R ∆LG series resistance RS can be calculated for all three GFETs. For GFETs LG,1 and LG,3 the series resistance should be the same since they have the same access length. Now the contact resistance can be calculated as follows

∆LA = LA,3 − LA,2 ∆RS =

L RS G,3 L



(99)

L RS G,2

(100) L

⇒ Rc = RS G,2 − RA = RS G,2 −

∆RS · LA,2 ∆LA

(101) (102)

Unlike the curve-fitting method, this method gives both the access and contact resistance for a GFET, although it requires three gate lengths and accurate knowledge of the access length. The three different size GFETs also need to be on the same die for the results to be reliable.

59

Figure 26: Transfer length measurement structure 4.4.6

Transfer Length Method

A well-known method to directly measure Rc is the transfer length method (TLM) that should not be confused with transmission line model (also TLM) used to characterize semiconductor sheet resistance and Rc [36]. Both methods use the similar test device geometry, but transfer length method has more than three contacts. Transfer length method test device is shown in Fig. 26. Transfer length measurement is performed so that the total resistance is measured between adjacent contacts, e.g. in Fig. 26 the resistance is measured between A-D, D-B, B-E, E-C and C-F. The measured total device resistances are plotted against the contact spacing. Contact resistance is the value of resistance at zero distance. TLM gives the sheet resistance, the contact resistance and the specific contact resistivity. TLM measurement should be conducted with low-fields, but away from the Dirac point. Changing the gate voltage in a back-gated TLM structure gives an additional dimension to the data. Transfer length method has been widely used in literature, for example in the following [39], [44] and [144]. The contact resistance can be calculated according to Rtotal =

Rsh Rsh d + 2Rc ≈ (d + 2LT ) W W

(103)

where d is the distance between contacts, Rsh is the graphene sheet resistance and LT is the transfer length.

60 RG Vg,ext

RD

Vg,int Vs,int

Intrinsic FET

Vd,ext

Vd,int

RS Vs,ext Figure 27: A typical transistor schematic depicting the transistor parasitic resistances. 4.4.7

Intrinsic Transconductance and Output Conductance

For circuit modeling, the intrinsic transconductance gmi and output conductance gdi are important parameters. These can be calculated with Eq. (27) and (28) when the contact resistances are assumed to be zero. However, contact resistance in GFETs is large and has to be taken into account if intrinsic parameters are to be extracted. Figure 27 illustrates the situation of the intrinsic FET and parasitic resistances. The gate parasitic resistance is usually small compared to RS and RD and mostly significant only in high frequencies, which is why RG is often neglected completely. The extraction of intrinsic transistor parameters is a well-known problem. The contact resistance is usually divided between two resistances, source resistance RS and drain resistance RD . If the output conductance is zero, the intrinsic transconductance is given by gmi =

gm 1 − RS gm

(104)

GFETs on the other hand are expected to have large resistances at both source and drain ends. Assuming that the source and drain resistances are independent of voltage bias, equations for intrinsic FET parameters can be derived according to Chou et al. [145]. The series parasitic resistance consists mostly of Rc , which is in turn dominated by the gate independent part [144]. Thus the assumption of the gate independent RS is considered valid. The derivation begins from finding the 0 0 intrinsic voltages VDS and VGS given by 0 VDS = VDS − RSD ID 0 VGS = VGS − RS ID

(105) (106) (107)

where RSD = RS + RD . The source is the reference potential. The differential of ID is 0 0 dID = gmi dVGS + gdi dVDS (108)

61

(a) The external gm .

(b) The calculated intrinsic gm .

Figure 28: The Vds voltage goes from -0.1 to 0.1 with 0.02 voltage steps in both a) and b). The top gated GFET dimensions are L= 0.5 µm, W=25 µm. Inserting Equations (106) and (107) into Eq. (108) will give gmi and gdi as a function of the extrinsic transconductance and output conductance as (1 + RSD gdi )gm 1 − RS gm (1 + RS gmi )gds gdi = 1 − RSD gds

gmi =

(109) (110) (111)

Before intrinsic parameters can be calculated, the parasitic series resistance i.e. RS and RD must be extracted from the DC data. An example of the extraction of intrinsic transconductance is shown in Fig. 28. The intrinsic transconductance in Fig. 28b is positive because absolute values of gm for hole conduction side are used. When no back-gate is used to modulate series parasitic resistance RS , it is safe to assume that RS value is fixed. Once RS is extracted from DC-measurements, the scattering time τ and mean-free-path length Lm can be calculated using Einstein relation [146] p ~ (112) τ = σ π/n · 2 q vF Lmf p = vF τ (113) where vF is the Fermi velocity in graphene and σ is the intrinsic channel conductivity. Figures 29 and 30 demonstrate the intrinsic channel properties. Only electron conduction is shown here. The sample in Figs. 29 and 30 is quite typical, but far from the state-of-the-art. 4.4.8

Scatttering Parameter Measurements

RF measurements provide information about the operation of the GFET under small-signal conditions. S-parameters provide the external parasitic elements and

62

Figure 29: The mean free path and intrinsic conductance of a L=0.5 µm W=25µm GFET.

Figure 30: The scattering time of a L=0.5 µm W=25µm GFET.

63

Figure 31: On-wafer short, open and thru calibration standards. resolve the charges, i.e. the model capacitances. An RF test system comprises of a vector network analyzer, RF cables and bias cables, power supplies and wafer probes. RF measurements are performed with a vector network analyzer (VNA). VNAs measure scattering parameters (S-parameters) which can be converted to other parameters, such as hybrid parameters. S-parameters describe the behavior of a linear system under steady state conditions. S-parameters are measured in terms of complex reflected and transmitted power through the device-under-test ports. Power is used as the measured quantity because at high frequencies it is easier to measure than voltages and currents. S-parameters are subset of X-parameters, which apply for both large- and small-signal operation. X-parameters can describe also the nonlinearity of a device, but X-parameters are not often used in university research due to high cost of equipment. Successful S-parameter measurements require careful calibration of the VNA and set-up. Calibration is done to ensure that the measured data is valid and to quantify the error in a test system. Calibration defines the electrical reference plane. Moreover, the calibration should be done separately for each GFET structure. Calibration corrects the parasitics from the surrounding environment, cables and signal crosstalk. A common calibration method is short-open-load-thru (SOLT). SOLT on-wafer calibration standards are shown in Fig. 31. In on-wafer measurements, de-embedding the probe pads is important [147]. The series parasitic resistance from the curve-fit is used in de-embedding. A ’stripping method’ de-embedding procedure using a measured open structure is used to subtract the influence of the pads. The impact of the terminal resistances (ZR ) is then removed as in Fig. 27. The admittance equation for the de-embedding is  −1 YFET = [YDUT − YPad ]−1 − ZR (114) The hybrid-π - small-signal model, see Fig. 32, parameters for the intrinsic

64 G CGS

CGD

D gm VGS

r0

CDS

S Figure 32: Classic FET hybrid-π small-signal model. transistor after the de-embedding can be calculated using the following formulae: gm =