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symmetric blocking SiC p-GTO thyristors. The proposed thyristor structure features a positive bevel edge termination implemented by orthogonal dicing ...
Proceedings of the 27th International Symposium on Power Semiconductor Devices & IC's May 10-14, 2015, Kowloon Shangri-La, Hong Kong

The First Demonstration of Symmetric Blocking SiC Gate Turn-Off (GTO) Thyristor Woongje Sung, Alex Q. Huang, B. J. Baliga, Inhwan Ji, Haotao Ke, Douglas C. Hopkins NSF FREEDM Systems Center, North Carolina State University, Raleigh, NC, USA, [email protected]

Abstract—This

paper reports the development of symmetric blocking SiC p-GTO thyristors. The proposed thyristor structure features a positive bevel edge termination implemented by orthogonal dicing technique. In this paper, a detailed design of the device structure, forward current-voltage characteristics, and symmetric blocking capabilities are discussed. Index Terms—4H-SiC, GTO, Edge Termination, Bevel Dicing, junction termination extension (JTE), Reverse Blocking

I. INTRODUCTION 4H-SiC is indisputably the most efficient semiconductor material when used for ultra-high voltage (>10kV) devices due to the high electric field, and substrate material maturity [1-3]. Smaller number of ultra-high voltage SiC IGBTs, and GTO thyristors connected in series with diodes can replace large number of Si power devices in AC applications such as solid-state circuit breakers [4]. For these applications, development of symmetric blocking structures can further reduce the power loss by eliminating the series diodes. Unlike their silicon counterparts, wafer scale SiC power device is not currently available and will remain so for the foreseeable future, this motivates the development of chip-scale symmetric blocking structures. In a symmetric blocking structure, conventional junction termination approaches such as FFRs, and JTE based designs can serve as forward blocking edge termination structures [5]. In order to achieve reverse blocking capability, an orthogonal positive bevel technique was proposed and successfully demonstrated [6-7]. This paper aims to report the first demonstration of the symmetric blocking SiC p-type Gate Turn-Off (GTO) Thyristor. Discussions on the design of the drift layer to maximize reverse blocking characteristics are also provided. II. DEVICE STRUCTURE AND FABRICATION Fig. 1 shows the proposed SiC symmetric blocking GTO thyristor (Fig. 1(a)) and N/P-/N+ reverse blocking test structure (Fig. 1(b)). In this p-type drift region GTO configuration, when negative bias is applied to the Cathode, the upper junction, J1 supports high voltage providing forward blocking capability,

978-1-4799-6261-7/15/$31.00 ©2015 IEEE

while the J2 junction blocks high voltage when positive bias is applied to the Cathode electrode (reverse blocking). One can design the forward blocking edge termination using well-known structures such as floating field rings (FFR), or junction termination extension (JTE). For the simplicity and ease of the process, single implanted multi-zone JTE structure (multiple floating zone-JTE, MFZ-JTE) is used for the forward blocking termination(see Fig.1(a)) [2]. Orthogonal positive bevel termination fabricated by dicing serves as a reverse blocking edge termination. In reverse blocking mode, “positive bevel edge termination” [5] allows the depletion region to extend wider along the bevel surface hence reducing the electric field to less than one half that in the active area, as shown in Fig. 2 [6]. SiC p-type GTO thyristors have been fabricated on P+/N/P-/N+ substrate as shown in Fig. 1(a). Detail parameters of each epitaxial layer are annotated in Fig. 1(a). The anode and gate mesa layers were formed by reactive ion etch processes. The gate contact and MFZ-JTE implants were carried out using nitrogen, followed by high temperature activation anneal process. N+ gate, and P+ anode ohmic metal were formed using annealed Nickel, and Aluminum, respectively. The passivation layer consisted of 1 ȝm of PECVD oxide. The overlayer metal (Ti/Al), with a 2 ȝm of Aluminum, was patterned to serve as the anode metal. Reverse blocking edge termination structure was formed by orthogonal bevel dicing technique using a 45 degree angled blade. At the same time, simple N/P-/N+ test structures (chip size 3 mm × 3 mm) were fabricated to evaluate the reverse blocking characteristics. A 4-inch P+/N/P-/N+ stacked wafer with the above-mentioned specifications (same specification as the GTO wafer) was donated by Cree, Inc. The bevel was formed using an orthogonal bevel dicing technique with a 45 degree angled blade, and the bevel surface was treated with approximately 0.3 μm etch to remove saw damaged layer. It should be noted that the high hardness of SiC smoothens out the surface morphology when rubbed by the dicing saw as shown in Fig. 1(c). In order to reduce the surface roughness and chipping of the SiC beveled surface, the angle of the dicing blade was chosen as 45 degrees, and the feeding speed of the dicing saw was set to 0.5mm/s.

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Anode P+ Ohmic

J1

Gate P+: 2.5um N+ Ohmic N+ 16 -3 N : 3um, 5×10 cm

Passivation

….

MFZ-JTE

CS

FB termination P-drift : 150um, 5×1014cm-3

J2 N+Substrate

Cathode

(a) Anode J1

N : 3um, 5×1016cm-3

Fig. 3. Measured reverse blocking characteristics. Reverse blocking characteristics of dies 1, 2, 3, …, 8 (see Fig. 4) are shown for leakage current comparison.

P-drift : 150um, 5×1014cm-3

J2 N+ Substrate

Cathode 6851 7546 7895 7859

(b)

6930 7100 7448 7541 test site

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(c) Fig. 1. Simplified cross-sectional view of the fabricated symmetric blocking SiC p-type GTO thyristor (a), Schematic cross section of a N/P-/N+ test structure with the reverse blocking orthogonal positive bevel termination (b), and Scanning Electron Microscope (SEM) image of bevel surface diced with 45 degree blade (c).

4068 4426 4507 4750 4596 4676 5019 5604 6211 6091 7492

Fig. 4. Distribution of measured reverse blocking voltages (at current 1mA). It varies from approximately 4kV at the center to 8.6kV at the edge.

III. EXPERIMENTAL RESULTS AND DISCUSSIONS A

B

A’

B’

0.6

Electric Field (A-A’)

Electric Field (B-B’)

1.0 0.4 0.5 0.2

0

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0

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Fig. 2. Simulated electric field distribution of a P+/P-/N+ diode structure. 45 degree angled bevel serves as a reverse blocking edge termination. Y axis in the graphs is electric field in MV/cm.

The breakdown voltage of a symmetric blocking N/P-/N+ structure is affected by the reach through phenomenon. At a given thickness of the drift layer, optimum doping concentration should be calculated to achieve optimum open base symmetric blocking voltages [5]. For instance, using a 150 μm thick drift layer with 8 × 1014 cmí3 doping concentration results in approximately 11kV for forward, and reverse blocking capability. We used an available 150 μm thick, 5 × 1014 cmí3 doped P-drift layer in order to demonstrate the symmetric blocking capability. With the given parameters of the wafer, device simulations show that the drift layer will be reached through approximately at 7.2kV in the reverse blocking mode. It should be noted that depletion extends wider along the bevel surface during the reverse blocking mode, resulting in reach through at a lower voltage than the bulk region.

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Fig. 3 shows the measured reverse blocking characteristics of the N/P-/N+ test structure. Breakdown voltage in the reverse direction was as high as 8.6kV, which is higher than the theoretically calculated value with the doping concentration of 5 × 1014 cmí3. Fig. 4 shows the reverse blocking voltage distribution over the wafer. As observed, it shows a clear trend; reverse blocking voltages are low and somewhat uniform within the near-center dies, and then increase when approaching the edge of the wafer. This trend may be attributed to the doping density variation on the wafer. Since the breakdown voltage of the fabricated N/P-/N+ structure is determined by the reach through phenomenon, lighter doped dies are reached through at lower voltage and vice versa. In fact, the doping density tolerance of thick P-type epitaxial layer is twice as high when compared to the N-type epitaxial layer (±25% vs. ±50% for N-type, and P-type epitaxial layers, respectively) [8]. The observed variations in blocking voltage is consistent with a doping variation from 3 × 1014 to 6 × 1014 cm-3. Investigation on the doping uniformity over the wafer is in progress. The reverse blocking leakage current is also lower in the center area, and higher near the edge of the wafer as shown in Fig. 3. It should be noted that this trend is not originated from the doping non-uniformity because very low reverse leakage current was also confirmed by previous experiments using a more heavily doped drift layer [6]. Instead, it can be explained by the distribution of material defects over the wafer. 4H-SiC defects such as screw dislocations, and stacking faults propagate from the substrate, which may result in an increase in leakage current in blocking mode [9], [10]. In the reverse blocking mode, the depletion extends from the bottom junction, J2, and is easily affected by these types of defects. It is encouraging to find this distribution of the breakdown voltage, and leakage current, because it can be translated that process yield of bevel edge termination is good enough to reveal raw material parameters. One can expect this non-uniformity in performance can be resolved by properly adjusting the target doping concentration so that avalanche behavior determines the blocking voltages in both directions. Symmetric blocking SiC p-type GTO was fabricated as described in the previous section using the same wafer stack. Fig. 5 shows the microscope image of the fabricated GTO taken after the photo-lithography process for the MFZ-JTE ion implantation (Fig. 5(a)) and the final GTO chip packaged on a DBC substrate (Fig. 5(b)). Chip size of the fabricated devices is 6.37mm×6.37mm, and the active device area is about 17mm2 (4.12×4.12 mm2). Fig. 6 shows the measured forward on-state I-V characteristics. Forward I-V characteristics at elevated temperatures confirm the conductivity modulation in the drift layer. Compared to previous results on the SiC p-type GTO structures [3], [4], the measured I-V characteristics shows larger forward voltage drop, which may be attributed to low drift lifetime, non-optimized ohmic metal process, or high density of recombination centers due to poor passivation quality.

Forward blocking MFZ-JTE Anode mesa

Gate mesa

(a)

Gate Anode Cathode

(b) Fig. 5. Microscope image of the symmetric blocking SiC GTO after the photo-lithography process for JTE ion implantation (a), and the SiC GTO in the in-house packaging.

Fig. 6. Forward on-state characteristics of the fabricated SiC symmetric blocking GTO at various temperatures. Gate current, Ig=140mA.

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REFERENCES [1]

Fig. 7. Symmetric blocking characteristics of the fabricated SiC GTO

Fig. 7 confirms the symmetric blocking capability of the fabricated p-GTO, showing 3.3kV, and 3.8kV forward and reverse blocking voltages, respective. As shown in the reverse blocking experiment, the blocking characteristics would vary across the wafer. In connection with this observation, the measured reverse blocking voltage with low leakage current is in the reasonable range. Forward blocking voltage can be increased by adopting better-quality passivation film, and well-controlled JTE charge in the forward blocking edge termination region.

B. J. Baliga, Silicon Carbide Power Devices. World Scientific Publishing Co. Ltd., 2005, Chap. 2, Section 2.1, pp.16–21. [2] W. Sung, E. Van Brunt, B. J. Baliga, and A. Q. Huang, ”A New Edge Termination Technique for High-Voltage Devices in 4H-SiC – Multiple-Floating-Zone Junction Termination Extension,’’ IEEE Electron Device Lett., vol. 32, no. 7, pp.880–882, July. 2011. [3] L. Cheng, J. W. Palmour, A. K. Agarwal, S. T. Allen, E. Van Brunt, G. Wang, V. Pala, W. Sung, A. Q. Huang, M. J. O’Loughlin, A. A. Burk, D. E. Grider, and C. Scozzie, “Strategic overview of high-voltage SiC power device development aiming at global energy savings,” in Mat. Sci. Forum, Vols. 778–780, 2014, pp. 1089–1095. [4] Q. Zhang, and A. K. Agarwal, “Design and technology consideration for SiC bipolar devices: BJTs, IGBTs, and GTOs,” Phys. Status Solidi A 206, No. 10, 2431-2456, 2009. [5] B. J. Baliga, Fundamentals of Power Semiconductor Devices. New York, NY: Springer, 2008, Chap. 3, pp. 91–162. [6] X. Huang, E. Van Brunt, B. J. Baliga, and A. Q. Huang, ”Orthogonal Positive-Bevel Termination for Chip-Size SiC Reverse Blocking Devices,’’ IEEE Electron Device Lett., vol. 33, no. 11, pp.1592–1594, November. 2012. [7] X. Huang, B. J. Baliga, A. Q. Huang, A. Suvorov, C. Capell, L. Cheng, and A. K. Agarwal, “SiC symmetric blocking terminations using orthogonal positive bevel termination and junction termination extension,” in Proc. Int. Symp. Power Semiconductor Devices ICs, 2013, pp. 179–182. [8] http://www.cree.com/LED-Chips-and-Materials/Materials [9] A. Agarwal, H. Fatima, S. Haney, and S-H. Ryu, ”A New Degradation Mechanism in High-Voltage SiC Power MOSFETs,’’ IEEE Electron Device Lett., vol. 28, no. 7, pp.587–589, July. 2007. [10] R. Singh, “Reliability and performance limitations in SiC power devices,” Microelectronics Reliability, 46 (2006), pp. 713–730.

IV. CONCLUSION This paper has summarized the design, fabrication, and characterization of the symmetric blocking 4H-SiC GTO thyristors. The fabrication of the 8.5kV symmetric blocking test structures in 4H-SiC has shown near ideal breakdown voltage with very low leakage current. Symmetric blocking capability of the fabricated SiC GTO has also been demonstrated for the first time. It is believed that better performance can be attained by implementing well controlled drift-layer parameters, and lower interface charge using a high quality passivation layer. ACKNOWLEDGEMENT The authors would like to thank Cree, Inc., for providing the thick epi wafer used for this study as well as for providing process assistances in annealing the implants, and lifetime enhancement. This work was supported ERC program of the National Science Foundation under Award Number EEC-0812121.

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