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Hafnium Oxide Films for Application as Gate Dielectric
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Hsu, Shuo-Lin
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The University of Arizona.
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HAFNIUM OXIDE FILMS FOR APPLICATION AS GATE DIELECTRICS by Shuo-Lin Hsu
A Dissertation Submitted to the Faculty of the DEPARTMENT OF MATERIALS SCIENCE & ENGINEERING In Partial Fulfillment of the Requirements For the Degree of DOCTOR OF PHILOSOPHY In the Graduate College THE UNIVERSITY OF ARIZONA
2005
2 THE UNIVERSITY OF ARIZONA GRADUATE COLLEGE As members of the Dissertation Committee, we certify that we have read the dissertation prepared by SHUO-LIN HSU entitled HAFNIUM OXIDE FILMS FOR APPLICATION AS GATE DIELECTRICS
and recommend that it be accepted as fulfilling the dissertation requirement for the Degree of Doctor of Philosophy _______________________________________________________________________
Date: November 22, 2005
Kenneth A. Jackson _______________________________________________________________________
Date: November 22, 2005
B. G. Potter _______________________________________________________________________
Date: November 22, 2005
Pierre Lucas _______________________________________________________________________
Date: November 22, 2005
John F. O’Hanlon
Final approval and acceptance of this dissertation is contingent upon the candidate’s submission of the final copies of the dissertation to the Graduate College. I hereby certify that I have read this dissertation prepared under my direction and recommend that it be accepted as fulfilling the dissertation requirement.
________________________________________________ Date: November 22, 2005 Dissertation Director: Kenneth A. Jackson
3
STATEMENT BY AUTHOR
This dissertation has been submitted in partial fulfillment of requirements for an advanced degree at The University of Arizona and is deposited in the University Library to be made available to borrowers under rules of the Library. Brief quotations from this dissertation are allowable without special permission, provided that accurate acknowledgment of source is made. Requests for permission for extended quotation from or reproduction of this manuscript in whole or in part may be granted by the head of the major department or the Dean of the Graduate College when in his or her judgment the proposed use of the material is in the interests of scholarship. In all other instances, however, permission must be obtained from the author.
SIGNED: Shuo-Lin Hsu
4 ACKNOWLEDGEMENTS
The author first would like to thank all of the commettee members, Dr. Kenneth A. Jackson, Dr. B. G. Potter, Dr. Pirre Lucas, and Dr. John F. O’Hanlon, for your time and valuable comments. I would like to mention, again, my thesis advisor, Prof. Kenneth A. Jackson for his guidance, support, and patient. I also would like to thank the two most important instructors in the past. They are my undergraduate thesis advisor, Dr. Chung H. Lee, and my master thesis advisor, Dr. Ronald L. Carter. I thank Dr. Donald Hilliard and Dr. Young Gao for their guidance about sputtering and process procedure. I thank to all the people who help me with the analysis: Dr. Mike Carducci of Department of Chemistry for XRD analysis, Tula Jutarosaga and Phil Anderson for TEM analysis, Mr. Paul Lee and Dr. Kenneth W. Nebesny of Department of chemistry for XPS analysis, Dr. Hongbin Zhu (Department of Chemical Engineering), Mrs. Sarah Dahl, and Mr. Mike J. Berman (Microelectronic lab of Department of Electrical and Computer Engineering) for electrical measurements. I would like to thank my two best friends in Tucson, Mr. Shang-Yuan Chung, and Mr. Iing-Yi Wang at Texas Instrument of Tucson division. I appreciate for their valueable discussion. Finally, I would like to devote all I have to my families. They are the most important people in my life. I would like to share all of the honor and happiness with them.
5
DEDICATION
Dedicated to my father
6
TABLE OF CONTENTS
LIST OF FIGURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
LIST OF TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
ABSTRACT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
CHAPTER 1 INTRODUCTION . . . . . . . . . 1.1 MOTIVATION . . . . . . . . . . . . . . 1.2 RESEARCH GOAL . . . . . . . . . . . 1.3 THE ORGANIZATION OF THE WORK
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14 14 17 18
CHAPTER 2 BACKGROUND . . . . . . . . . . . . . . . . . . 2.1 DC MAGNETRON REACTIVE SPUTTERING . . . . 2.1.1 Sputter deposition . . . . . . . . . . . . . . . . 2.1.2 DC magnetron sputtering . . . . . . . . . . . . . 2.1.3 DC magnetron reactive sputtering . . . . . . . . 2.2 THE ELECTRICAL CHARACTERISTICS OF OXIDE 2.2.1 Capacitance–voltage (C–V) characteristics . . . 2.2.2 Carrier transport in dielectric layer [70] . . . . .
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20 20 20 22 24 26 26 36
CHAPTER 3 EXPERIMENTAL DETAIL . . . . . . . . . . . . . . . 3.1 DEPOSITION SYSTEM . . . . . . . . . . . . . . . . . . . . 3.1.1 High vacuum pump . . . . . . . . . . . . . . . . . . . 3.1.2 Sputter chamber . . . . . . . . . . . . . . . . . . . . 3.1.3 Gas distribution system . . . . . . . . . . . . . . . . . 3.2 EXPERIMENTAL PROCEDURE . . . . . . . . . . . . . . . 3.2.1 Sample deposition . . . . . . . . . . . . . . . . . . . 3.3 SAMPLE CHARACTERIZATION . . . . . . . . . . . . . . . 3.3.1 Glancing angle X–ray diffraction . . . . . . . . . . . 3.3.2 Transmission electron microscope cross section image 3.3.3 Chemical analysis . . . . . . . . . . . . . . . . . . . 3.3.4 Electrical measurements . . . . . . . . . . . . . . . .
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39 39 39 41 41 42 43 44 44 44 45 45
CHAPTER 4 THE STRUCTUREAL, COMPOSITIONAL AND INTERFACIAL CHARACTERIZATIONS OF HfO2 FILMS . . . . . . . . . . . . . . . . . . . 47 4.1 X-RAY DIFFRACTION ANALYSIS . . . . . . . . . . . . . . . . . . . . 47
7 TABLE OF CONTENTS – Continued
4.2
4.3
4.4
4.1.1 The XRD pattern of HfO2 films . . . . . . . . . . . 4.1.2 Discussion of crystallization behavior of HfO2 films TEM CROSS-SECTION STUDY . . . . . . . . . . . . . . 4.2.1 As deposited samples . . . . . . . . . . . . . . . . . 4.2.2 The effect of heat treatment . . . . . . . . . . . . . COMPOSITION ANALYSIS . . . . . . . . . . . . . . . . . 4.3.1 Surface analysis . . . . . . . . . . . . . . . . . . . 4.3.2 Interface chemistry analysis . . . . . . . . . . . . . 4.3.3 Discussion of the interface reaction . . . . . . . . . SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . .
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47 50 55 55 57 59 59 63 67 70
CHAPTER 5 THE ELECTRICAL PROPERTIES OF HfO2 FILMS . . . . . . . 71 5.1 CURRENT–VOLTAGE (I–V) CHARACTERISTIC . . . . . . . . . . . . 71 5.1.1 The I–V characteristic of ultra–thin (5.8 nm) HfO2 film . . . . . . 71 5.1.2 Discussion of the conduction behavior of HfO2 films . . . . . . . 75 5.1.3 The comparison with ZrO2 . . . . . . . . . . . . . . . . . . . . . 79 5.2 CAPACITANCE-VOLTAGE (C-V) CHARACTERISTIC . . . . . . . . . 81 5.2.1 The C-V characteristic of as deposited HfO2 films and parameter extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.2.2 The effects of annealing . . . . . . . . . . . . . . . . . . . . . . 86 5.2.3 The influence of sputter pressure . . . . . . . . . . . . . . . . . . 93 5.2.4 Circuit model of an Al/HfO2 /Si MOS diode . . . . . . . . . . . . 95 5.3 RELIABILITY TEST . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 5.3.1 The effect of constant voltage stress on Al/HfO2 /Si MOS diodes . 98 5.3.2 Aging effect on HfO2 films in the ambient . . . . . . . . . . . . . 104 5.4 SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 CHAPTER 6 CONCLUSION AND FUTURE WORK . . . . . . . . . . . . . . 109 6.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 6.2 Future work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
8
LIST OF FIGURES
1.1
The MOS structure including the interfacial layer . . . . . . . . . . . . .
16
2.1 2.2
Schematic of a DC sputtering system (After Chapman [60]) . . . . . . . . Standard configurations for (a) a classic, unmagnetized, parallel plate diode sputtering, and (b) magnetron sputtering (After Hillard [62]) . . . . Generic hystersis curve for system pressure vs. reactive gas flow reate during reactive sputtering. Dotted line represents behavior with an inert gas. (After Westwood [63]) . . . . . . . . . . . . . . . . . . . . . . . . . MIS capacitance–voltage curves. (a) low frequency ; (b) high frequency. (After Sze [64]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The energy band and block charge diagrams for a p–type device: (a) accumulation, (b) flat band, (c) depletion, (d) inversion at low frequency and (e) inversion at high frequency. . . . . . . . . . . . . . . . . . . . . . Effect of φM S on the MOS–C high–frequency C–V characteristic . . . . . Types and locations of charges present in thermally grown SiO2 /Si structure (After Deal [66]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . Capacitance stretch–out due to interface trapped charges (After Sze [68]) The tunneling mechanism of insulator: (a) Schottky emission; (b) Frenkel–Poole emission; (c) Fowler–Nordheim tunneling; (d) direct tunneling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
2.3
2.4 2.5
2.6 2.7 2.8 2.9
3.1 3.2 3.3 3.4
The schematic diagram of the DC magnetron reactive sputtering system The magnification of sputter chamber scheme . . . . . . . . . . . . . . The sandwitch structure of a TEM sample . . . . . . . . . . . . . . . . The schematic diagram of the DC magnetron reactive sputtering system
4.1
The XRD pattern of HfO2 films: (a) as deposited (20 nm); (b) as deposited (5.8 nm); (c) annealed at 600◦ C for 6 minutes (22.4 nm); (d) annealed at 600◦ C for 6 minutes (11.2 nm); (e) annealed at 600◦ C for 6 minutes (5.8 nm); (f) annealed at 720◦ C for 2 minutes (20 nm); (g) annealed at 720◦ C for 2 minutes (10.8 nm); (h) annealed at 720◦ C for 2 minutes (5.8 nm). (m: monoclinic; t: tetragonal) . . . . . . . . . . . . . . . . . . . . . . . . The energy of the HfO2 film . . . . . . . . . . . . . . . . . . . . . . . . Illustrating of the atomic mobility within films with different thickness: (a) thinner film; (b) thicker film. . . . . . . . . . . . . . . . . . . . . . . The dependence of energy release due to annealing on annealing temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 4.3 4.4
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27 32 33 34
36 40 42 44 46
48 50 52 54
9 LIST OF FIGURES – Continued 4.5
The TEM cross section image of as deposited samples: (a) 5.8 nm; (b) 20 nm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6 The TEM cross section images of the 5.8 nm sample annealed at: (a) 600◦ C for 6 minutes and (b) 720◦ C for 2 minutes . . . . . . . . . . . . . 4.7 The X-ray photoelectron spectra of C1s before and after soft sputtering (operated at 4 kV and 15 mA for 25 minutes) . . . . . . . . . . . . . . . 4.8 The XP spectras of O1s and Hf4f before and after sputtering to remove surface contamination (peak position is not calibrated). The interference of hydrocarbon contamination to the signals is clearly observed. . . . . . 4.9 The X-ray photoelectron spectra of as deposited HfO2 film. . . . . . . . . 4.10 The interface XP spectra of Hf4f before and after annealing . . . . . . . . 4.11 The XP spectras of Si2p and O1s at HfO2 /Si interface . . . . . . . . . . . 4.12 The interface reaction of HfO2 /silicate/Si: (a) during deposition; (b) during annealing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 5.2 5.3 5.4
The VG vs. |JG | plot of 5.8 nm HfO2 film before and after heat treatment Schottky and Frenkel–Poole plots for the films before and after annealing The barrier lowering effect of image potential . . . . . . . . . . . . . . . Comparison of I–V characteristic of ZrO2 and HfO2 with comparable physical thickness. The sputter conditions of ZrO2 are: power – 40 W; Ar flow rate – 18.0 sccm; O2 flow rate – 1.90 sccm. . . . . . . . . . . . . . . 5.5 The C-V characteristic of an Al/as deposited–5.8 nm HfO2 /Si MOS diode. 5.6 The frequency dispersion of an Al/as deposited–5.8 nm HfO2 /Si MOS diode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7 The C-V characteristic of Al/as deposited–5.8 nm HfO2 /Si MOS diodes before and after annealing. The heat treatments were performed at 600◦ C for 6 minutes, and 720◦ C for 2 minutes, respectively. . . . . . . . . . . . 5.8 The C-V characteristic of Al/as deposited–5.8 nm HfO2 /Si MOS diodes with different thicknesses of HfO2 films, annealed at 600◦ C and 720◦ C . . 5.9 The frequency dispersion of an HfO2 film annealed at 600◦ C for 6 minutes. The measurement frequencies were 10 k, 100 k, and 1 MHz, respectively. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.10 The influence of sputter pressure to the C–V characteristic (sputter power: 35 W; O2 flow rate: 1.85 sccm; Ar flow rate: 17 sccm) . . . . . . . . . .
56 58 60
61 62 64 65 69 72 74 78
80 81 84
87 89
90 94
10 LIST OF FIGURES – Continued 5.11 Circuit model of: (a)Al/as deposited–HfO2 /Si MOS diode; (b) Al/as deposited–HfO2 /Si MOS diode measured at low frequency; (c) Al/as deposited–HfO2 /Si MOS diode measured at high frequency; (d) Al/HfO2 /Si MOS diode with low defect HfO2 film. (Cox : oxide capacitance; CD : depletion layer capacitance; Cit : interface trap capacitance; CDS : damage silicon layer capacitance; Rp : parallel resistance; Rs : series resistance) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 5.12 The I–V curves of HfO2 films (5.8 nm) before and after stressing for 1500 seconds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 5.13 The C–V curves of HfO2 films (5.8 nm) before and after stress for 1500 seconds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 5.14 The Schottky and Frenkel–Pool plots of as deposited HfO2 film before and after stress. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 5.15 The Schottky plots of HfO2 films annealed at 600◦ C before and after stress.102 5.16 The C–V curves measured before and after aging in the ambient . . . . . 104 5.17 The I-V characteristic of Al/5.8 nm–HfO2 /Si MOS diodes aging for one month . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
11
LIST OF TABLES
1.1 5.1 5.2 5.3 5.4
High-performance logic technology requirement [2] (|JG |: gate leakage current density) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
The leakage current density of a an Al/5.8 nm–HfO2 /Si MOS diode @ VG = −1.5 V before and after heat treatment. . . . . . . . . . . . . . . . 72 The leakage current density of a Al/5.8 nm–HfO2 /Si and Al/5.8 nm– ZrO2 /Si MOS diode @ VG = −1.5 V. . . . . . . . . . . . . . . . . . . . 79 The changes of EOT and Vf b after heat treatment . . . . . . . . . . . . . 86 The leakage current density of Al/5.8 nm–HfO2 /Si MOS diodes before and after aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
12 ABSTRACT
The deposition and characterization of HfO2 films for potential application as a high–κ gate dielectric in MOS devices has been investigated. DC magnetron reactive sputtering was utilized to prepare the HfO2 films. Structural, chemical, and electrical analyses were performed to characterize the various physical, chemical and electrical properties of the sputtered HfO2 films. The sputtered HfO2 films were annealed to simulate the dopant activation process used in semiconductor processing, and to study the thermal stability of the high–κ films. The changes in the film properties due to the annealing are also discussed in this work. Glancing angle XRD was used to analyse the atomic scale structure of the films. The as deposited films exhibit an amorphous, regardless of the film thickness. During postdeposition annealing, the thicker films crystallized at lower temperature (< 600◦ C), and ultra–thin (5.8 nm) film crystallized at higher temperature (600 − 720◦ C). The crystalline phase which formed depended on the thickness of the films. The low temperature phase (monoclinic) formed in the 10 − 20 nm annealed films, and high temperature phase (tetragonal) formed in the ultra–thin annealed HfO2 film. TEM cross–section studies of as deposited samples show that an interfacial layer (< 1nm) exists between HfO2 /Si for all film thicknesses. The interfacial layer grows thicker during heat treatment, and grows more rapidly when grain boundaries are present. XPS surface analysis shows the as deposited films are fully oxidized with an excess of oxygen. Interfacial chemistry analysis
13 indicated that the interfacial layer is a silicon–rich silicate layer, which tends to transform to silica–like layer during heat treatment. I–V measurements show the leakage current density of the Al/as deposited–HfO2 /Si MOS diode is of the order of 10−3 A/cm2 , two orders of magnitude lower than that of a ZrO2 film with similar physical thickness. Carrier transport is dominated by Schottky emission at lower electric fields, and by Frenkel–Poole emission in the higher electric field region. After annealing, the leakage current density decreases significantly as the structure remains amorphous structure. It is suggested that this decrease is assorted with the densification and defect healing which accures when the porous as-deposited amorphous structure is annealed. The leakage current density increases of the HfO2 layer crystallizes on annealing, which is attributed to the presence of grain boundaries. C–V measurements of the as deposited film shows typical C–V characteristics, with negligible hystersis, a small flat band voltage shift, but great frequency dispersion. The relative permittivity of HfO2 /interfacial layer stack obtained from the capacitance at accumulation is 15, which corresponds to an EOT (equivalent oxide thickness) = 1.66 nm. After annealing, the frequency dispersion is greatly enhanced, and the C–V curve is shifted toward the negative voltage. Reliability tests show that the HfO2 films which remain amorphous after annealing possess superior resistance to constant voltage stress and ambient aging. This study concluded that the sputtered HfO2 films exhibit an amorphous as deposited. Postdeposition annealing alters the crystallinity, interfacial properties, and electrical characteristics. The HfO2 films which remain amorphous structure after annealing possess the best electrical properties.
14 CHAPTER 1
INTRODUCTION
1.1
MOTIVATION
Since first commercial integrated circuits device was announced at 1960, the aggressive development of integrated circuit (IC) technology during these forty years has pushed the semiconductor industry from generation to generation. For instance, the silicon wafer size has increased from 2 inch to 12 inch. The feature size of devices is moving into nanometer range. Moore’s law predicts that the chip capacity doubles every one and half years. Indeed, the trend is to make more powerful devices on a smaller area at production rates and lower cost. A major portion of the semiconductor industry is devoted to digital logic IC as well as to memory IC. These two devices are both based on MOSFET technology, in which the metal–oxide–semiconductor (MOS) structure is the most fundamental block. In the MOS structure, the gate capacitance is of primary importance in determining the properties of MOSFET devices, such as threshold voltage and drain current. The gate capacitance is given by C = ²0 ²r
A d
(1.1)
where ²0 is the vacuum permittivity, ²r is the relative permittivity, A is the gate area, and d is the gate oxide thickness. The trend of microelectronic technology has been to scale down the feature size (A) of devices to increase the chip capacity. Therefore, the thickness
15 of the gate oxide has been reduced to maintain the required gate capacitance. However, ˚ as the effective oxide thickness (EOT) is scaled down to ∼13 A[1], large direct–tunneling leakage current results in the loss of inversion layer charge and as a consequence, the transistor performance becomes worse. Also, the static power dissipation increases as the tunneling current increases. The 2003 ITRS roadmap predicts that oxy-nitride will be unable to meet the leakage gate current density limit in 2007 and beyond for the high-performance logic devices (table 1.1). Therefore, to scale the EOT thinner than 1 nm, alternative gate material is required to replace oxy-nitride. Year Gate length (nm) EOT (nm) |JG | limit (A/cm2 ) Simulate |JG | (A/cm2 )
2006 28 1.0 6.0 × 102 4.0 × 102
2007 25 0.9 9.3 × 102 1.3 × 103
2008 22 0.8 1.1 × 103 3.0 × 103
2009 20 0.8 1.2 × 103 3.3 × 103
2010 18 0.7 1.5 × 103 4.0 × 103
Table 1.1: High-performance logic technology requirement [2] (|JG |: gate leakage current density)
Many oxides have been studied extensively, such as ZrO2 [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13], Ta2 O5 [14], La2 O3 [15, 16, 17, 18], HfO2 [19, 20, 21, 22, 23, 24, 25, 26] and silicate [26, 27, 28, 29, 30, 31, 32]. Among these candidates, HfO2 has large band gap (∼ 6.0 eV) [8], significant calculated conduction band offset (1.5 eV) [18], and high dielectric constant (∼ 25 ) [33]. In addition, HfO2 is stable in contact with a Si substrate [34]. Therefore, HfO2 is attracting more attention recently. As the film is prepared, it is inevitable to form an interfacial layer between HfO2 layer and silicon substrate, even if the hydrogen-terminated silicon is used as the substrate [35, 36, 37, 38, 39]. As MOS device with an interfacial layer will have the structure as
16
Figure 1.1: The MOS structure including the interfacial layer shown in figure 1.1 The interfacial layer affects the gate oxide properties in two different ways. As the interfacial layer is inserted into the HfO2 /Si interface, the gate dielectric becomes an HfO2 /interfacial layer stack, which is a bi–layer structure. The entire oxide stack is the two capacitors that are in series. Since the interfacial layer is usually a low-κ material, the existence of the interfacial layer lowers the gate capacitance, and increases the EOT value. However, if the HfO2 is directly contact with silicon substrate, the dangling Hf bonds at the interface results in high interface state [40]. The presence of the interfacial layer is helpful in decreasing the interface state density. So we would like to have an interfacial layer between the HfO2 layer and silicon substrate to modify the interfacial properties [41]. However, if the interfacial layer is too thick, the capacitance is greatly reduced. Therefore, the existence of the interfacial layer is a trade-off between the capacitance and interface quality. A thin interfacial layer is desired to have decent device properties. In the MOSFET fabrication process, high temperature annealing is utilized to activate the implanted dopants. As the oxide is annealed, not only the interfacial properties may change, but also the crystallinity can vary [38, 42]. The variations of interfacial layer
17 include the interfacial layer thickness and chemistry. When the crystallinity as well as interfacial layer properties are changed by the heat treatment, the electrical properties and the device performance will be affected. It is, therefore, crucial to understand the mechanism of crystallinity and interfacial layer variation after heat treatment as well as the influence of these variations to the electrical properties. It is, therefore, crucial to understand the mechanism of crystallinity and interfacial layer variation after heat treatment as well as the influence of these variations to the electrical properties. During operation of a MOSFET device, a gate voltage is applied constantly across the silica gate oxide. Due to this voltage stress, some charges become trapped traps within the oxide. These traps are either native traps generated by process, or the traps generated by high voltage stress [43, 44, 45, 46, 47, 48, 49]. The trapped charges, in turn, result in the variation of the oxide properties, such as the low level leakage current [45, 46, 48, 49], stretchout of the C–V curve [43], and even breakdown of oxide [47, 50]. Similiar reliability issues are observed in high−κ oxides as well [51, 52, 53, 54, 55, 56, 57]. In addition, there are the aging effects when high–κ films are stored in ambient conditions. Carbonate formation [58] and water–related species [59] have been observed to affect the electrical properties of high−κ films. These alter the properties of high–κ films during transormation or storage. These reliability issues, which must be explored before utlizing sputered HfO2 as the gate dielectric, have been explored.
1.2 RESEARCH GOAL As mentioned above, the annealing affects the film properties by changing the crystallinity and interfacial properties. This work is to investigate the variation on crystallinity and in-
18 terfacial properties, and the effect of these variations on the electrical properties, including I–V, C–V and reliability characteristics. DC magnetron reactive sputtering was used to prepare HfO2 films in this work. The sputtering process is known to be versatile, and can be operated at room temperature. However, radiation damage is easily observed if the deposition parameters are not well adjusted. Additionally, the presence of oxygen in the plasma tends to complicate the entire process. To have good electrical properties, radiation damage has to be avoided, and the interfacial layer formation during sputtering deposition has to be minimized as well. Therefore, the sputter conditions have to be carefully optimized to obtain films with low leakage and good dielectric property. Structural, compositional as well as electrical measurements will be performed to the sputtered films. The correlation of the crystallinity and the interfacial properties of the films with their electrical properties is the primary topic of this study.
1.3 THE ORGANIZATION OF THE WORK The organization of this thesis is as the follows: Chapter 2 will describe the background of the work, including the fundamentals of DC magnetron reactive sputtering, capacitance-voltage characteristic of MOS structures and the conduction mechanisms of insulators. Chapter 3 outlines the experimental details of the work. The sputtering set up, experimental procedure, and characterization techniques are described. Chapter 4 will mention the structural and compositional characterization results. The thickness dependence of the crystallization temperature, the composition of the deposited
19 films as well as the interfacial properties, including the interface chemistry and interfacial layer thickness variations are reported. The crystallization behavior of HfO2 films with different thickness will be discussed from the result of glancing angle XRD studies. The interfacial chemistry and TEM cross section results will deal with the interface reactions which occurr during the heat treatment. Chapter 5 presents the results of electrical measurements, which include current– voltage (I–V) and capacitance–voltage (C–V) characteristics. The properties of the gate oxide, such as capacitance and leakage current density will be shown. The constant voltage was performed by stressing the gate dielectric for a certain time to study the reliability of the gate oxide. The effect of the heat treatment was also investigated. Chapter 6 provides a summary of the entire work.
20 CHAPTER 2
BACKGROUND
2.1
DC MAGNETRON REACTIVE SPUTTERING
2.1.1 Sputter deposition Sputter deposition is a process in which atoms are transferred from a target to substrate by using energetic particles to strike the target to remove the atoms. The energetic particles are usually ions of inert gases accelerated in an electric field. The deposition is, therefore, accomplished by building up the sputtered atoms from the target layer by layer. Figure 2.1 shows the typical DC sputter system [60]. The chamber is filled with inert gas (usually Ar) at specific pressure. The target is made of the material we would like to deposit. A high negative voltage, typically 1 kV, is applied to the cathode, where the target is located. Charge carriers are generated by the acceleration of the secondary electrons emitted from the target which collide with gas atoms. The collision between the accelerated electrons and the inert gas atoms forms the ions and more electrons. The ionized species are then accelerated by the electric field, and move toward the cathode to dislodge the atoms on the target surface by momentum transfer. The sputtered atoms move in random directions. Although most of them deposit on the chamber wall, some of them land and condense on the substrate. The condensation of the atoms on the substrate forms the coating.
21
Figure 2.1: Schematic of a DC sputtering system (After Chapman [60])
22 2.1.2 DC magnetron sputtering In DC diode sputtering as we mentioned in the previous section, the secondary electrons emitted from the cathode are accelerated inefficiently, so the generation rate of ions which is balanced by the recombination rate results in a low plasma density. To increase the ionization rate, a magnetic field perpendicular to the electric field is added to modify the moving trajectory of electrons. The electrons travel spirally and have a longer moving distance due to the magnetic field effect, and, thus, the collision probability of the secondary electrons and neutral gas atoms increases. Additionally, the existence of the magnetic field can confine the plasma. So a dense plasma can be formed near the cathode at low pressures (< 5 mtorr) so that ions can be accelerated from the plasma to the cathode without loss of energy due to physical and charge-exchange collisions [61]. However, the planar magnetron configuration does not generate uniform plasma over the target surface as shown in figure 2.2 [62]. The erosion curve of the target is, therefore, position dependent.
23
Figure 2.2: Standard configurations for (a) a classic, unmagnetized, parallel plate diode sputtering, and (b) magnetron sputtering (After Hillard [62])
24 2.1.3 DC magnetron reactive sputtering Reactive sputtering is performed when the deposited film contains volatile species, e.g., oxygen. Thin films of compounds can be prepared by sputtering from metallic targets in the presence of a reactive gas, usually mixed with the inert working gas. Or ceramic targets are sputtered in the atmosphere containing the reactive gas to compensate the loss of the volatile component. The reactive gas molecules are trapped by the sputtered atoms, and incorporated into the coating. The sputtered atoms/molecules react with a gaseous species in the gas mixture, with an adsorbed species or with a co-deposited species to form a compound, solid solution or a mixture of the two. Since the reactive gas is usually mixed with the working gas, to prevent the formation of compound layer on the target surface is a typical problem. This problem is controlled by having a high sputtering rate as well as the appropriate gas composition. Figure 2.3 illustrates the hystesis curve for the variation of system pressure with respect to the reactive gas flow [63]. The dotted line shows the variation of pressure with the inert working gas (Qi ). The pressure increases linearly with the flow rate. The slope of the line gives the pumping speed of the high vacuum pump. As Qr (reactive gas flow rate) increases from Qr (0), the system pressure remains constant, P0 , because the reactive gas is consumed by the reaction. As the critical flow rate, Qr ∗ , is reached, the system pressure raises sharply to p1 . If there is no reaction, the pressure would be higher (p3 ). As the equilibrium pressure is reached, subsequent changes in Qr result in pressure variations (from p1 to p2 ). The pressure changes linearly with the same slope of Qi –P relationship. When Qr is decrease until the reactive gas is balanced by the sputtered atoms, P reaches the initial pressure, p0 . The hystersis behavior represents two stable states, A and B as shown in the figure,
25
Figure 2.3: Generic hystersis curve for system pressure vs. reactive gas flow reate during reactive sputtering. Dotted line represents behavior with an inert gas. (After Westwood [63]) of the system with a rapid transition between them. In state A, the pressure change is little, and the pressure changes linearly with Qr in state B. It is obvious all of the reactive gas incorporates into the film. The atomic ratio of the reactive gas to sputtered atoms, therefore, increases with the reactive gas flow rate. In state B, excess reactive gas is introduced, and consequently, a compound layer forms on the target surface. The thickness of the compound layer depends on the parameters, such as sputtering yield of the target and sputter power.
26
Figure 2.4: MIS capacitance–voltage curves. (a) low frequency ; (b) high frequency. (After Sze [64]) 2.2
THE ELECTRICAL CHARACTERISTICS OF OXIDE
2.2.1 Capacitance–voltage (C–V) characteristics Ideal MOS behavior The high– and low–frequency C–V curves for p–substrate metal–oxide–semiconductor (MOS) capacitor are shown in figure 2.4 [64]. As the d.c. bias is swept from gate voltage VG < 0 to VG > 0, the charges inside the p–type MOS capacitor respond to the applied a.c. signal as the d.c. bias is changed from accumulation, through flat band and depletion, to inversion. As a negative bias is applied to the gate, at oxide/semiconductor interface, the top of the valence band bends upward and is closer to the Fermi level (figure 2.5(a)). Since the carrier density depends exponentially on the energy difference (EF − Ei ), this band
27
Figure 2.5: The energy band and block charge diagrams for a p–type device: (a) accumulation, (b) flat band, (c) depletion, (d) inversion at low frequency and (e) inversion at high frequency.
28 bending causes an accumulation of majority carriers (holes) near the oxide/semiconductor interface. This is the ”accumulation” case. In accumulation, the d.c. state is characterized by the pileup of majority carriers right at the oxide-semiconductor interface. Furthermore, under accumulation condition, the state of the system can vary very rapidly with the a.c. signal. The device can follow the applied a.c. signal by adding or subtracting a small ∆Q on the two sides of the oxide as shown in figure 2.5 (a). Since the a.c. signal simply adds or removes charges close to the two sides of an insulator, the charge configuration inside the accumulated MOS–C is essentially an ordinary parallel-plate capacitor. For either low or high measurement frequencies, it is therefore concluded Caccmumlation ≈ Cox = ²0 ²r
A d
(2.1)
When VG = 0, the MOS capacitor is at flat band condition (figure 2.5(b)). There is no bend bending in the semiconductor. The flat band condition is the border line of accumulation and depletion. The differential capacitance [65] of Si at flat band condition is obtained as f latband CSi = ²0 ²r
where LD is the Debye length, which is LD =
A LD
(2.2)
s kT ²0 ²r NA q 2
(2.3)
The flat band capacitance is analogous to two parallel plat capacitors (Cox and CfSilatband ) in series, which gives 1 1 1 = + f latband CF B Cox CSi
(2.4)
where Cox is the oxide capacitance as shown in equation 2.1 and CfSilatband is the differential capacitance of silicon as shown in equation 2.2.
29 When a small positive voltage (VG > 0) is applied, the bands bend downward, and the majority carriers are depleted from oxide/semiconductor interface (figure 2.5(c)). This is the ”depletion” case. Under depletion biasing, the d.c. state of a p–type MOS structure is characterized by a +Q charge on the gate/oxide interface and a −Q depletion layer charge (ionized acceptors) in the semiconductor. The majority carriers are removed from the depletion layer with an effective depletion width W adjacent to the oxide/semiconductor interface. When the a.c. signal places an increased negative charge on the MOS capacitor gate, the depletion width quasistatically fluctuates about its d.c. value in response to the applied a.c. signal. If the stationary charge is conceptually eliminated, all that remains are small fluctuating charges on the two sides of the double-layer insulator. For all frequencies, this situation is analogous to two parallel plate capacitors (Cox and Cdeplstion ) in Si series, which gives 1 Cdepletion
=
1 1 + depletion Cox CSi
(2.5)
is the capaciwhere Cox is the oxide capacitance as shown in equattion 2.1 and Cdepletion Si tance of depletion layer, which is given by deplstion = ²0 ²r CSi
A W
(2.6)
Since depletion width W increases with increased depletion biasing, Cdepletion correspondingly decreases as the d.c. bias is changed from flat band to the onset of inversion. When a larger positive voltage is applied, the band bending is even larger so that the intrinsic level Ei at the surface crosses over the Fermi level EF . At this point, the number of electrons (minority carriers) at the surface is larger than the holes (majority carrier). The surface layer adjacent to oxide/semiconductor interface is thus inverted, and this is the ”strong inversion” case. Once inversion is achieved, the abundant amount of minority
30 carriers pile up near the oxide/semiconductor interface in response to the applied d.c. bias. The width of the depletion layer is the maximum depletion width, WT , which is given by s 4²0 ²r kT ln(NA /ni ) WT = (2.7) NA q 2 The a.c. charge response, however, depends on the measurement frequency of the a.c. signal. If the MOS–C is measured at a very low frequency (ω → 0), minority carriers can be generated or recombined in response to the applied a.c. signal and the time-varying a.c. state is essentially a succession of d.c. states (figure 2.5(d)). The charges are added or subtracted close to the edges of a single–layer insulator like accumulation condition. It is therefore, concluded at low frequency, C(inv) ≈ Cox
(2.8)
If the measurement is operated at a very high frequency (ω → ∞), minority carriers (electrons) will not be able to be supplied or eliminated by the relatively slow generation– recombination process in response to the applied a.c. signal. The number of minority carriers in the inversion layer therefore remains constant at its d.c. value and the depletion width fluctuates about the WT d.c. value (figure 2.5(e)). The capacitance of silicon at inversion is therefore, analogous to the capacitance at depletion with maximum depletion width WT , which gives inversion CSi = ²0 ²r
A WT
(2.9)
Similar to depletion biasing, the corresponding total capacitance is equivalent to two parallel-plate capacitors in series, which is given by 1 Cinversion
=
1 1 + inversion Cox CSi
(2.10)
31 Non-ideal MOS behavior In the discussion of last section, the MOS diode was assumed to be prefect. However, the metal-semiconductor work function difference (φM S ), charges within oxide and traps at oxide/semiconductor interface are present and shift the flat band voltage.
Metal-semiconductor work function difference In a real device, the energy differences between the Fermi level and vacuum level at metal and semiconductor sides, respectively, are not the same; that is, φM 6= φS = χSi + (Ec − EF )F B
(2.11)
Therefore, when the VG is set as zero, a flat band condition is not achieved. There is a built–in potential between metal gate and semiconductor, which is equal to the difference between metal and semiconductor work function, φM S . For p-type substrate, φM S is given by 1 1 φM S ≡ (φM − φS ) = [φM − χSi − (Ec − EF )F B ] q q
(2.12)
For n-type substrate, φM S is given by 1 1 φM S ≡ (φM − φS ) = [φM − χSi + (Ec − EF )F B ] q q
(2.13)
Because of the φM S , the entire C–V curve will be shifted an amount of φM S volts along the VG axis relative ideal C–V curve as shown in figure 2.6. The amount of φM S is determined by the gate material and the doping concentration of silicon substrate.
32
1.0 N Ideal C-V curve
15
A
x
0
= 10
cm
-3
= 100 nm
C/C
ox
0.8
0.6
ms
0.4
Real C-V curve
0.2 -3
-2
-1
0
1
V
G
2
3
4
5
(Volts)
Figure 2.6: Effect of φM S on the MOS–C high–frequency C–V characteristic
33
Figure 2.7: Types and locations of charges present in thermally grown SiO2 /Si structure (After Deal [66]) Oxide charges and interface trap In addition to the metal–semiconductor work function difference, the presence of oxide charge and interface traps shift the flat band voltage as well. The terminology and location for charges associated with thermally oxidized silicon are shown in figure 2.7 [66]. Interface traps are present at the Si/SiO2 interface. Fixed oxide charges, oxide-trapped charges and mobile charges are inside the oxide. Interface trap (Qit ) are essentially the silicon dangling bonds at Si/oxide interface (Pb ). The Pb defect is amphoteric, with a dornor state at an energy of Ev + 0.30 eV, and an acceptor state at an energy of Ev + 0.80 eV [67]. The interface traps can be charged or discharged over a wide variation of ψs . The presence of interface traps will stretch the C–V curve and shift the threshold voltage as shown in figure 2.8 [68]. The interface trap density is orientation dependent. For orientations with higher atomic density, the atoms are less likely to be fully oxidized. In the < 100 > orientation, the interface trap density is about an order of magnitude smaller than in the < 111 >
34
Figure 2.8: Capacitance stretch–out due to interface trapped charges (After Sze [68]) orientation. Low temperature forming gas annealing (∼ 450◦ C for 30 minutes) effectively decreases the interface trap density (1010 cm−2 eV −1 for < 100 > orientation). The interface trap density can be evaluated by Terman’s method from high frequency C–V measurements. The experimental ψs versus VG curve is a stretched–out version of the theoretical curve, and the interface trap density is determined from this curve by [69] · ¸ Cox dVG CSi Cox d(∆VG ) Dit = −1 − = q ψs q q dψs
(2.14)
The origin of the fixed oxide charges (Qf ) is unoxidized silicon atoms or ions near the SiO2 /Si interface. These unsaturated Si bonds result in fixed oxide charges. For the ˚ the SiO2 /Si structure, the fixed oxide charges are located within approximate by 30 Aof interface. The fixed oxide charges are positive charges, and unlike interface traps, fixed oxide charges can not be charged or discharged as the surface potential is changed. Oxide-trapped charges (Qot ) are related to the defects in oxide layer. These charges are generated, for instance, by radiation damage or electrical stress. Most of the defects generated during processing can be removed by low temperature annealing. Mobile ion charges (Qm ) result from alkali-metal ions, such as sodium and potassium ions. Under high bias-temperature operating conditions, mobile ions move back and forth
35 between gate/oxide and gate/semiconductor interfaces, and cause a reliability problem. The concentration of mobile ionic charges can be decreased by careful process and by using high purity chemicals during process. The flat band voltage shift due to the oxide charges is given by ∆VF B
¸ · Z q 1 d qQox x xρ(x)dx = − =− Cox d 0 Cox d
(2.15)
where d is the oxide thickness, x is the distance of charge centeroid plane to the injecting interface, ρ(x) is the volume charge distribution inside the oxide, and Qox is the planar oxide charge density. The flat band voltage of the MOS diode is therefore, given by VF B = φM S
¸ · Z qQox x q 1 d xρ(x)dx = φM S − − Cox d 0 Cox d
(2.16)
To find the flat band voltage, the flat band capacitance needs to be calculated first from equation 2.4. The shift of flat band voltage is then obtained by comparing the calculated and measured CF B values. The metal–semiconductor work function difference can be calculated by equation 2.12 or 2.13 if the metal work function and substrate doping concentration are known. The difference between the shift of flat band voltage and φM S then gives the flat band voltage shift due to oxide charges.
36
Figure 2.9: The tunneling mechanism of insulator: (a) Schottky emission; (b) Frenkel– Poole emission; (c) Fowler–Nordheim tunneling; (d) direct tunneling. 2.2.2 Carrier transport in dielectric layer [70] Ideal insulators are assumed to be non–conducting; that is, there is no leakage current across the ideal insulator layer. However, in a real diode, at moderate high electric field and temperature, carriers are transported across the insulator. The basic conduction process is shown in figure 2.9. Schottky emission results from the thermionic emission across the emitting interface, which is a metal-insulator interface or insulator-semiconductor interface, as shown in
37 figure 2.9 (a). The field dependence of current density is ³ ´ p q φB − qE/4π²i J = A∗ T 2 exp − kT For Schottky emission, a plot of ln J vs.
√
(2.17)
E which is Schottky plot, yields a straight
line with a slope determined by the insulator dynamic permittivity, ²i . Frenkel–Poole emission is due to field-enhanced thermal excitation of trapped electrons into the conduction band as shown in figure 2.9. The field dependence of current density is given by
³ ´ p q φB − qE/π²i J ∝ E exp − kT
For Frenkel–Poole emission, a plot of ln J/E vs.
√
(2.18)
E, which is Frenkel–Poole plot-
plots yield a straight line with a slope determined by the insulator dynamic permittivity, p ²i . The barrier height, φB , is the depth of the trap potential well, and the quantity q/π²i is larger than in the case of Schottky emission by a factor of 2, since the barrier lowering is twice as large due to the immobility of the positive charge. The temperature dependence of Frenkel–Poole emission is not as strong as for Schottky emission. Frenkel–Poole emission usually dominates at room temperature. Tunnel emission is caused by the electrons tunneling from the Fermi level of the metal into the insulator conduction band, which is known as the Fowler–Norheim tunneling (figure 2.9(c)). The field dependence of current density is " p # ∗ (qφ ) 2m 4 B J ∝ E 2 exp − 3q~E
(2.19)
A Fowler–Nordheim plot is obtained by plotting ln J/E 2 vs. 1/E plot, which gives a straight line with a slope determined by the barrier height, φB .
38 When the oxide field is too high, electrons tunnel from the cathode contact to the anode contact without entering the oxide conduction band, which is the direct tunneling as shown in figure 2.9 (d). Direct tunneling dominates when the film thickness is less than 4 − 5 nm, and the electric field dependence of current density is given by [71] (µ " # r ¶ √ V A 4π 2m∗ q V · d · φB − J= 2 φB − exp − d 2 q 2 " #) r ¶ µ √ ∗ 4π 2m q V V − φB + exp − · d · φB + 2 q 2
(2.20)
Tunnel emission has the strongest dependence on the applied voltage but is essentially independent of the temperature. After an initial current flow, positive and negative space charges will build up near the metal–insulator and the semiconductor–insulator interfaces, causing a distortion of the potential distribution. When the applied field is removed, large internal fields remain which cause some ions to flow back toward their equilibrium position; hysteresis affects the result.
39 CHAPTER 3
EXPERIMENTAL DETAIL
3.1
DEPOSITION SYSTEM
A schematic diagram of the DC magnetron reactive sputtering system is shown in figure 3.1. The reactive sputtering system has three parts: high vacuum pump, sputter chamber and gas distribution system.
3.1.1 High vacuum pump The high vacuum pump is Balzers DIFF 5000 diffusion pump, which is backed by Leybold Trivac D65BCS mechanical pump. A trap is placed between the mechanical pump and roughing valve to prevent the backstream of mechanical pump oil (Formblin). A baffle is located between the high vacuum valve and main chamber to prevent the backstream of diffusion pump oil. Those devices would eliminate the contamination of pumping fluid in the chamber. Two pirani gauges are placed at the working chamber and roughing line, which are for controling and checking the mechanical pump blank–off pressure, respectively. The thermocouple gauge at the foreline is for fault detection. The low pressure of the system is obtained by the ion gauge located in the chamber. A Penning gauge underneath the gate valve measures the blank–off pressure of the diffusion pump.
40
Figure 3.1: The schematic diagram of the DC magnetron reactive sputtering system
41 3.1.2 Sputter chamber The sputter chamber is also the reaction chamber. The primary part is the high voltage cathode with metal target (Hf, bought from Kert. J. Lesker, purity: 99.9 %). The high voltage cathode accelerates the Ar ions, which sputter the target atoms for the deposition to proceed. The substrate is placed on the substrate holder, which is connected to a rotator, so the substrate can be rotated during the deposition process. The substrate faces down to prevent particles landing on it. The pressure of the sputter chamber is measured by the capacitance monometer, and controlled by the throttle valve. The shutter is used to begin and stop the deposition. During the presputtering, the shutter can prevent deposition. The purpose of this design was to limit the size of the plasma, so as to isolate the plasma from the main chamber when the plasma is acitve. During presupttering, the sputter chamber is effectively an ion–pump. Therfore, any contamination is gettered by sputtering, thus assuring the chamber is contamination–free. A gap between substrate holder and chamber was designed intentionally to increase the conductance of gas during the process.
3.1.3
Gas distribution system
Argon and oxygen are used in the process. Ar is used for generating a plasma, and O2 is for the reaction. The two gases are introduced into the chamber separately to prevent the poisoning of target. Argon is introduced into the chamber at the high voltage cathode, and oxygen is introduced from the oxygen distributor on the top of the sputter chamber. The flow rates of argon and oxygen are controlled by mass flow controller.
42
Figure 3.2: The magnification of sputter chamber scheme 3.2 EXPERIMENTAL PROCEDURE High-κ dielectric films were deposited on B-doped P-type silicon (100) substrates with a resistivity 4 − 50 Ω − cm. The silicon substrates were cut into 3.5cm × 3.5cm squares. The silicon substrates were cleaned by the standard RCA process. The substrates first were immersed in piranha (H2 SO4 : H2 O2 = 4 : 1) at 80◦ C for 15 minutes to remove the organic contamination on the surface and then rinsed in by D.I. water for 10 minutes. To remove the chemical oxide formed during piranha clean, the substrates were dipped in dilute hydrofluoric acid (49% HF: H2 O = 1 : 10) for 3 minutes, followed by a D.I. water rinse for 5 minutes. The substrates were then cleaned by SC 1 (NH4 OH: H2 O2 : D.I. H2 O = 1 : 1 : 5) and SC 2 (HCl: H2 O2 : D.I. H2 O = 1 : 1 : 5) at 75◦ C for 15 minutes, respectively, and then rinsed in D.I. water for 10 minutes. Before loading into the chamber, the substrate was dipped into dilute hydrofluoric acid (49% HF: H2 O
43 = 1 : 100) for 1 minute, then rinsed in D.I. water and blown by dry nitrogen.
3.2.1 Sample deposition After the substrate was loaded into the chamber, the chamber was first roughly pumped to 110 mtorr. The roughing valve was then closed and the high vacuum valve is opened. The chamber was pumped down by diffusion pump until the base pressure was reached (∼ 5 × 10−7 torr). Argon was then introduced into the sputter chamber. The voltage cathode was turned on to ignite the plasma, which is known as presputtering. The presputtering removed the contaminants on the target surface and gettered the absorbents on the chamber surface. The presputtering pressure is 5 mtorr, and the power is 100 W for 10 minutes. The sputter chamber pressure was then adjusted with the throttle valve to the deposition pressure. Oxygen was then introduced into the chamber, and the flow rate was adjusted for deposition with mass flow controller. Experiments were carried out at room temperature. The flow rates of argon and oxygen were 17 sccm and 1.90 sccm, respectively. The sputter pressure was 4.0 mtorr. The power of the high voltage cathode was kept at 35 W. Post deposition annealing was performed in a horizontal quartz furnace in nitrogen atmosphere. The furnace was preheated to the anneal temperature (600 and 720◦ C, respectively) and stabilized for several hours. This is necessary because the processed films are very thin. The films are heated up to the anneal temperature very quickly.
44
Figure 3.3: The sandwitch structure of a TEM sample 3.3 SAMPLE CHARACTERIZATION 3.3.1
Glancing angle X–ray diffraction
The crystallinity of hte films was studied using Phillips X’pert MPD X–ray diffractometer with a thin film attachment. The glancing angle was fixed at 1◦ , and the detector scan range was 20◦ to 60◦ . The step size was 0.02◦ . The system was operated at 45 kV and 40 mA.
3.3.2 Transmission electron microscope cross section image The TEM cross section images were studied in a Hitachi 8100 Scanning Transmission Electron Microscope. The sample was first glued and stacked with dummy silicon as shown in figure 3.3. The sandwitch was then rounded by grinding to remove the corners so that the sample could fit into the sample holder. It was then grinded, polished and dimpled to about 1µm thickness, and then thinned in an ion miller to a thickness which is transparent to the electron beam.
45 3.3.3 Chemical analysis The O/Hf ratio and the oxidation state of interfacial layer were studied using Kratos Axis Ultra–165 XPS system, with Al Kα (1486.6 eV) X–ray source. Soft sputtering, (operated at 4 kV and 15 mA for 25 minutes) was performed before the analysis to remove the surface contamination. The analysis is operated at around 10−8 torr.
3.3.4 Electrical measurements Metal–oxide–semiconductor capacitor (MOSCAP) devices as shown in fig 3.4 are prepared to perform the electrical measurements. Before electrode preparation, the samples were cleaned by acetone and iso-pronol alcohol (IPA) for 10 minutes, respectively, and followed by a D.I. water rinse. The top electrode material (Al, ∼ 300 nm) was deposited by thermal evaporation, and patterned by a photo mask process. The diameter of the aluminum dots is 40µm, with an area of 1.25×10−5 cm2 . To remove the residual photoresist, the backside of the silicon substrate was clean by plasma ashier. The back side electrode (Al, ∼ 300nm) was deposited by DC sputtering using an Al target (bought from Kurt J. Lesker, purity: 99.99%). The sputtering power was 150 W, and the pressure was 4.0 mtorr. Post metallization annealing was performed in forming gas (3 % H2 balanced by N2 ) at 450◦ C for 30 minutes. The MOSCAP were placed in probe station for measurement.
Current–voltage measurements The current–voltage (I–V) characteristics were measured with an HP 4145A Semiconductor Parameter Analyzer. The sweep range was +2 to −2 V, and the sweep step was 0.05 V. To study the reliability of the high–κ films, constant voltage stresses (−2.05 and
46
Figure 3.4: The schematic diagram of the DC magnetron reactive sputtering system −3.05 V, respectively) was applied to the MOSCAP for 1500 seconds.
Capacitance–voltage measurements The capacitance–voltage (C–V) characteristics were measured using an Agilent 4284 Precision LCR meter. The measurement frequency is fixed at 100 kHz. The sweep range was +1 to −2 V, and the sweep step was 0.05 V. To study the frequency dispersion of the MOSCAP, 10 kHz and 1 MHz measurements were also performed.
47 CHAPTER 4
THE STRUCTUREAL, COMPOSITIONAL AND INTERFACIAL CHARACTERIZATIONS OF HfO2 FILMS
4.1
X-RAY DIFFRACTION ANALYSIS
X-ray diffraction analysis was utilized to study the crystallinity of samples with various thicknesses. In addition to the as deposited sample, the samples were further annealed to study the thermal stability of the deposited HfO2 films. It is expected that the crystallization behavior varies with the process and condition of the films.
4.1.1 The XRD pattern of HfO2 films Figure 4.1 shows the XRD pattern of the samples with different thicknesses before and after annealing (600◦ C for 6 minutes and 720◦ C for 2 minutes). The figure shows that the as deposited samples are amorphous, regardless of the thickness of the film. Although a thickness dependence of crystallinity of films prepared by ALD at elevated temperatures was observed [72], the films deposited by reactive sputtering does not show this phenomenon. This is probably because our films are deposited at room temperature. At room temperature, mobility of sputtered atoms is limited, and the sputtered atoms do not move after arriving the substrate. Consequently, crystallization is inhibited, and all as sputtered films are amorphous. After annealing at 600◦ C for 6 minutes, the XRD pattern shows that the 5.8 nm film
48
t (2 1 1)
m
m
(h)
-
( 1 1 1)
(g)
m (1 1 0)
(1 1 1)
m
(0 2 0)
m
-
( 1 2 1)
m
(2 2 0)
(f)
(e)
(d) (c)
(b) (a)
20
30
40
50
60
70
2
Figure 4.1: The XRD pattern of HfO2 films: (a) as deposited (20 nm); (b) as deposited (5.8 nm); (c) annealed at 600◦ C for 6 minutes (22.4 nm); (d) annealed at 600◦ C for 6 minutes (11.2 nm); (e) annealed at 600◦ C for 6 minutes (5.8 nm); (f) annealed at 720◦ C for 2 minutes (20 nm); (g) annealed at 720◦ C for 2 minutes (10.8 nm); (h) annealed at 720◦ C for 2 minutes (5.8 nm). (m: monoclinic; t: tetragonal)
49 remains amorphous structure, but the 11.2 and 20 nm films both crystallize. It is interesting to note that the diffraction peaks of 20 nm sample are mostly the monoclinic phase, which is the stable phase of HfO2 at room temperature. The diffraction pattern of 11.2 nm sample shows significant intensity for the (211) diffraction of the high temperature phase of HfO2 ) at 2θ = 30.3◦ . With the background noise substrcted, the relative intensities of tetragonal (211) line to the monoclinic (111) line are 0.28 and 0.67 for 20 and 11.2 nm samples, respectively, which indicates more of the high temperature tetragonal phase exists in 11.2 nm thick sample than in 20 nm thick sample. For heat treatments performed at 720◦ C, diffraction peaks are present for all thicknesses of sample, which means all the samples have crystallized, regardless of thickness. The XRD pattern of the 5.8 nm sample shows pure tetragonal phase exists in this film. Nonetheless, both monoclinic and tetragonal phases exist in 11.2 and 20 nm samples. The relative intensitis of tetragonal (211) to the monoclinic (111) are 0.08 and 0.71 for 20 and 10.8 nm samples, respectively. The presence of monoclinic phase decreases significantly for the 20 nm sample, and increases only slightly for 10.8 nm sample as compared to the 600◦ C.
50
Figure 4.2: The energy of the HfO2 film 4.1.2 Discussion of crystallization behavior of HfO2 films The results of the XRD study clearly point out a thickness dependence of the crystallization temperature. The thicker films (11.2 and 20 nm) crystallize below 600◦ C, and thinner film (5.8 nm) crystallizes between 600◦ C and 720◦ C. It was also observed the crystalline phase depends on thickness. A higher percentage of the high temperature phase exists in the thinner film. This is more pronounced for the higher anneal temperature. The energy at room temperature of HfO2 film is shown schematically in figure 4.2. For bulk HfO2 , the stable phase is monoclinic at room temperature. Bulk HfO2 transforms to a tetragonal phase at 2000 K, and to a cubic phase at 2870 K. Above 3031 K, the HfO2 melts, and liquid phase is the stable phase.
51 The difference between the free energy per unit area of an amorphous HfO2 film and crystallized film can be written as: ∆G = ∆Gv × d + (∆γf s + ∆γf v ) + ∆²f s × d
(4.1)
where ∆Gv is the change in free energy per unit volume of the HfO2 on crystallization, d is the film thickness, ∆γf s is the change in surface tension of film with substrate on crystallization, ∆γf v is the change in surface tension of film with ambient on crystallization, and ∆²f s is the strain energy per unit area. As deposited thin films are usually stressed, but the state of stress is difficult to evaluate, and so the strain energy will not be discussed, except to note that it may be important. The driving force for the phase change includes the change in bulk free energy on crystallization as well as the change in interfacial free energies on crystallization. The amorphous HfO2 /SiO2 interfaces should have lower interface tensions than crystalline HfO2 /SiO2 interfaces, and this increase in surface tension during crystallization decreases the overall free energy for the transformation. The change in surface tension makes a greater contribution to the change in free energy during crystallization of the thinner films than thicker films. This retards the crystallization of the thinner films. Although figure 4.2 shows same driving force for HfO2 films with different thicknesses to crystallize, the experimental results show that the crystallization temperature depends on film thickness. This suggests that crystallization of HfO2 films is dominated by kinetics, i.e., the mobility of atoms. Figure 4.3 illustrates the movement of atoms within within films of different thickness. When thermal energy is applied, the atoms tend to migrate to another stable site in the random configuration. For the atoms in a thinner film as shown in figure 4.3 (a), the motion of the atoms at the top and the bottom of
52
Figure 4.3: Illustrating of the atomic mobility within films with different thickness: (a) thinner film; (b) thicker film. the film are constrained by the surface. The atoms with more freedom to move are those in the middle of the film. In thicker films, more atoms have increased mobility. Therefore, more atoms are involved in the transformation, and the phase transformation can proceed at a faster rate. This model, thus, explains why the crystallization temperature of 5.8 nm film is higher than 10 and 20 nm films. The 5.8 nm film is essentially a structure composed of 10 − 15 atomic layers of HfO2 , which means that the atoms only the few layers in the middle can migrate freely. This suggests that only a few atoms in the middle of the layer are involved in the nucleation. It is, therefore, more difficult to form stable nuclei larger than critical size. Because of the limited mobility of atoms at interface, nucleation relies on the motion of atoms in the middle of an ultra–thin film. The crystallization temperature of 5.8 nm HfO2 film is, therefore, higher than that of 20 and 10 nm films. It is well known that there are kinetic processes are involved in nucleation. Sometimes the most stable phase nucleates first, and sometimes a metastable phase nucleates and then transforms to the stable phase. And sometimes there are remnants of the intermediate phase and sometimes there are not. And this can be strongly affected by stresses in the
53 material, and by the state of the material in any adjacent layers. A lot of is this is very difficult to predict, because it is difficult to know a priori which kinetic process is likely to be fastest in a given situation. Our results as shown in fiugre 4.1 indicate that 5.8 nm film crystallized as pure tetragonal phase. The monoclinic phase is dominant in 20 nm film. For bulk HfO2 , monoclinic phase is the stable phase at both annealing temperatures (600 and 720◦ C). The dependence of crystallization phase on the film thickness can be explained in two ways. Thermodynamically, the phase transformation temperature may have been changed when HfO2 is as thin as 5.8 nm. So the HfO2 film shows a tetragonal structure after annealing. Kinetically, this suggests different reaction paths for HfO2 films with different thicknesses. For a 20 nm film, the atoms within the films have high mobility, which it easy to form the stable monoclinic phase. When the thickness is as thin as 5.8 nm, the atomic mobility is limited as mentioned above. The film tends to crystallize as metastable tetragonal phase during annealing. This also implies the reaction to form tetragonal phase during the annealing temperature is relatively easier. Figure 4.4 shows the relationship of free energy release to annealing temperature during heat treatment. When the annealing temperature is lower than the crystallization temperature, crystallization has not been initiated. Excess vacancies and interstitials in HfO2 films tend to migrate and annihilate in this stage. When the annealing temperature is higher than the crystallization temperature, larger atomic movement is allowed, and crystallization is triggered during heat treatment. Since thermodynamically the crystallization phase is preferred, more free energy is released during crystallization. This observation indicates that the activation energy for point defects annihilation is lower than
54
Figure 4.4: The dependence of energy release due to annealing on annealing temperature that for crystallization. Crystallization begins at a higher temperature as shown in figure 4.4. However, the completion of crystallization releases more energy than annihilation of point defects. The figure also shows that for thinner film, annihilation of point defects lasts for longer period.
55 4.2
TEM CROSS-SECTION STUDY
The cross section of HfO2 /Si interface was studied by TEM. The TEM images confirm the crystallinity results studied by XRD. The morphologies of interfacial layer are also revealed in the TEM images.
4.2.1
As deposited samples
Figure 4.5 (a) and (b) show the TEM images of the 20 and 5.8 nm as deposit samples, respectively. The TEM images show the both samples are amorphous, which confirms the result of XRD. Both images show a uniform interface with interfacial layer about 0.8 nm thick, regardless of the thickness of HfO2 films. Since the thermodynamics predicts that the HfO2 is stable in contact with Si [34], this indicates the interfacial layer is either the native oxide or formed during the deposition. When the deposition proceed for longer time, more oxygen is introduced, but the interfacial layer does not grow thicker.
56
Figure 4.5: The TEM cross section image of as deposited samples: (a) 5.8 nm; (b) 20 nm
57 4.2.2 The effect of heat treatment Figures 4.6 (a) and (b) show TEM imagees of the 5.8 nm thick samples after annealing at 600◦ C for 6 minutes, and 720◦ C for 2 minutes, respectively. The TEM pictures show that the films remain amorphous after annealing at 600◦ C. For the sample annealed at 720◦ C, the presence of the atomic fringes in the film area indicates that the film has crystallized, confirming the result of XRD. The growth of the interfacial layer depends on the anneal temperature. The interfacial layer of sample annealed at 600◦ C is about 1 nm, wherereas it is about 1.47 nm after annealed at 720◦ C. The source of oxygen for this growth may be either from the ambient or excess oxygen in the HfO2 film.
58
Figure 4.6: The TEM cross section images of the 5.8 nm sample annealed at: (a) 600◦ C for 6 minutes and (b) 720◦ C for 2 minutes
59 4.3
COMPOSITION ANALYSIS
4.3.1 Surface analysis The XPS was utilized to study the surface composition of the HfO2 films. It is known that surface contamination, e.g., hydrocarbon, from the ambient is usually observed. To avoid the interference from surface contamination, soft sputtering (operated at 4 kV and 15 mA for 25 minutes) was applied before the analysis. The XP spectras of C1s peak (centered at 284.6 eV) before and after soft sputtering are illustrated in figure 4.7. The figure clearly shows that the carbon peak disappears entirely after the soft sputtering. It indicates that the carbon contamination is merely on the surface, and can be removed by soft sputtering. The film is, therefore, free of hydrocarbon contamination. It has been shown that the chlorine is present in ZrO2 and HfO2 films prepared by ALD [73], when chlorides are used as the precursors. For reactive sputtering, the reactants involved in the process are sputtered hafnium atoms and the oxygen. The film is expected to be without other species. The result also indicates that the sputtering chamber is clean, and the entire preparation process is under control. Figure 4.8 shows the X–ray photoelectron spectras of O1s as well as Hf4f , which are the signals we used for the calculation of the O/Hf stoichiometric ratio, before and after soft sputtering. The interference from hydrocarbon contamination to the signals is clearly observed in the figure. When hydrocarbon contamination exists, both the peak positions and intensities are influenced. The peak intensities of both Hf4f and O1s are reduced due to the blocking effect of hydrocarbon contamination. It is interesting to note the original peak of O1s . A shoulder is present at the high energy side. This result clearly indicates the hydrocarbon contaminats bond with the dangling bonds on the surface. Once the
60
C
1s
Before sputtering
After sputtering
300
295
290
285
280
275
Binding Energy (eV)
Figure 4.7: The X-ray photoelectron spectra of C1s before and after soft sputtering (operated at 4 kV and 15 mA for 25 minutes)
61
sputtering sputtering
Before
t
Af er
26
24
Hf 4f
22
20
18
16
sputtering sputtering
Before
t
Af er
540
538
536
O 1s
534
532
530
528
526
Binding Energy (eV)
Figure 4.8: The XP spectras of O1s and Hf4f before and after sputtering to remove surface contamination (peak position is not calibrated). The interference of hydrocarbon contamination to the signals is clearly observed. contamination is removed by sputtering, the C–O bonds are not present on the surface, and the shoulder disappears. Additionally, the nucleis of hafnium and oxygen pull the valence electrons tighter after the surface contamination is removed, and therefore, the binding energies shift toward higher energies. Figure 4.9 shows Hf4f XP spectra, calibrated by C1s (centered at 284.6 eV) for the as deposited sample. The XP spectra consist of a 4f7/2 − 4f5/2 component. The figure shows the binding energy of 4f7/2 peak is centered at 17.40 eV, and the 4f7/2 − 4f5/2 spin–orbit
62
4
17. 7 eV
Hf 4f
6
1. 7 eV
4f
2
7/
4f
2
5/
24
22
20
18
16
14
12
Binding Energy (eV)
Figure 4.9: The X-ray photoelectron spectra of as deposited HfO2 film. splitting value is 1.67 eV, which are the characteristics of fully oxidized Hf4+ peak [74]. The calculation shows the O/Hf ratio is 2.3 ± 0.2, which is higher than the ideal ratio.
63 4.3.2 Interface chemistry analysis Interface chemistry was analyzed by studying the 5.8 nm samples. The escape depth of ˚ Before analysis, the film was sputtered at 4 kV for X–ray photoelectrons is about 50 A. 35 minutes to remove surface contamination. The sample thickness is appropriate for interface analysis, so the signal from the interface can be detected. Figure 4.10 illustrates the interface spectra of Hf4f for the samples before and after annealing. The peak position as well as the 4f7/2 − 4f5/2 separation is not altered by heat treatment. No new peak appears at the low energy side, which means no silicide has formed during the heat treatment. In the study of Kirsch et al., when a hafnium layer was deposited before the preparation of HfO2 , the Hf–O reaction competes with the Hf–Si reaction, since metallic Hf is directly in contact with Si [75]. Muraoka’s research points out that silicide formation takes place, when the poly-Si/ZrO2 /Si structure is annealed [76]. Because the ZrO2 /Si is embedded in an oxygen-deficient environment, the annealing generates volatile SiO, and triggers silicide formation. In both studies, an interfacial layer (either metallic or oxide) is involved in the reaction. Instead, our result indicates that silicide does not form at interface. When the HfO2 is deposited on silicon, the oxide is directly in contact with Si. Thermodynamics predict that the the Hf–Si reaction is unlikely to happen [34]. Additionally, our surface analysis shows there is an excess of oxygen in the film. The ambient can also introduce traceable amounts of oxygen into the film. So the HfO2 /Si interface is not in an oxygen–deficient environment. Thus, silicide formation does not occur in our samples even during heat treatment. Figure 4.11 shows the core–level spectra of Si2p as well as O1s . Both Si2p and O2p signals contain a shoulder on the high energy side. Lorentzian–Gaussian deconvolution
64
f4f
17.4 eV
H
1.67 eV
0
Anneal at 72
4f
7/2
4f5 24
22
20
/2
Anneal at
600
o
o
C
C
As deposit
18
16
14
12
Binding Energy (eV)
Figure 4.10: The interface XP spectra of Hf4f before and after annealing
65
Si
99.2 eV
O
Hf-O
2p
1s
4.2 eV
Anneal at 720
o
C Anneal at 720
3.1 eV
o
C
Si-O
Anneal at 600
Anneal at 600
o
o
C
C
As deposit As deposit
108 106 104 102 100 98
96
94
Binding Energy (eV)
92
90
540
535
530
525
520
Binding Energy (eV)
Figure 4.11: The XP spectras of Si2p and O1s at HfO2 /Si interface was used to analyze the signal. For the as deposited film, the curve fitting indicate that Si2p spectra can be deconvoluted into five components. The primary peak centered at 99.2 eV is the signal of silicon from silicon substrate. The three peaks on the high energy side (> 101 eV) are Six+ signals from the interfacial layer. The peak with a separation of 4.2 eV from the primary Si peak, centered at 103.4 eV, is a typical Si4+ signal. The Si4+ peak at 99.2 eV is the dominant peak in the spectrum. The other two peaks ON the high energy side are silicon suboxide Six+ signals, which indicate the existence of Si–O–Hf bonds. The O1s peak was deconvoluted into two peaks: the peak centered at 531.7 eV (the signal of an Hf–O bond),
66 and the shoulder at the high energy side is (Si–O bond). The peak centered at 532.41 eV is from the interface. The peak position is, indeed, slightly lower than than Si–O bond (typically centered at 533.7 eV) [75]. This discrepancy from the usual value suggests the existence of the sub–oxidized Six+ , which agrees with the results of Si2p analysis. This suggests the presence of hafnium atoms in the interfacial layer or a Hf–poor silicate [29], that is, the existence of Si–O–Hf bonds. These XPS results suggest that the interface layer is composed of a silicon–rich silicate. In the Si2p signals, the silicon suboxide signals of lowest energy tend to decrease intensity after annealing at 600◦ C, and to disappear after annealing at 720◦ C. The peaks with a separation of 3.1 eV from the metallic silicon peak intensify, and move toward higher energy after annealing. This suggests that the sub–oxidized silicon tends to become to more fully oxidized during annealing. After annealing, the shoulder on the high energy side of the O1s spectrum move toward higher energy, and the area of the Si–O curve decreases. This implies the dominance of the Hf–O bonding, and that the silicate at interface separates into HfO2 + SiO2 . The interface layer is converted to a silica–like layer.
67 4.3.3 Discussion of the interface reaction Figure 4.12 illustrates a model of interfacial layer formation during preparation and interfacial reaction during heat treatment. In the beginning of the deposition, the atoms hit the substrate and transfer their kinetic energy to silicon substrate. Provided the experimental parameters are proper, the arriving atoms do not damage the substrate. Instead, these atoms can modify the substrate surface. As shown in the results of XPS analysis, the primary composition of interface layer of the as deposited film is a silicon–rich silicate. However, thermodynamics predicts the reaction of HfO2 and silicon is not spontaneous, and our HfO2 films were prepared at the room temperature. Therefore, the formation of a silicate layer should not be the result of the chemical reaction of HfO2 and Si. Instead, it is more likely that the hafnium atoms or Hf–O molecules with proper kinetic energy are incorporated into the native oxide formed before the HfO2 layer was deposited. This result implies our sputter conditions were well adjusted. When the HfO2 films are annealed, the XPS results show that the silicate layer tends to segregate, that is, the silicate layer transforms to HfO2 + SiO2 . This result suggests that the hafnium atoms tend to out–diffuse to join the top HfO2 layer. This would predict that the interfacial layer shrinks during annealing. However, the TEM analysis shows that interfacial layer grows during annealing. This indicates that there is an interfacial reaction which takes place below the original interface during annealing. The XPS surface analysis shows that there is an excess of oxygen in the HfO2 film. In addition, although the heat treatment is performed in an N2 atmosphere, the ambient contains trace amounts of oxygen. The oxygen in the ambient or the excess oxygen within the film can diffuse
68 into the silicon substrate, and react with silicon. The reaction, therefore, results in the formation of silica–like layer. The newly formed interface layer is more like the SiO2 prepared by thermal oxidation. Essentially, it provides better interface quality, which will be shown in the electrical measurement results. When the HfO2 is annealed at 720◦ C, the interfacial layer grows thicker than during the anneal at 600◦ C. Obviously, the diffusivity of oxygen in HfO2 and the Si–O reaction rate will increase with the increase in temperature. In addition, the presence of the grain boundaries may also be a factor. The grain boundaries provide an easy path for oxygen transport, which results in more oxygen arriving at silicon substrate. The interfacial layer, thus, grows thicker as a result of the presence of more reacting species.
69
Figure 4.12: The interface reaction of HfO2 /silicate/Si: (a) during deposition; (b) during annealing.
70 4.4
SUMMARY
The structural analyses (glancing angle XRD and TEM cross section) show that the as deposited films are amorphous structure with interfacial layers of 0.8 nm, regardless of the film thickness. The compositional study indicates that the deposited HfO2 films are fully oxidized and free of contamination from other elements, e.g. hydrocarbon. The O/Hf ratio is larger than the ideal value, 2. The interface chemistry analysis performed by X–ray photoelectron spectroscopy shows that the constituent of interfacial layer is a silicon–rich silicate, HfSix Oy . When the films are annealed at 600◦ C, the crystallinity of 5.8 nm film does not alter, and these films remain amorphous. The thicker samples (10 nm and 20 nm) crystallize, and are composed of the monoclinic and tetragonal phases. The interfacial laye grows to 1.0 nm during the heat treatment. After annealing at 720◦ C, all the films have crystallized, and the interfacial layer thickness grows to 1.47 nm. The composition of interfacial layer changes to a silica-like layer after this heat treatment.
71 CHAPTER 5
THE ELECTRICAL PROPERTIES OF HfO2 FILMS
Current–voltage (I–V) and capacitance–voltage (C–V) characteristics of deposited HfO2 films are discussed in this chapter. The electrical properties of HfO2 films annealed at different temperature are compared to as deposited films to study the influence of heat treatment. MOS diodes were stressed at different voltages for up to 1500 seconds to characterize the reliability of the HfO2 films. The aging test is performed by placing the sample in the ambient for one month. The electrical properties were measured afterward to investigate the aging effect.
5.1
CURRENT–VOLTAGE (I–V) CHARACTERISTIC
5.1.1 The I–V characteristic of ultra–thin (5.8 nm) HfO2 film Figure 5.1 shows the VG vs. |JG | plot of 5.8 nm HfO2 films before and after annealing. The leakage current density of HfO2 films before and after annealing at VG = −1.5 V are summarized in table 5.1. The leakage current density of the as deposited HfO2 film is of the order of 10−3 A/cm2 . After annealing at 600◦ C, the leakage current density decreases by about four orders of magnitude. When the film was annealed at 700◦ C, the film crystallized as shown by the XRD analysis. The leakage current density at VG = −1.5 V increased in the crystallized films by about one order of magnitude. This result clearly shows a strong influence of annealing on the leakage current density.
72
0
10
A
s
osit l t 600 oC or 6 i l t 20 oC or 2 i
dep
ed
Annea a
-2
10
Annea a
7
f
m n
f
m n
-4
|JG|
2
(A/cm )
10
-6
10
-8
10
-10
10
-12
10
-2
-1
0
1
2
VG Volts) (
Figure 5.1: The VG vs. |JG | plot of 5.8 nm HfO2 film before and after heat treatment
Sample |JG | (A/cm2 )
As deposited 3.41 × 10−3
Annealed at 600◦ C 9.11 × 10−7
Annealed at 720◦ C 2.21 × 10−2
Table 5.1: The leakage current density of a an Al/5.8 nm–HfO2 /Si MOS diode @ VG = −1.5 V before and after heat treatment.
73 Figure 5.2 illustrates Schottky as well as Frenkel–Poole plots. A VG – |JG | plot shows significant changes for the films before and after heat treatment, but the effective filed applied to the gate oxide is different due to a variation of flat band voltage as shown in C–V measurements in a later section. And consequently, the VG has to be adjusted by subtracting Vf b from VG as the conduction behavior of the gate oxide is investigated. The effective field, Eef f , is given by ¯ ¯ ¯ VG − Vf b ¯ ¯ |Eef f | = ¯¯ tox ¯
(5.1)
The figure clearly indicates that again the leakage current density increases after anneal at 720◦ C and decreases after anneal at 600◦ C at the same effective filed. The figure also shows for the as deposited, and film anneal at 720◦ C, that Schottky emission dominates in the low field region (0.26 − 1.70 MV/cm), and Frenkel-Poole emission dominates in the high field region (1.79 − 2.68 MV/cm). When effective field, Eef f , is 1.33 − 2.10 MV/cm, the data points are slightly off the fitting line, which specifies the transition region from Schottky to Frenkel-Poole emission. However, the film annealed at 600◦ C shows different conduction behavior. Schottky emission dominates throughout the entire measurement range.
74
-6
0
10
10
As deposited -1
10
Anneal at 600 Anneal at 720
o
o
Transition C C
2
Schottky -3
emission
-4
-8
10
10
(A/V cm)
10
eff
G
-7
10
E
|J | (A/cm )
emission
JG/
Frenkel-Poole
-2
10
-5
10
-6
10
400
-9
600
800
1000
E
1200 eff
1400
1600
1800
10 2000
V cm
Figure 5.2: Schottky and Frenkel–Poole plots for the films before and after annealing
75 5.1.2 Discussion of the conduction behavior of HfO2 films It has been shown that the interface layer becomes Si-rich silicate, which has a larger conduction band offset [40]. Besides, the thicker interfacial layer decreases the effective field, and furthermore, the tunneling probability. Therefore, in the direct tunneling regime, the interface reaction results in a decrease of tunneling probability and, consequently, a decrease of leakage current density. However, as shown in figure 5.2, the conduction mechanism of our HfO2 films is either Schottky or Frenkel–Poole emission. In the low field region, Schottky emission dominates. The variation of leakage current density has to be accomplished by modifying the barrier height of injecting interface. In the high field region, the Frenkel–Poole emission dominates. The mechanism is determined by barrier height as well as the number of traps. The barrier height φB is lowered due to the presence of the applied field and the oxide charge by ∆φB , know as image force, which is given as [78] Z xm 2q q ∆φB = + x0 n0 (x0 )dx0 16π²i xm ²ox 0
(5.2)
where ²i is the image force permittivity, xm is the barrier height position with respect to the emitter surface as shown in figure 5.3, and n0 (x0 ) is the charge density. The first term at the right hand side denotes the applied field effect, and the second term the oxide charge effect. Sputtered films are known to have a porous and defective structure with many charged point defects. The existence of these charged point defects will enhance the barrier lowering effect, and decrease the effective barrier height. As a result, the as deposited films show high leakage due to the presence of charged point defects. Additionally, the XPS analysis shows there are excess of oxygen in the HfO2 film,
76 which means that the oxygen interstitials exist in the HfO2 film. The reactive sputtering performed at room temperature is known to prepare films with low density; that is, the number of vacancies is higher than equilibrium. Since these point defects (interstitials and vacancies) may serve as the electron and hole traps at the HfO2 conduction band [79], these defects behave as Frenkel–Poole emission centers, which increases the trapping and emission probablities of the charges at higher fields. As the film is annealed, the vacancies and interstitials have a very high tendency to migrate and annihilate to decrease the free energy. The decrease of point defect density ameliorates the barrier lowering effect, and decreases the number of trapping sites. Both of these decrease the number of emission charges, and result in lower leakage current density. It is worth noting that for the film anneal at 600◦ C, the Schottky emission, which has lower field dependence, dominates at entire sweep range. It suggests the trapping effects do not play an important role, and the film conduction relies on the thermonic emission of electrons from the electrode. That implies the traps with shallow barrier height are mostly removed by the heat treatment. When the film is annealed at 720◦ C, the film crystallizes and grain boundaries are present as shown in XRD and TEM analysis. The interface chemistry study shows the the interfacial layer becomes silica–like layer, which has a high band offset. The TEM analysis also shows that the growth of interfacial layer is larger than during the anneal at 600◦ C. The variation of interface properties (chemistry and morphology) suggests that the leakage current density should decrease. However, the oxide shows a large increase in conduction. This clearly indicates that the interfacial effect is overwhelmed by the crystallinity. In the films which crystallized during the anneal, grain boundaries are
77 present. These 2–D planar defects are the mismatch planes of different grains. Abundant of dangling bonds and charges are usually present on these planar defects in ionic solids. The grain boundaries tend to be chemically active. Since the charge density along grain boundary is higher than in the grains, the barrier lowering effect is enhanced locally at grain boundaries. In the region of the grain boundaries, the Schottky emission probability is higher in the low field regime. In addition, defects tend to segregate to grain boundaries. The local trap density is, thus, higher at grain boundaries. In the high field regime, charge trapping and emission activity are more probable at grain boundaries than within the grains and amorphous films. At elevated temperatures, the open structure of grain boundaries increase the diffusivity. Similarly, charge mobility is enhanced and carriers migrate more rapidly within grain boundaries under the applied electric field due to the larger mean free path. For 5.8 nm film, the film morphology is the bamboo structure, in which a grain boundary line connects the electrode and the substrate. Thus, the grain boundaries provide a shortcut for the transport of charges through the oxide. In summary, the leakage current density is controlled by the interface (morphology and chemistry) and bulk (point defect density and crystallinity) properties of the film. If the film retains an amorphous structure, the interface properties and the point defect density determine the leakage current density. If the film crystallized during the anneal, the grain boundaries are present within the film. The existence of grain boundaries not only increases the charge trapping and emission probability, but also provides an easy conduction path for the charges. Therefore, if the film crystallizes during the anneal, the leakage current density increases sharply. The ease of charge emission and charge
78
Figure 5.3: The barrier lowering effect of image potential transport in the grain boundaries results in the high conductivity of crystallized films.
79 5.1.3 The comparison with ZrO2 Figure 5.4 shows the comparison of I-V characteristic of ZrO2 and HfO2 with comparable physical thickness. As summarized in table 5.2, the leakage current density of ZrO2 at VG = −1.5 V is two orders of magnitude higher than the as deposited HfO2 film, and one order of magnitude higher than the crystallized HfO2 film. The result shows a remarkable difference of these two oxides. The difference may result from the higher defect density within the ZrO2 film. It may also be due to the larger conduction band offset of HfO2 (34 %) [40]. The results show that ZrO2 is not an appropriate substitute as high–κ gate dielectric due to its high leaky property. Sample |JG | (A/cm2 )
As deposited HfO2 3.41 × 10−3
Crystallized HfO2 2.21 × 10−2
ZrO2 0.759
Table 5.2: The leakage current density of a Al/5.8 nm–HfO2 /Si and Al/5.8 nm–ZrO2 /Si MOS diode @ VG = −1.5 V.
80
2
10
As deposited HfO
2
0
(5.8 nm)
Crystallized HfO
10
2
As deposited ZrO
2
(5.6 nm)
-2
|JG|
2
(A/cm )
10
-4
10
-6
10
-8
10
-10
10
-2
-1
0
1
2
V
G (Volts)
Figure 5.4: Comparison of I–V characteristic of ZrO2 and HfO2 with comparable physical thickness. The sputter conditions of ZrO2 are: power – 40 W; Ar flow rate – 18.0 sccm; O2 flow rate – 1.90 sccm.
81
orward sweep ers o to a Ba ward sweep a lat o to F
2000
(inv
i
n
lat o
ccumu
ck
( ccumu
n
eas red at 100
1500
M
2
C/A (nF/cm )
i
u
i
n)
ers o
inv
i
n)
kHz
1000
500
0 -3
-2
-1
0
VG Volts)
1
2
(
Figure 5.5: The C-V characteristic of an Al/as deposited–5.8 nm HfO2 /Si MOS diode. 5.2
CAPACITANCE-VOLTAGE (C-V) CHARACTERISTIC
5.2.1 The C-V characteristic of as deposited HfO2 films and parameter extraction The C-V characteristic of the as deposit film (5.8 nm) is shown in figure 5.5. The measurement was performed by sweeping from inversion to accumulation region (+VG to -VG ). The backward sweep (accumulation to inversion, -VG to +VG ) was performed immediately to study the hystersis effect. The figure illustrates typical C–V curve with negligible hystersis. At VG < 0, the majority carriers are attracted to the HfO2 /Si interface, and thus, form the accumulation at the very negative VG region. The relative permittivity, ²r , of the HfO2 /interfacial layer
82 stack obtained from the maximum capacitance, Cmax , is 15, which gives EOT = 1.66 nm. Nonetheless, the entire stack can be viewed as two capacitors are in series combination (HfO2 and interfacial layer). Therefore, the maximum capacitance obtained by the C–V measurement is 1 Cmax
=
1 CHf O2
+
1 1 1 = + CIL ²0 ²r dHfAO ²0 ²IL dAIL
(5.3)
2
where ²o is the vacuum permittivity, Cmax is the maximum capacitance obtained from the measurement, A is the area of aluminum dots (1.25 × 10−5 cm2 ), dHf O2 is the thickness of HfO2 layer, and dIL is the thickness of interfacial layer. The thicknesses of HfO2 and interfacial layers are evaluated from TEM images. The relative permittivity of HfO2 and interfacial layers can, therefore, be determined by introducing the measured Cmax values of different thickness [39], which gives ²Hf O2 = 19.44 and ²IL = 5.53. The evaluation shows the interfacial layer is a silicon–rich silicate [80], which is similiar to the result of Park [39]. This evaluation confirms our result of XPS interface chemistry analysis. The minimum capacitance, Cmin , as we mentioned in chapter 2, is the series combination of oxide and depletion layer, in which the depletion layer reaches the maximum thickness given by
s WT =
4²0 ²Si kT ln(NA /ni ) q 2 NA
(5.4)
Since the maximum depletion width is determined from Cmin , the substrate doping concentration, NA , can be extracted, which gives 3.62 × 1016 cm−3 . The substrate doping information can, in turn, determine the Debye length (equation 2.3) and the flat band capacitance (equation 2.4), which are 2.15µm, and 4.92 pF, respectively. The shift of flat band voltage, ∆Vf b , is, then, determined to be 465.83 mV from the C–V curve.
83 The hystersis at flat band is −11.76 mV. The existence of this hystersis effect is attributed to charge trapping. As the voltage is swept from positive to negative, the voltage reaches the maximum at accumulation. Holes tunnel from channel to the gate [31]. Some tunnel holes are trapped by the defects within the film, and these trapped charges do not return to the equilibrium positions [82, 83]. As the gate voltage sweeps from negative to positive voltage, the C–V curve shifts toward negative side as shown in the figure. Figure 5.6 shows the frequency dispersion of the as deposited 5.8 nm film. The Al/HfO2 /Si MOS diode was measured at 10, 100 and 1MHz. The figure clearly shows the strong frequency dependence of C–V characteristic. The position of C–V curve, value of Cmax , and slope of depletion region all vary as the Al/HfO2 /Si MOS diode was measured at different frequencies. As we have shown in the previous section, the sputtered films are defective and porous, containing many point defects, which may serve as electron and hole traps. These defects tend to trap charges from the leakage current. When the measurement is performed at high frequency (1 MHz), these traps are unable to response to the AC signal, and the detrapping of the trapped charges can not be completed. The trapped charges therefore, stay in the HfO2 films, and shift the C–V curve. Additionally, the negative shift suggests that the holes are trapped within the HfO2 film. That implies the defects within the HfO2 film are mostly neutral vacancies, which merely serve as hole traps. Other defects (charged vacancies and interstitials) have a higher tendency to trap electrons as we judge from their relaxed electron and hole affinities at point defects [84]. The influence of series and parallel resistance is more significant as the gate oxide thickness is scaled down. For high leakage films, the parallel resistance, which is a fre-
84
3000 10 kHz 100 kHz
2500
1 MHz
2
C/A (nF/cm )
2000
1500
1000
500
0 -5
-4
-3
-2
-1
VG Volts)
0
1
2
3
(
Figure 5.6: The frequency dispersion of an Al/as deposited–5.8 nm HfO2 /Si MOS diode.
85 quency dependent term, plays a more important role. Due to the existence of the parallel resistance, the measured maximum capacitance is less than the real value. The variation in oxide capacitance is, thus, because of the parallel resistance [85]. The percentage error in oxide capacitance is reduced to 11.79 % after considering the parallel resistance. The significance of the parallel resistance implies a high leakage of the HfO2 film, which is observed in I–V measurements. The stretchout of the high–frequency C–V curve is an abnormal phenomenon. The slope in depletion is expected to be larger when measured at higher frequency due to the elimination of the interface trap effect. This is usually how interface state density is evaluated by Terman’s method [86]. However, the C–V curve shown in the figure indicates the stretchout is more distinct when the measurement frequency is 1 MHz. This suggests that another mysterious interface capacitance, which will be discussed in a later section, is activated at higher frequency. The interface capacitance is in parallel with the silicon capacitance, and contributes to the MOS capacitance. This results in the stretchout of the C–V curve. The existence complicates the interface analysis, and the interface state density can not be evaluated. In summary, the Al/as deposited–5.8 nm HfO2 /Si MOS diode is strongly frequency dependent. The existences of defects, parallel resistance and a mysterious interface capacitance result in a large frequency dispersion.
86 5.2.2 The effects of annealing Figure 5.7 shows the C–V characteristics of HfO2 films measured at 100 kHz before and after anneals at different temperatures. The changes of EOT and Vf b are summarized in table 5.3. As shown in the figure, the maximum capacitance, Cmax , decreases after annealing, which means that the EOT of the oxide stack increases. In a previous chapter, it has been observed an interfacial layer grows during annealing. Furthermore, the interfacial chemistry analysis indicates that, during the heat treatment, the interfacial layer is converted to a silica–like layer, which has a lower κ–value. The growth of the interfacial layer and the interface chemistry conversion result in a reduction of the interfacial layer capacitance. Although the κ–value of the HfO2 layer may increase after annealing, this effect is obviously overwhelmed by the change of the interfacial layer. Sample EOT Vf b
As deposited 1.66 −0.55
Annealed at 720◦ C 2.22 −1.33
Annealed at 600◦ C 2.30 −1.27
Table 5.3: The changes of EOT and Vf b after heat treatment
When the film was annealed at 720◦ C, the capacitance density drops before accumulation. It was mentioned previously that the film crystallizes during annealing at 720◦ C. The leakage current density increases due to the presence of grain boundaries. The phenomenon is, therefore, ascribed to a grain boundary effect. When the grain boundaries are present, the oxide becomes too leaky to hold the charges at both sides of the oxide. When VG is very negative, the charges are transported by the electric field, and consequently, the C–V characteristic behaves abnormally. It is interesting to note that the flat band voltages of annealed films shift from positive
87
s
a
2000
C
Anne
7
C
t 100
ed a
kHz
2
C/A (nF/cm )
Mea
ed
6
sur
1500
osit l t 00 o o al at 20
dep
Annea a
1000
500
0 -4
-3
-2
-1
VG Volts)
0
1
2
(
Figure 5.7: The C-V characteristic of Al/as deposited–5.8 nm HfO2 /Si MOS diodes before and after annealing. The heat treatments were performed at 600◦ C for 6 minutes, and 720◦ C for 2 minutes, respectively.
88 to negative. Obviously, the net oxide charge variation suggests the generation of positive charges. The already–existing negative charges are compensated by these positive charges. Furthermore, the net charge of the HfO2 film becomes positive. The variation of charge type after heat treatment was also observed in the study of ZrO2 . It was pointed out by Houssa et. al. [87] that the positive charges are the overcoordinated oxygen centers induced by hydrogen, i.e., [Si2 =OH]+ and/or [Zr2 =OH]+ . In this mechanism, the water dissociates at the surface of ZrO2 . The products of water dissociation stay on the film surface or are adsorbed afterward. During the postmetallization annealing, the hydrogen atoms can not escape from the film due to the coverage of the metal layer. The generation of overcoordinated oxygen centers is then triggered by these hydrogen atoms. Due to the similarity of HfO2 and ZrO2 , we propose that the negative shift of flat band voltage is because of the generation of [Hf2 =OH]+ . Figure 5.8 illustrates the C–V curves of the films with different thicknesses annealed at 600 and 720◦ C. Both the anneal temperature and the film thickness dependence are observed in the figure. The thickness dependence of the position may suggest that the water–related species are present on the surface of the film. Therefore, even after the reaction is triggered, those overcoordinated oxygen centers are merely on the surface, and do not play an important role of the shift of Vf b for thicker films. The temperature dependence can be explained by a more complete dissociation of water when the heat treatment is performed at a higher temperature. Therefore, when less water–related species are available on the surface, the generation of the overcoordinated oxygen centers is limited, which results in a smaller shift of C–V curve. Figure 5.9 shows the frequency dispersion of an HfO2 film annealed at 600◦ C for 6
89
1600
1600 5.8 nm
5.8 nm
10 nm
10 nm
20 nm
1400
20 nm
1400
Measured at 100 kHz
Measured at 100 kHz
1200
1200 o
Annealed at 720
C
C/A (nF/cm )
1000
o
C
1000
2
2
C/A (nF/cm )
Annealed at 600
800
600
800
600
400
400
200
200
0
0 -4
-2
0
V
G
(Volts)
2
-4
-2
0
V
G
2
(Volts)
Figure 5.8: The C-V characteristic of Al/as deposited–5.8 nm HfO2 /Si MOS diodes with different thicknesses of HfO2 films, annealed at 600◦ C and 720◦ C
90
2000 10 kHz 100 kHz 1 MHz
2
C/A (nF/cm )
1500
1000
500
0 -4
-3
-2
-1
VG Volts)
0
1
(
Figure 5.9: The frequency dispersion of an HfO2 film annealed at 600◦ C for 6 minutes. The measurement frequencies were 10 k, 100 k, and 1 MHz, respectively. minutes. The dispersion of Cmax is 1.63% after correction for the parallel resistance [85]. The reduced dispersion in capacitance dispersion suggests that the parallel resistance is less important. The HfO2 film is, therefore, closer to an ideal capacitor, which is an open circuit. The leakage current density is expected to be reduced as was observed in I–V measurements. The deviation in the depletion region due to variations in frequency, as indicated in the figure, is greatly enhanced, as compared with the as deposited film. This implies that the defects within the oxide are mostly removed by annealing. The number of trapped charges decreased. As the measurement frequency is increased, the trapped charge effect
91 decreases, and there is no variation in the depletion region. The stretchout of the C–V curve when the measurement was performed at 1 MHz does not appear in figure 5.9. This means that the mysterious interface capacitance which we observed in as deposited HfO2 films is not present, which suggests that it can be eliminated by the heat treatment. As discussed in the interface chemistry analysis, the HfO2 /Si interface becomes a silica–like layer by the reaction of oxygen in–diffusion and the first few layers of silicon substrate. The C–V measurement shows that as the new interfacial layer is formed, the stretchout at high frequency disappears, which implies that the formation of a new interfacial layer removes the mysterious interfacial capacitance. This suggests that the stretchout at high frequency observed in the as deposited film results from the first few layers of the silicon atoms which are consumed by interfacial reaction. We suggest that, because the first few layers are damaged by the sputtered atoms, the defect density in these few layers is higher than in the silicon substrate. When the test frequency is so high that these trapped charges can not respond to the AC signal, most of the trapped charges can not go back to equilibrium positions. These remnant charges stay at the HfO2 /Si interface, and change the surface potential at high frequency. This damaged silicon layer then becomes a capacitor, which results in the stretchout at high frequency. Once this damage layer is removed by the interfacial reaction, the high frequency stretchout disappears. The experimental result also shows that the capacitance resulting from the damage silicon layer is more significant than interface traps. In a previous section, we characterized the relative permittivity of HfO2 and the interfacial layer by introducing the Cox value obtained from samples with different thicknesses.
92 However, as shown in XRD analysis, the crystal structures of HfO2 films vary with thickness after heat treatment. The dielectric constant of the HfO2 and interfacial layer can not be evaluated in the same way.
93 5.2.3 The influence of sputter pressure The influence of the pressure during sputtering to the C–V characteristic is illustrated in figure 5.10. The figure clearly indicates that the transition region is seriously distorted when the film is deposited at a lower pressure. This result suggests a poor interface condition. When the HfO2 films are prepared at lower pressure, the sputtered atoms undergo less scattering with ambient molecules before arriving at the silicon substrate, and therefore, possess higher kinetic energy. When the sputtered atoms arrive the substrate, this kinetic energy is transferred to the substrate. Ifr the sputter conditions are not properly, the sputtered atoms with high kinetic energy profuce radiation damage of the interface. This radiation damage results in an inconsistence of the surface potential as the gate voltage is swept. The C–V curve, therefore, shows an irregular behavior.
94
p = 4.0 mtorr
1.0
p = 1.2 mtorr Measured at 100 kHz
C/C
ox
0.8
0.6
0.4
0.2
0.0 -3.0
-2.5
-2.0
-1.5
-1.0
-0.5
VG Volts)
0.0
0.5
1.0
1.5
(
Figure 5.10: The influence of sputter pressure to the C–V characteristic (sputter power: 35 W; O2 flow rate: 1.85 sccm; Ar flow rate: 17 sccm)
95 5.2.4 Circuit model of an Al/HfO2 /Si MOS diode To conclude this section, we propose an equivalent circuit model of our Al/HfO2 /Si MOS diode as shown in figure 5.11 for different measurement conditions. The equivalent circuit of MOS diode with as deposited HfO2 film is shown in figure 5.11 (a). The circuit includes four capacitors. The silicon capacitance contains the depletion layer, the interface traps and the damage silicon layer capacitors. This series set is in series with oxide capacitor. The capacitance of the MOS is, therefore, given by 1 1 1 = + C Cox CD + Cit + CDS
(5.5)
where Cox is the oxide capacitance, CD is the capacitance of the depletion layer, Cit is the interface trap capacitance, and CDS is the capacitance of damaged silicon layer. Due to the high leakage characteristic, a parallel resistance needs to be included, which is in parallel with the capacitor set, including all four capacitors. The series resistance resulting from the measurement set up and the substrate, such as the back side contact and probe resistance is, in turn, in series with the entire capacitor and parallel resistance set. The most common observed problem is backside contact resistance, which is related to process. Although the substrate has been clean carefully before the preparation of backside electrode, it is not guaranteed the backside silicon is free from the contamination from ambient. In addition, an oxide layer may exist between Si/Al interface, although the aluminum electrodes are prepared at the power as high as 150 W. The existence of series resistance is, thus, inevitable, and may vary with different samples. When the MOS diode is measured at low frequency as shown in figure 5.11 (b), the damage layer capacitance is not significant, so it can be ruled out of the circuit. The
96 capacitance of the MOS diode is, therefore, given by 1 1 1 = + C Cox CD + Cit
(5.6)
Figure 5.11 (c) shows the equivalent circuit when the MOS diode is measured at high frequency. The interface traps do not respond the AC signal at high frequency, so the interface trap capacitance is ruled out. However, the damage silicon layer capacitance is activated at high frequency. So at high frequency, the interface capacitance is replaced by the damaged silicon layer capacitance. The capacitance of MOS diode is given by 1 1 1 = + C Cox CD + CDS
(5.7)
When the film is annealed at 600◦ C, the damaged silicon layer is removed by the interfacial reaction, and the leakage current density is reduced greatly. The damaged silicon layer capacitance is not present, and the effect of the parallel resistance is less important. The equivalent circuit is therefore, as shown in figure 5.11 (d).
97
Figure 5.11: Circuit model of: (a)Al/as deposited–HfO2 /Si MOS diode; (b) Al/as deposited–HfO2 /Si MOS diode measured at low frequency; (c) Al/as deposited–HfO2 /Si MOS diode measured at high frequency; (d) Al/HfO2 /Si MOS diode with low defect HfO2 film. (Cox : oxide capacitance; CD : depletion layer capacitance; Cit : interface trap capacitance; CDS : damage silicon layer capacitance; Rp : parallel resistance; Rs : series resistance)
98 5.3
RELIABILITY TEST
In this section, we discuss the reliability of the sputtered HfO2 film. This study includes a constant voltage stress as well as an aging test in the ambient. A constant voltage (Vef f = −2.05 and −3.05 V) was applied to the gate for 1500 seconds, and the I–V and C–V measurements were performed afterward. The aging test was to place the Al/HfO2 /Si MOS diodes in the ambient for one month. The results of the electrical measurements are reported in the following.
5.3.1 The effect of constant voltage stress on Al/HfO2 /Si MOS diodes A constant voltage (Vef f = −2.05 and −3.05 V) was applied to the gate for 1500 seconds. The I–V curves before and after stress is shown in figure 5.12. The figure indicates that the I–V characteristic does not alter much after stress at −2.05 V, but a greater change was observed when stressed at −3.05 V. That means charge trapping is not very significant at VG = −2.05 V, but active at VG = −3.05 V. This implies that there is a threshold value for electron enrergy below which charge trapping is not activated. The effect of stress on the C–V curves as shown in figure 5.13 shows different tendency from the I–V characteristics. The C–V curves both shift toward negative voltage, which suggests that positive charges are trapped during the stress. The depletion region of the C–V curves does not alter too much, which means that not many interface traps are generated during the stress. Shottky and Frenkel–Poole plots of HfO2 film (5.8 nm) before and after stress are shown in figure 5.14. The effective field is corrected as in equation 5.1. Although figure 5.12 does not show much difference after stressed at −2.05 V, the figure shows significant
99
0
10
Virgin i tr ss t V tr ss t V
dev ce
-2
|JG|
2
(A/cm )
10
S
e
a
S
e
a
eff
eff
V -3.05 V
= -2.05 =
-4
10
-6
10
-8
10
-10
10
0.0
0.5
1.0
|VG| Volts)
1.5
2.0
(
Figure 5.12: The I–V curves of HfO2 films (5.8 nm) before and after stressing for 1500 seconds.
100
Virgin ic tr ss t V tr ss t V Dev
1.0
0.8
S
e
a
S
e
a
r
eff
eff
im
C/C
ox
St ess t
M
r
e
V 3.05 V
= -2.05 = -
c
e: 1500 se
easu ed at 100 kHz
0.6
0.4
0.2
0.0 -3
-2
-1
VG Volts)
0
1
(
Figure 5.13: The C–V curves of HfO2 films (5.8 nm) before and after stress for 1500 seconds.
101
0
10
-7
Virgin device Stress at V = -2.05 V Stress at V = -3.05 V Stress time: 1500 sec
10
eff
eff
Frenkel-Poole emission
-2
2
-8
(A/
|JG|
V cm)
-4
10
S
chottky emission
-6
10
400
(A/
10
eff
cm )
/
JG E
10
-9
600
800
1000
E
eff
1200
1400
1600
10 1800
V cm
Figure 5.14: The Schottky and Frenkel–Pool plots of as deposited HfO2 film before and after stress. variation after the flat band voltage factor is taken into account. The figure also indicates that Frenkel–Poole emission is more dominant after stressed at −3.05 V, which means that the trapped charge effect is more significant. This may be due to more trapped charges within the oxide, or the lowering of the barrier height when HfO2 film was stressed at higher voltage. Figure 5.14 is a Schottky plot of an HfO2 film annealed at 600◦ C before and after stress. The figure indicates that the conduction mechanism is dominated by Schottky emission for the film annealed at 600◦ C in the entire sweep range. The trapped–assisted tunneling of this film is not significant, even after the film was stressed at −3.05 V for
102
-1
10
Virgin device Stress at V = -2.05 V Stress at V = -3.05 V Stress time: 1500 sec eff
-2
10
eff
|JG|
(A/
2
cm )
-3
10
-4
10
-5
10
-6
10
400
600
800
1000
E
eff
1200
1400
1600
1800
2000
V cm
Figure 5.15: The Schottky plots of HfO2 films annealed at 600◦ C before and after stress. 1500 seconds. The result shows that the shallow level traps are nearly removed by annealing. Therefore, the constant voltage stress does not increase the trapped charges, or alter the conduction mechanism. As compared with as deposited HfO2 film, the stress resistance is greatly enhanced. The increase of low level leakage current density is related to the creation of interface traps has been studied extensively [43, 44, 47, 49, 88]. The creation of the interface traps results from the release of hydrogen atoms at the interface, which originally pin the dangling bonds at SiO2 /Si interface. However, a threshold voltage for the generation of low level leakage current is required. DiMaria and Stasiak pointed out that in order to
103 relaease the hydrogen atoms, the kinetic energy of electrons has to be higher than 2.0 eV. The maximum kinetic energy of the tunnel electrons is given by [49] Emax = q[VG − (Vf b + ψs ) − φb ]
(5.8)
where Vf b is the flat band voltage, ψs is the surface potential, and φb is the potential barrier at the injecting interface. In our measurement, the stress is performed at accumulation, so that the surface potential is negative, and does not offset the gate voltage. So the effect of surface potential is ruled out. The φb for Al/HfO2 interface is 1.28 eV as shown in Zhu’s work [89]. Therefore, the maximum electron energy we have during the stress is 1.77 eV, which is lower than the threshold energy to release the hydrogen atoms. As a result, we suspect the charge traps existing in the HfO2 films are mostly generated during processing. These traps can be reduced by the postdeposition annealing.
104
2500
Original device Aging for one month
C/A (
2
nF/cm )
2000
Measured at 100 kHz
1500 1000 500
s deposit
A
0 -3
-2
-1
V
G
lts)
0
1
2
Original device Aging for one month
1500
C/A (
2
nF/cm )
2000
(Vo
Measured at 100 kHz
1000
500
nneal at 600
A
o
C
0 -4
-3
-2
-1
V
G
(Vo
0
1
2
lts)
Figure 5.16: The C–V curves measured before and after aging in the ambient 5.3.2 Aging effect on HfO2 films in the ambient Figure 5.16 indicates the C–V curves of the Al/5.8 nm–HfO2 /Si MOS diodes aged for one month. The figure clearly illustrates that for both samples, C–V curves shift and oxide capacitances, Cox , decrease during aging for one month. These results show that the ambient does change the oxide properties by injecting species into the film, which is observed at La–silicate as well [59]. The decrease of oxide capacitance may be attributed to the growth of an interfacial layer or carbonate formation [58, 90]. The shift of the C–V curve may result from the water–related species as we
105 mentioned in a previous section. These species infiltrate into the film by a capillary effect due to the porous structure of sputtered films. They even reach the interface and react with the silicon substrate. The larger shift in the as deposited film suggests that it has more porous structure. As a result, more water-related species are trapped into the as deposit HfO2 film. For the sample annealed at 720◦ C, the C–V curve can not be obtained after aging for one month. This means the ambient has a greater effect on the HfO2 film. This is because when grain boundaries are present, the infiltration is enhanced. More species are adsorbed by the film and even at the interface due to the presence of the grain boundaries. This result shows that the presence of grain boundaries worsens the reliability of crystallized film by enhancing the diffusion of undesired species, even at room temperature. The I–V characteristic of an Al/HfO2 /Si MOS diode after aging for one month is illustrated in figure 5.17. The correlation of heat treatment condition to leakage current density is the same. However, as summarized in table 5.4, the leakage current density of the crystallized sample increased by more than 150 %. The sample annealed at 600◦ C, which remained amorphous, increases about 33.92 %. This result again shows that the presence of grain boundaries is detrimental to the electrical properties. |JG | (A/cm2 ) Fresh MOS diode Aging for one month % Increase
As deposited 3.41 × 10−3 7.42 × 10−3 117.59
Annealed at 600◦ C 9.11 × 10−7 1.22 × 10−6 33.92
Annealed at 720◦ C 2.21 × 10−2 5.64 × 10−2 155.2
Table 5.4: The leakage current density of Al/5.8 nm–HfO2 /Si MOS diodes before and after aging
Both the results of C–V and I–V measurements show that the the HfO2 film annealed
106
1
10
A -2
|JG|
2
(A/cm )
10
s
osit l t 00 oC l t 20 oC
dep
ed
Annea a
6
Annea a
7
-5
10
-8
10
-11
10
-14
10
-2
-1
0
1
2
VG Volts) (
Figure 5.17: The I-V characteristic of Al/5.8 nm–HfO2 /Si MOS diodes aging for one month at 600◦ C has smaller changes after aging. This result indicates the adsorpting species in the HfO2 film annealed at 600◦ C is less than in the other two samples. This implies that the annealed HfO2 film has a denser structure than as deposited and crystallized films. Additionally, the absence of grain boundaries prevents the fast diffusion of these species. These results show that the HfO2 films are not stable in the ambient, and that protection of the sputtered films from the ambient is necessary.
107 5.4
SUMMARY
The I–V measurements show the crystallinity is the most dominant factor in leakage current density. The leakage current density increases significantly whenthe film crystallizes during annealing due to the presence of grain boundaries. The conduction mechanism is Schottky emission at lower fields, and Frenkel–Poole emission in the higher field region. After annealing at 600◦ C, the conduction mechanism is Schottky emission in the entire sweep range. The C–V characteristic is determined primarily by the interface properties. The as deposited films contain many defects within the film and at the HfO2 /Si interface, which shifts the position and stretches the C–V curve. When the film is annealed, the defect density is reduced, and the interface is modified. The C–V characteristic is changed significantly. The frequency dispersion in the accumulation and depletion regions are both enhanced greatly. The C–V curves shift toward negative voltages due to the generation of overcoordinated oxygen centers. When the film is annealed at 720◦ C, accumulation does not occur due to the high leakage current density. Reliability studies show that both the I–V and C–V characteristics change during constant voltage stress due to the charge trapping. The charges are trapped by native traps within the oxide, which are generated during the preparation. The constant voltage stress resistance of an HfO2 film annealed at 600◦ C is superior to the as deposited film. The results of the aging test show that the ambient aging can change the film properties. Water–related species infiltrate into the film, and even to the interface. The porous structure of sputtered films enables the adsorption and penetration of these species. When the film is annealed at 600◦ C, the film structure densifies, so less traps are generated dur-
108 ing aging, so that variations of I–V and C–V characteristics are not so significant. When the film is annealed at 720◦ C, the adsorption of water–related species is enhanced due to the presence of grain boundaries. The variations of the electrical properties during aging are more significant.
109 CHAPTER 6
CONCLUSION AND FUTURE WORK
6.1
Conclusion
Sputtered HfO2 films were prepared and characterized for potential application as the gate dielectric in MOSFET devices. This study reports on correlations between the physical and chemical properties of the films and the electrical properties of the films. The physical and chemical properties include the layer thickness, the interfaces of the layer, the defect structure of the layer and its composition. Glancing angle X–ray diffraction and TEM to evaluate the crystallinity of the layers, TEM cross-section images were used to determine layer thicknesses, and XPS was used to probe the chemical composition of the layers. Metal–oxide–semiconductor devices were fabricated to evaluate the electrical properties of the layers. The electrical properties which were measured include the leakage current, and the I–V and C–V characteristics. The films were annealed to evaluate the effects on the electrical properties, and to correlate these with observed changes in the structure and chemistry of the layers. The films were also subjected to voltage stressing and to aging in air to assess their long–term stability. The as deposited HfO2 films, which are prepared by reactive sputtering are very defective, and have a very porous structure and contain many point charge defects. These point defects serve as traps within the oxide, which produce shifts in the C–V curves from the ideal values. For HfO2 films annealed at a low temperature, the primary activity within
110 the film is the annihilation of point defects. Interstitials and excess vacancies migrate and annihilate. The driving force for this reaction is a decrease in excess point defects. At a higher heat treatment temperature, the atomic mobility increases, and crystallization begins. Thicker HfO2 (10 and 20 nm) films crystallize below 600◦ C. The ultra–thin HfO2 films (5.8 nm) crystallize between 600 − 725◦ C. Since thinner films crystallize at higher temperature, the region during which point defects are annihilated is extended in these films. The interface characterizations show that an amorphous silicon–rich silicate layer is produced between HfO2 /Si interface during the preparation process. During annealing, the interface layer thickens. The interfacial layer thickens more than during an anneal at 720◦ C, than at 600◦ C. This is ascribed to the presence of grain boundaries, because the layer annealed at 720◦ C crystallizes. The grain boundaries provide an easy transport path for oxygen species to reach the silicon substrate, and so to enhance the interfacial layer growth. The interfacial layer growth is accompanied a change in interface chemistry. Phase separation occurs at interface during heat treatment, so that the interface layer is converted to a silica–like layer. The growth of the interfacial layer modifies the interface structure and also its properties. When the heat treatment is performed at 600◦ C, the defects tend to migrate and annihilate as discussed above. The electrical properties of films are, consequently, enhanced due to the decrease of point defects. For samples annealed 720◦ C, where the HfO2 film has crystallized, the presence of the grain boundaries increases the leakage current density significantly, by one order of magnitude. The C–V characteristic is also adversely affected due to the increase of leakage
111 current density. The reliability of the gate oxide is strongly affected by its crystallinity and by variations in the interfacial properties. For films annealed at 600◦ C, the carrier transport mechanism is dominated by Schottky emission even after voltage stressing, which means the effect of traps is minimal. The aging test results indicate aging under ambient conditions, that is, in air at room temperature, changes the film properties. Traps are generated during the aging, which adversely affect the electrical properties of the film. In conclusion, the electrical properties are best if the film remains amorphous structure after heat treatment. The I–V, C–V and reliability characteristics of these amorphous films are enhanced by annealing, which is attributed to the annihilation of point defects, and to the modification of interfacial properties.
6.2 Future work The structural, interfacial, and electrical properties of the as deposited and annealed HfO2 films have been studied extensively in this work. It is concluded that amorphous HfO2 films after heat treatment have the best electrical properties. In previous work, the SiO2 /HfO2 /Si sandwitch was found to be able to stablize the amorphous of HfO2 to as high as 900◦ C. Therefore, changes of various properties of amorphous HfO2 films after annealing at 900◦ C, such as the interfacial reactions in an oxygen-deficient environment, shifts of C-V curves, resistance to voltage stress, and aging effects, should be studied. Sputter damage on the substrate surface has been observed in our results, although the TEM images do not show a rough surface. This damage needs to be ameliorated by
112 increasing the sputter pressure. The use of a different preparation method, such as ALD, may be more appropriate in order to avoid this problem. An interfacial layer of good quality is crucial in order to obtain good electrical properties. The preparation of an interfacial layer at a higher temperature under high vacuum should enhance the properties of the interfacial layer, and therefore, the electrical properties. Additionally, replacing interfacial layer with an oxi-nitride layer may prevent boron diffurion from silicon substrate. New gate electrode materials with appropriate work funcions should be used to replaced aluminum or poly-silicon. Perhaps an electrode material which is appropriate for both n– and p–MOSFET can be found, or perhaps different electrode materials for n– MOSFET and p–MOSFET may be required. Finally, the fabrication of the MOSFET devices using stablized HfO2 as the gate dielectric should be pursued.
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