Vin. Vout. WPG QWRTr. (active load). WPG SET. (driver Tr.) (S. Kasai and H. Hasegawa ... GaAs etched nanowires and .... AlGaAs/GaAs etched nanowire. V. DS.
Hokkaido University
ECS 2001 Joint Intenational Meeting, San Francisco Sept. 2-7,RC2001 Sixth International Symposium on Quantum Confinement
Quantum Devices and Integrated Circuits Based on Quantum Confinement in III-V Nanowire Networks Controlled by Nano-Schottky Gates
Hokkaido University
RC
Hideki Hasegawa Research Center for Integrated Quantum Electronics (RCIQE) and Graduate School of Electronics and Information Engineering Hokkaido University, Japan
Outline
Hokkaido University
RC
1. Introduction 2. Hexagonal BDD Quantum Circuits 3. GaAs-Based Quantum BDD Node Devices and Circuits • Novel nanometer-scale Schottky gates • GaAs-based quantum BDD node devices • Integration of BDD node devices on hexagonal nanowire networks
4. Toward Room Temperature Operation and High Density Integration • Formation of InP-based high density hexagonal nanowire networks • Surface related key issue
5. Conclusion Collaborators RCIQE staff Dr. S. Kasai, Dr. C. Jiang and Dr. T. Sato Students T. Muranaka, A. Ito and M. Yumoto
Speed, Delay-Power Product of Quantum Devices
Hokkaido University
RC
G ≈ G0 ≡ 2e h
2
τ = C G
J.E.Mooij, 1993 SSDM Ext. Abs. 339 106 300K 104
105K
thermal energy 1K
present-day semiconductor devices
10-15F
2
τ 10 [ps]
10-16F
1
10-17F Single Electronics
10-2 10-14
10-18F
Quantum Limit 10-12 10-10 10-8 P[W]
10-6
10-4
10-2
Hokkaido University
RC
Scale-down limit of Si CMOS LSIs
Research on Semiconductor Nanostructure
Growing demands on Information Technology (IT)
Nanotechnology in wide area ~ chemistry, biology, etc.
Semiconductor Nanoelectronics based on Quantum Device and Circuit • delay-power product near quantum limit • small-size and high-density • nano-sensing, nano-control
But, How to ? So far no realistic approach.
High Density Integration ?
Hokkaido University
RC
Semi-classical devices First Monolithic Integrated Circuit in the World (Noyce, 1959)
Current Microprocessor (2001)
IBM PowerPC
300µm rule
Discrete quantum devices
64-bit 0.18µm rule 700MHz 1.4mm x 1.4mm SOI technology
How to make QLSIs ?
Example of Quantum Logic Circuits
Hokkaido University
RC
QWRTr-load SET inverter (S. Kasai and H. Hasegawa presented at DRC 2000) 25 Gain = 1.3
QWRTr (Active Load)
20
input
output
VDD = 40 mV VBG = -1.0 V VG(QWRTr) = 0 mV
15 10
3-gate WPGSET
5 µm
W = 440 nm SET: LG = 50 nm, df = 200 nm QWRTr: LG = 300 nm VDD VG(QWRTr)
Vin
WPG QWRTr (active load) Vout WPG SET (driver Tr.)
5
T = 1.6 K
0 -550 -500 -450 -400 -350 -300 -250 Vin (mV)
small delay•power product but low gain voltage mismatch poor Vth control poor drivability low temperature
Novel Approach for III-V QLSI
Hokkaido University
RC
1. Digital Processing Architecture Binary Decision Diagram (BDD) logic architecture 2. Nanostucture Hexagonal nanowire networks by GaAs etched nanowires and InGaAs nanowires by Selective MBE 3. Nanoscale Gate Technology Schottky in-plane gate (IPG) and wrap gate (WPG) 4. Surface and Interface Control Nano-Schottky interface Interface control layer (ICL)-based passivation 5. Device BDD node devices using gate-control quantum wire (QWR) and quantum dot (QD)
Digital Logic Architecture
Hokkaido University
RC
Digital processing (operations on digital functions) Implementation of digital functions Representation Boolean Equation Truth Table
etc. Binary Decision Diagram (BDD)
Implementation Binary Logic Gate Look-Up Table using Memory Transistor Switch ROM device
BDD Device
Hexagonal BDD QLSI Approach
Hokkaido University
RC
BDD logic architecture
BDD node device entry branch input 0
messenger Xi
1
0-branch 1-branch QWR switch
r1
root
tunnel barrier
input
0
0
x1
1 0
x12
x13
1 0
x1i
1
0
x1n
quantum dot
terminal
r2
0
Hexagonal network
1
0
0
x2
Boolean Logic Gate
f x1
1
1 0
x2
0
x1 f x2
1
3 devices
node
1
Example: Exclusive OR Logic Function BDD
1
5 gates, 16 Trs
Features of Our Approach
Hokkaido University
RC
BDD is suited to quantum devices No direct input-output connection is required •no precise voltage matching •no large voltage gain •no large current drivability •no large fan-in and fan-out
Conventional Logic Gate Architecture
Ultra-low delay-power product near the quantum limit Hexagonal quantum BDD
High density integration •hexagonal closely packed nanowire network •free from contact problem •reduced device count
root
few electron regime
many electron classical regime
r2
x1
x2
x3
node
x4
input
The circuit itself works at room temperature 1 at sacrifice of delay-power product IPG/WPG QWRTr-based BDD devices act as classical path switching devices even under non-quantum conditions. single electron regime
r1
xi xn 0
terminal
Basic Schottky Gate Structure
Hokkaido University
RC
Schottky In-Plane Gate (IPG) and Schottky Wrap Gate (WPG) control of AlGaAs/GaAs etched nanowires Schottky Schottky GaAs In-plane Gate (IPG) Wrap Gate (WPG) nanowire electrons AlGaAs GaAs
·lateral structure ·stronger confinement size ~ smaller AlGaAs/GaAs quantum wire nanowire
depletion layer WPG quantum wire transistor (QWRTr)
suitable for planar integration high temperature operation tunnel barrier control WPGs
quantum dot 2-gate WPG single electron transistor (SET)
Gate Control Characteristics of IPG/WPG Structures
Hokkaido University
RC
Controlof Weff
SdH oscillation
IPG QWRTr 4
Source Wgeo
T = 4.2K
800
3
400
1 Drain
1µm
0
600
-0.4V
2 IPG
-0.6V
0
1
2
3
4 5 B (T)
6
7
8
200 0
WPG QWRTr LG
Schottky WPG
5
W
500 nm
T=1.6 K
0
-1.5
-1 -0.5 VG (V)
0
WPG QWR
400
15 10
-2
500
20
GaAs exit branch
IPG QWR
VG=0V
-0.48V
-0.36V
300 -0.42V -0.24V
0
1
2
3 4 B (T)
200
VG=0V
5
6
100 0 -0.6
-0.4 -0.2 VG (V)
0
I-V Characteristics of IPG/WPG QWRTrs
Hokkaido University
RC
AlGaAs/GaAs etched nanowire IPG QWRTr 30
10
VG =0V
T = 300 K 25
T=1.7K
VG = 0 V
8
20
-0.2V
15
-0.4V
6 -0.05 V 4
10 -0.6V 5 0
WPG QWRTr
-0.1 V
2 -0.2 V
-0.8V 0
0.5
1.5
2
0
0
0.1
VDS (V)
3
2
1
4
W = 530 nm LG = 600 nm T=3K
3
-0.15 V
0.2 0.3 VDS (V)
0.4
0.5
W = 750 nm LG = 300 nm T = 1.7 K
2 1 1 0 -800
0 -600 -400 VG (mV)
-200
-600
-550 -500 VG (mV)
-450
Single Electron Transport in 2-WPG SET
Hokkaido University
RC
GaAs SET GaAs nanowire
Lateral resonant tunnling of single electron
WPG
e2 h
I=
|T(E)|2 [f (E) – f (E+qVDS)] dE
0.6 Breit-Wigner formula e 2 Γl Γr 1 ~ l r 4kTΓ +Γ cosh2 E-EF 2kT
0.5
AlGaAs
GaAs
0.4 0.3
Experiment 1.4 1.2 1.0 0.8 0.6 0.4 0.2
Theory
df = 160 nm, W = 820 nm T = 30 K 20 K 15 K 7.5 K 4.2 K 2.5 K 1.5 K
1.4 1.2 1.0 0.8 0.6 0.4 0.2
0.2 0.1
T = 30 K
0.0
0
5
10
5
10
20 K 15 K
60
4.2 K
40
2.5 K
20
1.5 K
20
25
20
25
30
80
7.5 K
0.0 0.0 -1.3 -1.25 -1.2 -1.15 -1.1 -1.3 -1.25 -1.2 -1.15 -1.1 VG (V) VG (V)
15 T (K)
0
0
15 T (K)
30
Various Types of BDD Node Devices by IPG/WPG Control of III-V Nanowires QWR-based BDD node device entry IPG
GaAs nanowire
WPG
QWR 0-branch
1-branch
Single electron BDD node device tunnel barrier
GaAs nanowire
WPG
quantum dot
WPG SET
Hokkaido University
RC
WPG BDD Quantum Node Device
Hokkaido University
RC
WPG QWR-based BDD device entry GaAs nanowire
500 nm
WPG single electron BDD devices entry GaAs nanowire
500 nm
WPG xi
xi
xi
xi
entry GaAs nanowire xi 0
1-branch
0-branch
0-branch
WPG 1-branch
WPG xi 1 1 µm
entry QWRTr
xi
0-branch
SET
xi
xi
xi
xi
xi
1-branch tunnel barrier
branch switch type
quantum dot
quantum dot
branch switch type
tunnel barrier
node switch type
Switching Characteristics
Hokkaido University
RC
QWR branch- switch BDD node device entry QWRTr
xi
xi
0-branch
1-branch
Switching characteristics
Branch I-V T = 300 K 4 1-branch
x
VG = 0 V
x
T = 300 K
0 -1
-0.2
3
0-branch
2
1-branch
-0.4
2
-0.6
1 0 0
-0.8 -1.0 100 200 300 400 500 VG (mV)
1
1 0 0
1
VDD = 200 mV 2 3 4 Time (s)
WPG BDD Single Electron Node Device
Hokkaido University
RC
entry 1 µm QD-based node switch GaAs nanowire device WPG xi 0-branch
Conductance oscillation from single channel 0.06
0.04
T = 1.5 K VGent = -3.0 V VGxi = 0.4 V 0-branch: open
-2.0
1-branch
Switching characteristics 3 2
0.02
0
xi
0-branch
VGent = -2.4 V VGxi = +0.4 V
1
-1.8
-1.6 -1.4 VGxi (V)
-1.2
0 -1.9
1-branch
T = 1.5 K
-1.8
-1.7 VGxi (V)
Conductance oscillation due to single electron transport Clear path switching
Quantum BDD Implementation
Hokkaido University
RC
Quantum BDD large scale integration hexagonal nanowire network + WPG 0
x1
1
0
x1
x1 1
WPG
x1 0
x2
10
x2 0
x2 1
x3
wiring
x2 x3 1
x3 0
x4
1
0
x4
x4 1
x4
branch cut-off (etching, FIB) one level metallization
WPG BDD OR Logic Function Block
Hokkaido University
RC
WPG single electron BDD OR circuit root
x1
hexagonal layout
x1
WPG
f node device
x2
0
x1
root 1
x2 1 GaAs nanowire
1000 nm 1- terminal
1
1-terminal
Operation of WPG BDD OR Logic
Hokkaido University
RC
Input/Output waveform
OR 0 x1 1 0 x2 1
1
0.3 0.2
T = 1.6 K x1 x2 output
0.1 0
0
2 VDD = 1 mV clock: 2 Hz
4 6 Time (s) x1: x2:
8
10
pulse height 100 mV 250 mV entry gate: 0 mV
0.7 0.6 0.5 0.4 0.3 0.2 0.1 0
T = 120 K x1 x2 output
0
50 VDD = 0.2 mV clock: 0.1 Hz
100 150 Time (s) x 1: x 2:
pulse height 1200 mV 1000 mV
200
entry gate: +1000 mV
WPG BDD Fundamental Logic Family
Hokkaido University
RC
OR
Half adder (exclusive OR) OR
0
0
x2
x1
1
1
x1 x2 0 0 0 1 1 0 1 1
ExOR
x1+x2 0 1 1 1
0
x2
1
x2
1
0
1
x1+ x2 0 1 1 0
1
1 x1
0.6
x1
0
x1 x2 0 0 0 1 1 0 1 1
120 K
RT
x1
x2
x2 output
0.4 output
20 nA
0.2 0
0
50
100 150 Time (s)
200
pulse height x1: 1200 mV x2: 1000 mV entry gate: +1000 mV VDD = 0.2 mV
0
5
10
15 20 25 Time (s) pulse h +x1: 0.02 V - x1: 0.44 +x2: 1.7 - x2: 0.1 VDD: 250 mV
30 offset -0.4 V -1.2 1.9 1.6
35
Circuit Design and Fabrication Technology Towards BDD Quantum Integrated Circuit
Example: BDD 2-bit adder
c1 1
root node
a1 0
c1
s0 a1
a1 0 0 a1 1
1
1
1
b1 0 1 b1 0 0 b1 1 1 a0 0
1
1
b0 0
0
b1
b1 1 0 b1 1
1
s1
1
b0 0
a1
1
0 1
s0
1 0
1
1
1 a1
1 0
b1
b1 a0 0
a0
1 1
b0
b0
0
0 1
terminal-1 sum: s1, s0 carry:c1
nanowire
1
root
s0
0 0
b1 b1
0 a0 1 1 a0 0
b0 0
augend: a1, a0 addend: b1, b0
0
s1
WPG/nanowire layout
s1 1
RC
Fabricated 2-bit adder circuit c1
circuit diagram
Hokkaido University
terminal
WPG augend: a1, a0 addend: b1, b0 sum: s1, s0 carry:c1
a0
a1
WPG
b1 QWRTr node device
a0
b0
b0
GaAs nanowire
5 µm 1-terminal
Hexagonal BDD 2 bit Adder
Hokkaido University
RC
a1 WPG C
S1
b1
S0 node device
a0 a1 b1
b0 hexagonal nanowire network
a0 terminal 1
5 µm b0
input
a1 a0 b1 b0
800 600 400
carry
200 0 0
10
20
30
40 50 time (s)
60
70
80
T = 300 K VDD = 250 mV
InGaAs Ridge Nanowires for Room Temperature Operation AlGaAs/GaAs etched nanowires: possible minimum width = 70-100 nm Room temperature operation requires sub-10 nm width InGaAs ridge quantum wire
Hokkaido University
RC
PL
T=20K QWR
InAlAs
23meV InGaAs
3µm
patterned InP sub.
0.8
Formation Process
4µm
(111)A
Pre-growth etching & O desorption by atomic Hydrogen
narrowest QWR by H* cleaning
1.4
1µm
1.2
InP patterned sub.
InGaAs ridge
MBE growth of InGaAs
1.0 1.2 1.4 Energy (eV)
InGaAs ridge QWR
1.0 theory 0.8
Growth of InAlAs/InGaAs/InAlAs
0
10 20 30 40 50 Effective width, Weff (nm)
Wire width of 6 nm has been achieved
Hexagonal InGaAs Ridge Nanowire Network
Hokkaido University
RC
SEM image of hexagonal InGaAs nanowire network
AFM image
µm 0.8 0.4
µm
4 3 3 µm
4 2 1
1
2
3
( Ito et al. IPRM01, ICFSI-8)
Potential Controllability of Nanometer-Sized Schottky Gates
φMS = 1.0 eV Lg = 90nm
n-GaAs 1. With strong pinned surface
2. With unpinned surface
gate
gate
0.8 ~ -2.0 V step 0.4 V 500
0
500 (nm)
RC
nano-Schottky gate
Semiconductor surface 1. Strong pinning (0.88 eV) 2. Unpinning
0
Hokkaido University
1000
0.8 ~ -2.0 V step 0.4 V 0
500 (nm)
1000
Control of an environmental Fermi level pinning is important
Conclusion
Hokkaido University
RC
1)
A new, simple and realistic approach for quantum LSIs is presented and discussed. •Architecture: BDD logic architecture •Hardware: Schottky WPG control of hexagonal III-V nanowire networks.
2)
WPG QWR and single electron BDD node devices using GaAs etched nanowires have been fabricated and BDD switching was realized.
3)
Hexagonal BDD ICs using GaAs etched nanowires have been fabricated. Logic operation has been confirmed.
4)
Hexagonal InGaAs nanowire network by H* assisted selective MBE combined with IPG/WPG gate technology gives good prospect for high density BDD QLSIs that are operating at delay-power products near the quantum limit at RT.
5)
Control of surface/interface remains to be a key issue.
