Sep 17, 2009 - Abstractâ This DC-DC buck converter is able to operate up to 120-MHz switching frequency with peak power efficiency of. 87% for 75% duty cycle ... 12 mW and the dynamic dissipation is 100 µW. On the contrary, with .... is a valuable solution for converters in the watt range to be integrated as SIP or SOC.
M. Belloni, E. Bonizzoni, F. Maloberti: "High Efficiency DC-DC Buck Converter with 60/120-MHz Switching Frequency and 1-A Output Current"; 35th European Solid-‐State Circuits Conference, ESSCIRC 2009, Athens, 15-‐17 September 2009, pp. 452-‐455.
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High Efficiency DC-DC Buck Converter with 60/120-MHz Switching Frequency and 1-A Output Current Massimiliano Belloni, Edoardo Bonizzoni, and Franco Maloberti University of Pavia Department of Electronics Via Ferrata, 1 – 27100 Pavia – ITALY [massimiliano.belloni, edoardo.bonizzoni, franco.maloberti]@unipv.it Abstract— This DC-DC buck converter is able to operate up to 120-MHz switching frequency with peak power efficiency of 87% for 75% duty cycle and 93% at 60 MHz. Key feature of this design is a new control method that replaces the conventional op-amp based scheme. The proposed circuit uses a current-mode control and a voltage-to-pulse converter for the PWM. The circuit, fabricated using a 0.18-m CMOS technology, reaches a peak load regulation of 20 mV/V and line regulation of 0.5 mV/V at 300 mA. The used 36-nH inductance and 4.7-F capacitor are suitable for SiP realizations.
I.
INTRODUCTION
Modern portable devices more and more require multioutput DC-DC converters with relative low currents but minimum volume and external components. Applications possibly share the inductors, the bulky element of buck or boost converters, or miniaturize the single DC-DC block. The first method is convenient for relative low currents (few hundreds of mA) because the cost of an extra switch in the buck scheme limits the power efficiency. To miniaturize the DC-DC converter, the used strategy increases the operating frequency to reduce inductance and capacitance. Target is to obtain small values to enable on-chip or in-package integration, [1-4]. The request of currents below 1 A makes reasonable the sizes of power switches. The dynamic dissipation is relatively low and the operational frequency can be increased from nowadays 5 MHz to several tens or hundreds of MHz. However, high switching frequency causes a quadratic increase of power in the control circuit that quickly becomes a non-negligible fraction of the dynamic dissipation, thus reducing efficiency. Buck converter aims at efficiencies higher than a linear regulator for a large range of the output current. If the generated voltage Vout is D times the supply voltage, the efficiency of the linear regulator is D. Therefore, the goal is to keep system efficiency well above D for an extended range of output current. Just obtaining very high switching frequency [1, 2] is not practical. The goal of this design is to achieve for 1-A output current, efficiency higher than what reported in published research results, [3, 4].
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This design reduces the power of the control loop at high switching frequency by a novel control strategy. Instead of using op-amps, the design employs current mode processing followed by a voltage-to-pulse converter. The total required current is as low as 45 A for switching frequencies up to 120 MHz. The buck converter, fabricated in a 0.18-m CMOS technology, achieves 93% peak efficiency with 500-mA output current, 1.1-V output voltage, 60-MHz switching frequency and 2.2-V supply voltage. The efficiency diminishes to 87% with 120-MHz switching frequency. At 1-A output current and 60-MHz switching frequency, the efficiency is 85% and remains above the linear limit until 100 mA. The inductance is 36 nH and output capacitor is 4.7 F. Experimental measurements show that load and line regulation are about 20 mV/V and 0.5 mV/V with 500-mA and 300-mA output current, respectively, figures that are obtained with no filter in the control loop. II.
DESIGN CONSIDERATIONS
Increasing switching frequency in conventional DC-DC converters requires op-amps in the control loop with an augmented bandwidth and large slew-rate. As known, more speed in the op-amps requires more current. The increase is linear if input transistors are in weak inversion, almost quadratic if in saturation. Typically, weak inversion is not possible and power cost of the control section becomes remarkable for switching frequencies above 50-60 MHz. The control circuit of typical buck converters operating at 3-MHz consumes around 20-30 W. At fCK = 60 MHz the power must increase by at least 200 times going up to 4-6 mW, that is some percents of the output power for currents below 0.1 A and low regulated voltages around 1 V. The conventional counterpart of this design is a buck converter with 3-MHz switching frequency, 2.8-V supply, with 30 W consumption in the control and 5 W of dynamic power. The overall series resistance is 0.12 . The power efficiency is higher than 95% in the 50 mA - 1 A
range of output current. If switching frequency goes up to 60 MHz the power needed by the control becomes about 12 mW and the dynamic dissipation is 100 W. On the contrary, with this design the power of the control is only 99 W for operation in the range 3-150 MHz. Therefore, expected performance, as shown in Fig. 1, compared with the conventional counterpart shows an improvement of the linear limit by 30% for a design optimized for having the peak efficiency at 0.5 A and 60-MHz switching. Obviously, the benefit would increase for designs optimized for lower output currents.
Fig. 1 – Simulated power efficiency of the proposed and a conventional scheme.
III.
CIRCUIT DESCRIPTION
As mentioned, the key feature of this design is a new control method that replaces the conventional op-amp based scheme. Other than allowing enhanced efficiencies, the method is promising for switching frequencies in the hundred MHz range that would need op-amps with multi-GHz unity gain frequencies. Fig. 2 shows the general architecture. The error drives a voltage-to-pulse converter (V2P) that directly controls the power switches driver (DRVR). Moving in the current domain significantly spares power and achieves controls up to very high frequency with pseudo-integral features.
Fig. 3 – Schematic diagram of the V2P together with bias generator.
Current-mode control is also employed in [5]. This design improves the method with a more effective voltageto-current converter (V2I). Fig. 3 shows the circuit schematic. The input differential pair transforms error, = (Vset kVout ) , into current and provides a transconductance gain, Gm. Output current I4 = IB /2 Gm is 1:1 mirrored and used to charge capacitor C1 (n-well shielded), initially discharged at VDD. The trigger signal starting the capacitor charge is a short pulse synchronous with the clock. The output control, started at the beginning of the switching period, ends when VG0 crosses the threshold of MP0, VthP0, and is enforced by a tapered inverter chain. With balanced signals at input of the V2I, the charge current of C1 is I1 = IB/2 with duty cycle D = 2C1VthP 0 /(IB TCK ) . Therefore, if the system needs a duty cycle D , a bias current IB = 2C1VthP 0 /(D TCK ) should be used. This design controls the bias current of the input differential pair with a proper generator. It uses two voltages, the setting and a suitable control, Vset and Vc, as shown in Fig. 3. The two voltages and the RB determine the bias current. The Vset gives a rough control of the current that diminishes at high settings. Moreover, a sudden change of setting voltage gives rise to an immediate response that changes the duty cycle. The control of Vc obtains a fine trimming and is open loop or closed loop. Open loop uses an external voltage. Closed loop processes the error in the current domain by using a replica of the error current I4 that is integrated on an RC with large time constant (off-chip for this implementation) to increase IB when I4 > IB. With D = 0.75, C1 = 0.15 pF, VthP0 = 0.7 V and fck = 60 MHz, IB is 16.8 A, a very low value when compared with current of conventional control loops at same switching frequency. Also, the required silicon area is negligible. The scheme has an equivalent loop gain. Its value for a quiescent duty cycle D with bias current I B is given by the expression of D as function of the error D=
Fig. 2 – Architecture of the proposed buck converter.
D G D1+ m G IB /2 1 m IB /2
(1)
linearly proportional to the error around the expected duty cycle. In conventional counterparts, the loop gain and the amplitude of saw-tooth, Vs, gives the sensitivity to error
dD/d = A0/Vs. An equivalent sensitivity is provided by the derivative of equation (1). It results
dD A0 = d Vs
= eq
2DGm IB
(2)
This design uses MOS transistors in saturation; therefore, Gm=IB/Vov yielding A0 Vs eq = 2D /Vov . Since the overdrive voltage is 80 mV, with D = 0.75 and Vs = 1.2 V, the equivalent gain is A0 = 22.5, a value that properly operates the circuit. IV.
MEASUREMENT RESULTS
The circuit has been designed using a standard 0.18-m CMOS technology with dual poly and 5 metals. The supply voltage ranges from 2.2 to 2.8 V. The nominal switching frequency is 60 MHz. Experimental results show that, at 2.2-V minimum supply, the output regulation range is 0.5 V – 2 V with output current up to 1 A. The power efficiencies for Vout = 1.1 V and 1.65 V (VDD = 2.2 V, D = 0.5 and 0.75, respectively) are shown in Fig. 4. The same figure also gives the power efficiency with higher supply voltage (2.8 V) and same values of D. Peak efficiency equals 92% and 93% for 2.8-V and 2.2-V supply voltages, respectively, and D = 0.75. Higher supply causes larger dynamic dissipation and this worsens the efficiency at low currents. However, the low power of the control (only 45 A), sustains the overall efficiency at almost one decade below the peak. Fig. 5 shows the load regulation measurement with output current, IL, switched from 0 A to 500 mA by on-off current control on PCB. The load switching speed is 4 s.
Fig. 5 – Measured load regulation with output current changing from 0 to 500 mA.
The low frequency ringing of the 1.4-V output voltage is mainly caused by the PCB and probe coupling. Load regulation is about 20 mV/V. Fig. 6 depicts the line regulation measurements for two different output voltages (0.9 V and 1.5 V) and different load conditions (0 and 300 mA output current). The line regulation is always less than 6 mV/V with no load and less than 0.5 mV/V with an output current of 300 mA.
Fig. 6 – Measured line regulation for different load conditions.
Fig. 4 – 60-MHz switching frequency measured power efficiency.
Since the control is able to operate at higher frequency, allowing lower inductors, the circuit has been tested at 120 MHz with halved inductance. Even if the design is optimized for 60-MHz switching frequency, with size of the power transistors such to obtain the peak efficiency higher than 90% of Fig. 4, the circuit obtains good performance. Fig. 7 gives the obtained efficiency. The results are good. However, an ad-hoc design with a proper trade-off between static and dynamic dissipation would give even better results. The peak efficiency is 87% at 0.7 A and the linear efficiency crossing point is 200 mA. The figure compares the simulated efficiencies for this design and the one of the conventional counterpart. The crossing point is at 200 mA for this circuit while it is at 320 mA for the conventional counterpart. Simulations at the transistor level optimized for 120 MHz
switching frequency predict a peak efficiency of 91% at 0.56 A and crossing point at 150 mA (Fig. 5). The measurements and simulation results show that the method can be used in SIP with inductors in the 10-15 nH range and capacitors of few F. With currents of hundreds of mA, switching frequency can be further increases while maintaining high the peak efficiency.
PERFORMANCE SUMMARY
TABLE I.
Feature
Value
Supply Voltage
2.2 V2.8 V
Output Voltage
0.5 V (VDD–0.2 V)
Output Current
01 A
Nominal Switching Frequency
60 MHz
Allowed Switching Frequency
Up to 120 MHz
Max Output Voltage Ripple
10 mV
Peak Power Efficiency
93%@60 MHz, 88%@120 MHz
Control Current Consumption
45 A
Max Line regulation
8 mV/V
Load Regulation @ 60 MHz
20 mV/V
Load Regulation @ 120 MHz
25 mV/V
V.
CONCLUSIONS
This design experimentally verifies a novel loop control scheme for DC-DC converter to obtain very high speed switching frequency with low power consumption. The power of control circuit is the bottleneck for an effective increase of DC-DC converters for portable apparatuses. The use of the proposed method is a valuable solution for converters in the watt range to be integrated as SIP or SOC. Fig. 5 – Measured and simulated power efficiency at 120-MHz switching frequency.
ACKNOWLEDGMENTS The authors would like to thank National Semiconductor Corporation for chip fabrication and FIRB, Italian National Program #RBAP06L4S5, for partial economical support. REFERENCES
Fig. 8 – Chip microphotograph.
Fig. 8 shows the chip microphotograph. Power transistors, MP and MN, their drivers (DRVR) and V2P are highlighted. The active area is 1.2 mm x 0.76 mm, with 0.003 mm2 used for the current-mode and V2P control. Table 1 summarizes circuit performance. In addition to the already indicated features, it is worth to note the low load regulation at 120-MHz switching frequency.
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