High-Efficiency MOSFET Inverter with H6-Type ... - IEEE Xplore

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 4, APRIL 2011

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High-Efficiency MOSFET Inverter with H6-Type Configuration for Photovoltaic Nonisolated AC-Module Applications Wensong Yu, Member, IEEE, Jih-Sheng (Jason) Lai, Fellow, IEEE, Hao Qian, and Christopher Hutchens

Abstract—A novel, high-efficiency inverter using MOSFETs for all active switches is presented for photovoltaic, nonisolated, acmodule applications. The proposed H6-type configuration features high efficiency over a wide load range, low ground leakage current, no need for split capacitors, and low-output ac-current distortion. The detailed power stage operating principles, pulsewidth modulation scheme, associated multilevel bootstrap power supply, and integrated gate drivers for the proposed inverter are described. Experimental results of a 300 W hardware prototype show that not only are MOSFET body diode reverse-recovery and ground leakage current issues alleviated in the proposed inverter, but also that 98.3% maximum efficiency and 98.1% European Union efficiency of the dc–ac power train and the associated driver circuit are achieved. Index Terms—AC module, high efficiency, MOSFET inverter, nonisolated, photovoltaic (PV) systems, transformerless.

I. INTRODUCTION HOTOVOLTAIC (PV) ac modules may become a trend for future PV systems because of their greater flexibility in distributed system expansion, easier installation due to their “plug and play” nature, and higher system-level energy harnessing capabilities under shaded or PV manufacturing mismatch conditions as compared to the single or multistring inverters [1]–[4]. A number of inverter topologies for PV ac-module applications have been reported so far with respect to the number of power stages, location of power-decoupling capacitors, use of transformers, and types of grid interface [5]–[15]. Unfortunately, these solutions suffer from one or more of the following major drawbacks: 1) the limited-lifetime issue of electrolytic capacitors for power decoupling [5]–[9]; 2) limited input voltage range for the available panels in the market [10]–[12]; 3) high ground leakage current when the unipolar pulsewidth modulation (PWM) scheme is used in a transformerless PV system [13]; 4) low-system efficiency if an additional high-frequency bidirectional converter is employed [14]–[16]; and 5) increased cost

P

Manuscript received December 6, 2009; revised March 25, 2010 and July 12, 2010; accepted August 16, 2010. Date of current version June 10, 2011. The paper was presented in part at the 25th IEEE Applied Power Electronics Conference, Palm Springs, CA, February 21–25, 2010. Recommended for publication by Associate Editor T. Shimizu. The authors are with the Bradley Department of Electrical and Computer Engineering, Virginia Polytechnic Institute and State University, Blacksburg, VA 24061-0111 USA (e-mail: [email protected]; [email protected]; [email protected]; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TPEL.2010.2071402

Fig. 1.

Two-stage PV ac-module application of the H6-type inverter.

and complexity of the circuit if energy in the transformer leakage inductance is recycled by either an active snubber or softswitching circuit [17]–[19]. Since galvanic insulation in an ac module for PV application is not required by code, a two-stage ac module combining a nonisolated high step-up converter and a high-efficiency inverter with H6-type configuration, as shown in Fig. 1, can be used to solve the aforementioned issues. This two-stage system configuration can significantly reduce the power-decoupling capacitance by locating the capacitor in the dc link [3]. And the first stage also can be designed to meet the requirement of the wide input voltage range for the available panels in the market. Reference [20] reported a dc–dc converter with a single active switch—combining boost, flyback, and charge-pump circuits to simultaneously achieve wide input range, high-voltage gain, high efficiency, and low cost with the 20–70 V input, 180– 200 V output, and 97.4% peak efficiency as the first part of PV integrated ac module. This paper, however, will concentrate on the second power stage—the inverter circuit to obtain high efficiency of the MOSFET dc–ac circuit and to avoid the high ground leakage current issue. The simplest inverter using hybrid MOSFETs and insulated gate bipolar transistors (IGBTs) with unipolar PWM to achieve high efficiency is shown in Fig. 2. The high-side IGBTs serve as line frequency polarity selection switches and low-side MOSFETs operate in high frequency sinusoidal PWM (SPWM) to control the output voltage or current. The high efficiency of the hybrid four-switch inverter can be achieved over wide load range because the MOSFETs can avoid the fixed voltage-drop losses and significantly reduce the turn-OFF losses without tail current as compared to the case with IGBTs. However, the hybrid four-switch inverter with unipolar PWM is not suitable for nonisolated ac-module application because the high ground leakage current is generated through the parasitic capacitance of the PV panel due to the high-frequency voltage swing at the PV terminals. The severe ground leakage current results in the problems, which include lower efficiency, output current distortion, electromagnetic interference (EMI) and safety issue [21]–[26].

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Fig. 2. Simplest inverter using hybrid MOSFETs and IGBTs with unipolar PWM to achieve high efficiency.

Fig. 3.

Fig. 4.

Circuit diagram of the proposed inverter with H6-type configuration.

High efficiency five-switch inverter with low ground leakage current. Fig. 5. PWM scheme for the proposed inverter: (a) signals in time domain; and (b) implemented circuit.

The five-switch high-efficiency inverter with unipolar PWM, as shown in Fig. 3, to solve the high ground leakage current issue is presented in [21]. The MOSFET S5 and S1 or S2 operate in the SPWM to avoid the fixed voltage-drop losses and significantly reduce the turn-OFF losses like what the inverter shown in Fig. 2 does. In addition, high-frequency voltage swing at the PV terminals is eliminated because the top and bottom switches are turned off simultaneously to share half the dc-bus voltage and to decouple the PV from the grid during the output inductor freewheeling interval. However, MOSFETs cannot be used as S3 or S4 in the inverter, as shown in Fig. 3, to further improve the efficiency in the PV ac-module applications where power level is typically lower than 300 W because the MOSFET body diode slow reverse-recovery induces large turnON loss, possible device damage and EMI problem [27], [28]. Moreover, the cost-effective solution using bootstrap technology with the integrated chips to drive the high-side and midside active switches has not been presented. In this paper, a novel, high-efficiency inverter, using MOSFETs for all the active switches, is proposed for PV, nonisolated, ac-module applications. The presented H6-type configuration features high efficiency over a wide load range, low ground leakage current, no need for split capacitors, and lowoutput ac-current distortion. Detailed power stage operating principles, PWM scheme, and novel bootstrap power supply for the proposed inverter are described. To verify the validity of the circuit and the improved performance of the proposed inverter, a 300 W hardware prototype—targeted at PV nonisolated ac-module applications—has been designed, fabricated, and tested. Experimental results show that not only are MOSFET body diode reverse-recovery and ground leakage current issues alleviated in the proposed inverter, but also that 98.3% maximum efficiency at about half of rated output power and 98.1% European Union (EU) efficiency of the dc–ac power train and the associated driver circuit are achieved.

II. PROPOSED INVERTER TOPOLOGY AND OPERATION ANALYSIS Fig. 4 shows the circuit diagram of the proposed inverter with H6-type configuration, which is composed of six power MOSFETs (S1 –S6 ), two freewheeling diodes (D1 and D2 ), and two split inductors (L1 and L2 ) as a low-pass filter. This circuit is well suited for nonisolated ac-module applications because of the following advantages: 1) high efficiency over a wide load range by using MOSFETs for all active switches since their intrinsic body diodes are naturally inactive; 2) low ground leakage current because the voltage applied to the parasitic ground-loop capacitance contains only low-frequency components; 3) smaller output inductance as compared to that of the common full-bridge inverter with bipolar PWM switching; and 4) low-output ac current distortion because there is no need to have dead time for the proposed circuit since the three active switches in the same phase-leg never all turn ON during the same PWM cycle. Fig. 5 illustrates the PWM scheme for the proposed inverter. As shown in Fig. 5(a), the top device in one leg and the bottom device in the other leg are switched simultaneously in the PWM cycle and the middle device operates as a polarity selection switch in the grid cycle. As shown in Fig. 5(b), if the sinusoidal control voltage vcontrol , which is synchronized with output voltage, is higher than the triangular carrier voltage vcarrier , then the gating voltage G1 and G6 are active; otherwise, G1 and G6 are inactive. And if vcontrol is higher than zero, the gating voltage G4 is active; otherwise, G4 is inactive. Similarly, the comparison of (−vcontrol ) with vcarrier or zero results in the logical signals to control G2 , G5 , and G3 , respectively. Fig. 6 shows the four topological stages in one grid cycle for the proposed inverter. Note that the point N is the dc-link negative terminal, and the point E is the grid negative terminal. The

YU et al.: HIGH-EFFICIENCY MOSFET INVERTER WITH H6-TYPE CONFIGURATION

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On the basis of the fact that (6) is identical to (3), the PWM switching frequency voltage of the ground potential is avoided. The operation modes similarly change during the grid negative half cycle. From Fig. 6(a)–(d), it can be seen that the body diodes of the MOSFETs are naturally inactive and the high-frequency voltage of the ground potential is avoided during the whole grid cycle. As a result, MOSFETs can be employed as all the active switches to achieve higher efficiency than that of the five-switch inverter, and high ground leakage current can be avoided just as same as the five-switch inverter. In case of enough energy left in the inductor, at the transition mode of turn-OFF G4 , zero-voltage-switching will be achieved because the current of the inductors is freewheeling through the body diodes of S2 , S3 , and S5 . Therefore, it is a normal transition without any device over-voltage issue. Fig. 6.

Topological stages of the proposed inverter.

four operation modes are briefly described as follows. During the grid positive half cycle, switch S4 remains ON, whereas S1 , S6 , and D1 commutate at the PWM switching frequency. When S1 , S6 , and S4 are ON and the other switches and diodes are OFF, the inductor current is charging, as shown in Fig. 6(a). Under the condition that the inductance values of L1 and L2 are identical, the inductor voltage can be found as vL 1 = vL 2 = 0.5(vdc − vac ).

(1)

And the output voltage vac is calculated by vac = vdc M sin(ωt)

(2)

where vdc is the dc-link voltage, M is the modulation index, and ω is the angular frequency of the grid. For simplification, the impedance at the line frequency between neutral line and ground is neglected. From (1) and (2), the ground potential shown in Fig. 6(a) in the charging interval during positive grid half cycle can be expressed vEN1 = 0.5vdc [1 − (M sin(ωt))] .

(3)

In the freewheeling interval during the positive grid half cycle shown in Fig. 6(b), the S1 and S6 simultaneously turn OFF and S4 and D1 are ON. The voltages of the inductor L1 and L2 are given as vL 1 = vL 2 = −0.5vac .

(4)

Under the condition that the S1 and S6 share the dc-link voltage when they are simultaneously turned off, the voltage stress of the S6 can be found as vS 6 = 0.5vdc .

(5)

For simplification, the impedance at the line frequency between neutral line and ground is also neglected. From (2), (4), and (5), the ground potential shown in Fig. 6(b) in the freewheeling interval during positive grid half cycle can be expressed as vEN2 = 0.5vdc [1 − (M sin(ωt))] .

(6)

III. ASSOCIATED MULTILEVEL BOOTSTRAP POWER SUPPLY AND INTEGRATED GATE DRIVERS FOR THE PROPOSED INVERTER Although the proposed inverter has the distinctive advantages over the conventional full-bridge inverter, there are also some shortcomings associated with this method: two more active switches and their gate drivers and the individual power supplies. Multilevel bootstrap technology has been presented in the multilevel inverter [27]–[29]. The major technology issue of this kind of bootstrap circuit is its dependence on the power train topology and the corresponding PWM scheme. In this paper, we apply the technique to the proposed power circuit using the cross-leg connection for charging path. Such a cost-effective solution to power the high-side and midside gate drives for the proposed inverter using the bootstrap power supply technique is shown in Fig. 7. Four small capacitors Ca1 –Ca4 and diodes Da1 –Da4 are employed to transfer energy to the high-side and midside switches from an auxiliary dc voltage source Ea . Note that the energy of Ca1 cannot be transferred from Ca3 , which is in the same phase leg because the middle device S3 and its body diode are never turned on when S1 operates at high frequency, such that the cross-leg connections of the bootstrap circuit for the proposed inverter are necessary. As shown in Fig. 8(a), when the inverter output voltage is positive, the capacitor Ca4 is charging through Da4 at very PWM cycle since the low-side switch S6 in the same leg is turned on at high frequency. With the cross-leg connection, Da3 can be turned on before D1 is ON at very PWM cycle while S4 remains ON like what the high-side drive in the normal buck converter does, as shown in Fig. 8(b). Thus, energy of Ca4 can transfer to Ca1 through Da3 to turn ON the high-side switch S1 . The proposed cross-leg bootstrap power supply is preferred to the use of isolated auxiliary supply for each gate drive because of its compact size and compatibility with integrated chips. It makes the proposed inverter more appealing for PV ac-module applications. The high-side and middle-side MOSFETs in the same phase leg can be driven by one of the FAN7385 integrated circuits, as shown in Fig. 9.

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Fig. 10. Symmetric inverter-side inductors: (a) the equivalent electric circuit, (b) physical structure with toroidal core, and (c) physical structure with ETD core. Fig. 7.

Circuit diagram of the bootstrap power supply for the proposed inverter.

Fig. 11.

Fig. 8. Charging path of the bootstrap capacitors: (a) for the middle-side gate drive and (b) for the high-side gate drive.

Fig. 9. High-side and middle-side gate drivers using integrated chips FAN7385 for the proposed inverter.

the symmetrical windings of the split inductors share the same core to avoid the effect of the magnetic variation. In order to attenuate more switching ripple for the grid-side current, additional capacitor Cf and inductor Lg can be added to form a second-order filter, as shown in Fig. 11. The second design consideration is the current control strategy effect on the output filter design. The design needs to consider the position of feedback signals and the current loop compensation [30]–[33]. As shown in Fig. 11, by selecting the voltage at the filter capacitor vac and the current of the inverter-side inductor iac as the feedback signals with admittance feedforward compensation, the entire 2 LCL current control plant can be simplified as a first-order system under the condition that the capacitor Cf is small enough to be negligible [31], [32]. Fig. 11 shows the block diagram of the complete inverter. More detailed analysis about the controller design can be referred in [32]. The third design consideration is filter-parameters calculation, which can be determined by setting criteria on ripple current and filtering criteria [30]–[33]. The inverter-side inductance can be calculated based on the design criterion that the maximum magnitude of the peak-to-peak current ripple is less than 10%–20% of the rated output current Irated in the whole grid cycle. The peak-to-peak inductor current ripple can be derived as

IV. DESIGN CONSIDERATIONS

Δipk =

A. Output Filter The first consideration is the type of the output filter. The proposed design is to adopt two split inductors at the inverter output to allow equal voltage swing over two inductors so that the high-frequency voltage swing between the PV negative terminal and the grid ground can be reduced significantly if the inductance values are identical. The physical structure shown in Fig. 10 can minimize the difference of inductance because

Block diagram of the complete inverter.

(vdc − vac )DTS . L1 + L2

(7)

And the duty cycle D in the proposed inverter is calculated by D = M sin(ωt).

(8)

From (2), (7), and (8), the peak-to-peak ripple of the inductor current can be derived as 0.25vdc TS Δipk = · [1 − (1 − 2M sin ωt)2 ] (9) L1 + L2


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Fig. 12.

Experimental gating signals: (a) in the grid cycle and (b) in the PWM cycle.

Fig. 13.

Experimental switches voltage waveforms: (a) in the grid cycle and (b) in the PWM cycle.

where TS is the PWM switching period and 1 − 2M sin(ωt) = 0.

(10)

The maximum peak-to-peak ripple of the inductor current in the whole grid cycle is calculated by Δipk,m ax =

0.25vdc TS ≤ (10 ∼ 20)% · Irated . L1 + L2

(11)

In the proposed inverter, the inverter-side inductance then can be calculated with 0.25vdc TS (L1 + L2 ) ≥ . (12) (10 ∼ 20)% · Irated In the conventional full-bridge inverter using bipolar PWM scheme, the inverter-side inductance can be calculated with Lout ≥

0.5 · vdc TS . (10 ∼ 20)% · Irated

(13)

As a result, the inverter-side inductance in the proposed inverter is half that of the conventional full-bridge inverter using bipolar PWM scheme. The filter capacitor Cf is calculated in (14) by selecting the cutoff frequency fc of the (L1 + L2 ) and Cf , which is suggested to be between five times less than switching frequency and five times higher than the fundamental frequency [32]. Cf =

4π 2 fc2

1 . (L1 + L2 )

(14)

In our case, the range of acceptable capacitance Cf value is wide because the 30 kHz switching frequency is 500 times

the grid frequency. In order to increase the power factor, the capacitor value is further limited by the allowed reactive power absorbed at rated condition [31]. And the grid-side inductor Lg can be selected by the high-frequency current ripple attenuation requirements and limited by the condition that the resonant frequency should be in a range between ten times the line frequency and one-half of the switching frequency to avoid resonance problem [31]. B. Evaluation of Conduction Loss Reduction The proposed inverter with pure MOSFETs as active switches can significantly reduce the conduction losses as compared with the five-switch inverter shown in Fig. 3 using hybrid MOSFETs and IGBTs for the PV ac-module applications where power level is typically lower than 300 W. The following analyzes and compares the conduction loss of the individual device including the IGBT, MOSFET, diode, and the inverter-side inductor in the two inverters with the specified SPWM schemes. For simplification, the conduction voltage drop characteristics of the semiconductor devices can be given by IGBT: vce = Vt + iRce MOSFET: vds = iRds Diode: vak = Vf + iRak

(15) (16) (17)

where vds is MOSFET drain-source voltage drop, Rds is MOSFET drain-source on-drop resistance, vce is IGBT collector–emitter voltage drop, Vt is IGBT equivalent voltage

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drop under zero current condition, Rce is IGBT on-drop resistance; vak is diode anode-cathode voltage drop; Vf is diode equivalent voltage drop under zero current condition; Rak is diode on-drop resistance. While the duty ratio of each conducting device is respectively expressed by top and bottom switches: dtop−b ot (t) = M sin ωt middle switches: dm id (t) = 1 freewheeling diodes: ddio de (t) = 1 − M sin ωt

(18) (19) (20)

where ω is angular frequency and M is modulation index. And, the average conduction loss during half-line cycle can be calculated with 1 π p(t)d (ωt). (21) P = π 0 Then, the total conduction losses in the inverter shown in Fig. 3 are derived as shown (22) at the bottom of this page. And the total conduction losses in the proposed H6 inverter can be derived as shown (23) at the bottom of this page. The aforesaid application data are as follows: MOSFETs are FDB2710 with Rds = 0.044 Ω, diodes are CMR5U-04 with Vf = 0.8 V and Rak = 0.008 Ω, IGBTs is IXGA9289 with Vt = 1.5 V and Rce = 0.005 Ω, the rated output current peak value Im = 3.535 A, and the equivalent series resistance is 0.15 Ω. As a result, the proposed inverter with pure MOSFETs as active switches can reduce the conduction losses up to 51% compared with the five-switch inverter in our case. V. EXPERIMENTAL VERIFICATIONS A 300 W hardware prototype has been designed, fabricated and tested to verify the validity of the proposed inverter targeted at PV nonisolated ac-module application. The main devices S1 ∼ S6 are 250 V, 42.5 mΩ MOSFETs (FDB2710), the freewheeling diodes D1 and D2 are ultrafast diodes CMR5U04 (400 V/5 A), the auxiliary diodes Da1 ∼ Da4 are ultrafast diodes MURA160 (600 V/1 A), and the bootstrap capacitors Ca1 ∼ Ca4 are 1 μF, 25 V X7R. A 2 LCL filter shown in Fig. 10 (L1 + L2 = 1.6 mH, Cf = 0.68 μF, and Lg = 0.5 mH) is used as the output filter. The three pieces of dual-channel

high-side gate driver integrated chips FAN7385 with the proposed bootstrap power supply are designed to produce the matched gating signals for the six power MOSFETs. Specifications of the inverter are as follows: battery bank voltage Vdc = 180–200 V; output power Po = 300 W; grid voltage Vg ,rm s = 120 V; switching frequency fsw = 30 kHz. A digital control board with Spartan-3E FPGA is used as the sinusoidal output current controller. Fig. 10 describes the block diagram of the complete inverter. The experimental gating signals in the grid cycle and in PWM cycle are shown in Fig. 12(a) and (b), respectively. It can be seen that the experimental gating signals vG 1 , vG 6 , and vG 4 agree with the analysis results of the PWM scheme and the proposed bootstrap circuit works well by observing that the gate drive voltage level of the middle and top switches are kept constant during the grid cycle. Moreover, the gate drive signal vG 1 of the top switch in one leg and the vG 6 of the bottom switch in the other leg are matched with each other. The experimental switches voltage waveforms under 200 V dc-link conditions are shown in Fig. 13. The voltage stress of the top switch S1 and the middle switch S4 is 200 V, which is the same as the dc-link voltage. The voltage stress of the bottom switch S6 is about half of the dc-link voltage, as shown in Fig. 13(a). It can be seen from Fig. 13(b) that the switches S1 and S6 almost evenly share the dc-link voltage when they switch OFF simultaneously. Fig. 14 shows the experimental waveforms of the ground potential under full-load conditions. The testing results of the ground potential vEN agree with the (6). The high ground leakage current is avoided by observing that the high-frequency voltage of the ground potential is less than 10 Vrm s under fullload conditions. The experimental waveforms of the grid current under the 120 Vrm s grid voltage and full-load conditions are described in Fig. 15. This figure shows that the proposed inverter presents high power factor and low harmonic distortion. Fig. 16 illustrates the experimental results for efficiency under different dc-link voltages and output loads with 30-kHz switching frequency and 120 Vrm s ac voltage condition. Note that the presented efficiency diagram covers the losses of the dc–ac power train and the associated driver circuit, but it does

PFive−switch = PIGBT m id + 2PM OSFET top−b ot + PDIODE + PL 2 2 2 1 4M 4M 1 Im 1 2 2 2 Im Vt + Im Rce + 2 Im RDS − M + Im Rak − = (ESR) + Im V f + √ π 2 3π π 2 2 3π 2 = 6.15 W.

(22)

PH 6 = PM OSFET m id + 2PM OSFET top−b ot + PDIODE + PL 2 1 2 2 1 4M 1 Im 4M Im RDS + 2 I2m RDS − M + I2m Rak − = (ESR) + Im V f + √ 2 3π π 2 2 3π 2 = 3.01 W.

(23)


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bulky capacitors for a split dc link like what three-level inverters do; 4) 50% reduction of the output inductance as compared to that of the common full-bridge inverter with bipolar PWM switching; 5) low output ac current distortion because the PWM dead time for the proposed circuit is eliminated; and 6) the simple bootstrap power supply and the integrated gate drivers for the presented inverter. A 300 W hardware prototype has been designed, fabricated, and tested. Experimental results verify the validity of the novel circuit and show 98.1% European efficiency of the dc–ac power train and the associated driver circuit. Fig. 14. Experimental waveforms of the ground potential and ac output current under full-load conditions.

REFERENCES

Fig. 15. Experimental waveforms of the grid current under the 120 V rm s grid voltage and full-load conditions.

Fig. 16. Experimental results of efficiency as a function of the input voltage and the output power.

not include the power consumption of control subcircuits. The efficiency is higher with a lower Vdc voltage because that the diode conduction losses are reduced with a short freewheeling interval, and the top and bottom devices’ switching losses are also reduced with the low voltage. The maximum experimental efficiency of the prototype is 98.3% at about half of rated output power and its EU efficiency is 98.1%. VI. CONCLUSION This paper proposes a novel single-phase inverter with H6type configuration as a part of a wide input range, high efficiency, and long lifetime PV nonisolated 300 W ac module. Key features of the proposed circuit are as follows: 1) high efficiency over a wide load range by using MOSFETs for all active switches since their body diodes are naturally inactive; 2) low ground leakage current even if no transformer is used; 3) no need for

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Jih-Sheng (Jason) Lai (S’85–M’89–SM’93–F’07) received the M.S. and Ph.D. degrees in electrical engineering from the University of Tennessee, Knoxville, in 1985 and 1989, respectively. From 1980 to 1983, he was the Head of the Electrical Engineering Department of the Ming-Chi Institute of Technology, Taipei, Taiwan, where he initiated a power electronics program and received a grant from his college and a fellowship from the National Science Council to study abroad. In 1986, he became a staff member at the University of Tennessee, where he taught control systems and energy conversion courses. In 1989, he joined the Electric Power Research Institute (EPRI) Power Electronics Applications Center (PEAC), where he managed EPRI-sponsored power electronics research projects. From 1993, he worked with the Oak Ridge National Laboratory as the Power Electronics Lead Scientist, where he initiated a high-power electronics program and developed several novel high-power converters including multilevel converters and soft-switching inverters. In 1996, he joined Virginia Polytechnic Institute and State University. He is currently a Professor and the Director of the Future Energy Electronics Center. His research interests include high-efficiency power electronics conversions for high power and energy applications. He is the author or coauthor of more than 165 technical papers and two books and is the holder of 14 U.S. patents. Dr. Lai is the recipient of several distinctive awards including a Technical Achievement Award in Lockheed Martin Award Night, two IEEE Industry Applications Society (IAS) Conference Paper Awards from Industrial Power Converter Committee, and one IEEE Industrial Electronics Society (IECON) Best Paper Award. He chaired the 2000 IEEE Computers in Power Electronics (COMPEL). He was the Founding Chair for the 2001 IEEE/DOE Future Energy Challenge. He was the General Chair of the 2005 IEEE Applied Power Electronics Conference and Exposition (APEC).

Wensong Yu (M’07) received the M.S. degree from the Huazhong University of Science and Technology, Wuhan, China and the Ph.D. degree from the South China University of Technology, Guangzhou, China, in 1995 and 2000, respectively, both in mechanical and electrical engineering. In 2000, he was with the Emerson Network Power Co., Ltd., Shenzhen, China, where he was involved in the development of digital uninterruptible power supply projects. In 2004, he joined School of Electronic and Information Engineering, South China University of Technology. He is currently a Research Assistant Professor in the Bradley Department of Electrical and Computer Engineering, Future Energy Electronics Center, Virginia Polytechnic Institute and State University, Blacksburg, VA. He is author or coauthor of more than 20 technical papers and holds three patents. His research interest includes soft-switching power converter, grid-tied inverter, industrial power electronics, digital control applied to power electronics, and renewable energy power conditioning systems.

Christopher Hutchens received the B.S. and M.S. degrees in electrical engineering from Virginia Polytechnic Institute and State University, Blacksburg, VA, in 2008 and 2010, respectively, where he is currently working toward the Ph.D. degree. Since 2008, he has been a Graduate Research Assistant at the Future Energy Electronics Center (FEEC) at Virginia Polytechnic Institute and State University. His current research interests include low-power renewable energy systems and dc-grid technologies.

Hao Qian received the B.S and M.S. degrees in electrical engineering from Zhejiang University, Hangzhou, China, in 2003 and 2006, respectively, and is currently working toward the Ph.D. degree at Virginia Polytechnic Institute and State University, Blacksburg, VA. Since 2006, he has been a Graduate Research Assistant at the Future Energy Electronics Center (FEEC), Virginia Polytechnic Institute and State University. His current research interests include softswitching power converter and high-efficiency renewable energy power conditioning systems.