REVIEW OF SCIENTIFIC INSTRUMENTS 81, 054705 共2010兲

High frequency, high time resolution time-to-digital converter employing passive resonating circuits Giancarlo Ripamonti, Andrea Abba, and Angelo Geraci Department of Electronics, Politecnico di Milano, via C. Golgi 40, Milano 20133, Italy

共Received 16 February 2010; accepted 29 April 2010; published online 28 May 2010兲 A method for measuring time intervals accurate to the picosecond range is based on phase measurements of oscillating waveforms synchronous with their beginning and/or end. The oscillation is generated by triggering an LC resonant circuit, whose capacitance is precharged. By using high Q resonators and a final active quenching of the oscillation, it is possible to conjugate high time resolution and a small measurement time, which allows a high measurement rate. Methods for fast analysis of the data are considered and discussed with reference to computing resource requirements, speed, and accuracy. Experimental tests show the feasibility of the method and a time accuracy better than 4 ps rms. Methods aimed at further reducing hardware resources are finally discussed. © 2010 American Institute of Physics. 关doi:10.1063/1.3432002兴

I. INTRODUCTION

Precise measurement of time intervals is required in an increasing number of applications: time-of-flight measurements and time-correlated photon counting are just two interesting examples. Since the intrinsic resolution of sensors employed in these setups is nowadays in the 10 ps range, the instrument should possibly resolve much better than that. Furthermore, there is an increasing request of high repetition rates to which the instrumentation should keep up. Finally, new multichannel setups are built, which in turn call for simple, small, energy conscious setups. These everincreasing requirements can difficultly be met by the present measurement methods, and new ideas are to be considered. The well-established method for high-accuracy time interval measurements is the time-to-amplitude conversion 共TAC兲.1,2 In this measurement approach, a ramp voltage starts synchronously with the beginning of the time interval and is stopped at its end. The reached voltage is then digitized, which is proportional to the time interval. Such approach may have a resolution of less than 10 ps full width at half maximum but has also important disadvantages: first, in order to increase the resolution, the ramp should have a high slew rate, which limits the maximum time interval that can be measured due to saturation of the analog circuits and/or of the analog-to-digital converter 共ADC兲 共hybrid solutions employing counters are used to address this issue兲; second, the linearity of the ramp and of the ADC—especially the differential linearity—should be very high. This rules out employing standard high speed ADC components, requires additional linearizing circuitry, and limits the conversion speed. All these limits notwithstanding, at this time it is the solution of choice in high accuracy measurements.3 Another method which is the subject of a growing interest is the time-to-digital conversion 共TDC兲, which has the definite advantage of an easy integration in an integrated circuit.4,5 In one basic implementation, it consists of two digital delay lines periodically bridged by flip flops. The de0034-6748/2010/81共5兲/054705/7/$30.00

lay of the two lines from a given flip flop to the following is different. The 共start and stop兲 signals will therefore penetrate the two lines at different speeds. Looking at the flip flops, the first ones will be set by the propagating waves and the following will stay reset if the slower delay line 共which resets the flip flop兲 is fed by the start signal and the faster, which sets the flip lop, propagates the stop. From this, one can determine the original delay between the start and stop signals. Such method has definite disadvantages due to the temperature dependence of the delays, the difficulty of implementing matched delays, and has therefore a worse timing resolution than the TAC approach. However, it is possible to measure long time intervals with high accuracy by exploiting a coarse-fine approach, in which the fine measurement, obtained with the above-described method, is placed after simple counters, which perform a measurement of the number of clock cycles between the start and stop occurrences. In 2007, Panek and Prochazka6 proposed a new almost digital method based on a phase measurement. The start and stop occurrences are signaled by deltalike signals. Such signals are fed to surface acoustic wave 共SAW兲 filters which synchronously output signals oscillating at a well-defined frequency and lasting less than 1 s. In turn, these oscillating signals are sampled at a frequency slightly different of the SAW filters’ and digitized by fast ADCs. The sampled data will carry the signature of the phase difference between the ADC clock and the delta pulse input to the SAW filter. This phase difference can be extracted by using a suitable software running in a dedicated digital processor. The method is really highly accurate since it is able to resolve 1 ps rms. As far as we know, nothing is reported about the digital processor complexity, so the maximum rate at which this processor can work. Indeed, the analog part is fairly simple and perhaps it would be able to withstand high repetition rates. High speed ADCs are available off the shelf. The aim of this paper is to introduce a different method for generating the oscillating shape to be sampled and whose phase is the fine timing information. We used an LC tank,

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whose capacitor is precharged at a defined voltage and connected to the inductance when the event to be timed occurs. The possible advantage of this method is the ability to quench the oscillation after a few periods, thereby allowing the detection of events at a rate possibly higher than that achievable with a passive SAW filter. A single measurement channel is sufficient when the experiment can be made somehow synchronous with the system clock. For instance, a luminescence signal acquired through time correlated single photon timing is triggered by a laser pulse train synchronous with the ADC clock signal. In other cases, this is not possible, e.g., when the laser is working in mode locking and so its frequency and phase cannot be set by the system clock: for these cases both the start and stop events should be timed with respect to the system clock. This calls for instruments with two measurement channels. In such cases a possible choice is to delay the stop signal by a fixed amount of time 共e.g., through a long cable兲 and then use the same hardware for both start and stop. However, long cables are a problem especially in case of multichannel measurements; therefore two oscillating circuits and two ADC may be used, which doubles the necessary hardware resources. In order to minimize the hardware, we evaluated the case where two oscillating signals at different frequencies are fed to the same ADC and the software is left to evaluate both phases from the resulting signal. Of course, there is no advantage to increase the detectable number of events if the algorithms used to analyze the data cannot keep the pace. So, evaluating different algorithms for efficiency and accuracy is essential. Complex hardware increases the cost of the instrumentation and its power consumption and it can eventually limit the affordability of the method. So, efforts were spent in order to address this issue. In the following, we introduce the employed analog circuit 共Sec. II兲. We discuss the mathematical methods which can be used in order to obtain real-time operation with a reasonable hardware configuration and with a reasonable timing resolution, showing possible tradeoffs between the two requests 共Sec. III兲. We discuss the digital apparatus used for the first tests 共Sec. IV兲. Finally we show and analyze some experimental results 共Sec. V兲.

Rev. Sci. Instrum. 81, 054705 共2010兲

FIG. 1. Simplified schematic of the analog circuit.

shape lasts for a time sufficient to acquire some digitized samples; then the oscillation is quenched and the capacitor is recharged to the voltage V, ready for another measurement. This mechanism allows keeping the oscillations of high amplitude along the entire measurement time—so allowing good phase measurement accuracy—and, at the same time, decouples the need for high amplitude with the requirement of a fast dumping necessary for high repetition rates. Since the oscillating circuit is passive it is simpler, at least in principle, to keep the oscillation frequency stable. In fact, it is clear that any oscillation frequency variation impacts on the phase being its time derivative. Figure 2 shows the timing diagram of the switch control signals. In the charging period, only Sw1 is closed, the capacitor is being charged, and the inductance has no current flowing through it. This phase lasts for a time sufficient to completely charge C to Vcc. When the event to be timed occurs, first Sw1 opens, then Sw2 closes, and thus the oscillation begins. When the oscillation time is ended, Sw3 closes, the inductance is shunted, and the oscillation ends. Another cycle can begin. Since we were just testing the measurement approach, we did not optimize the circuit, so we employed standard analog switches to implement Sw1, Sw2, and Sw3. This led to some problems in the measurements, which will be discussed later. However, it is worth noting that the switches should not be identical. The resistance of Sw1 impacts on the time constant with which C is charged; however its stray

II. ANALOG SHAPING

The purpose of the analog circuits is to generate an oscillating waveform synchronous with the event to be timed. In the following, the event is considered to be the rising edge of some digital signal. We will not discuss how such a signal is generated and how to make it synchronous with the physical event to be timed since such problems are very application dependent and have been thoroughly addressed in the literature. The working principle of the circuit, which is shown in Fig. 1, is to use the digital edge as a trigger. The energy stored in the capacitor C, which is already charged at the stable voltage V, is allowed to discharge on the inductor L, thereby generating an oscillating cosinusoidal shape whose amplitude decreases with a 共low兲 dumping factor. This wave

FIG. 2. Timing diagram of the relevant signals.

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nonlinear capacitance is in parallel with C. The same happens for Sw3, whose resistance limits the quenching time of the oscillation. Switch Sw2 has the most impact on the oscillation. Its resistance adds to that of the inductor, and therefore it compromises the Q factor of the oscillation if too high. When the oscillation begins, the charge stored in capacitor C is rapidly shared with that of the stray capacitance of Sw3; therefore a voltage step occurs before the oscillation can begin. This in turn reduces the oscillation amplitude if the entire wave shape should fit within the dynamic range of the ADC. Means for clipping the voltage to keep the oscillation high enough can be used; however we did not employ such method. So again, space for further improvement of the circuit is present. The choice of the oscillation frequency depends primarily on the choice of the ADC sampling frequency; then one can wisely choose the values of L and C taking into account the stray capacitances and resistances of the switches. This circuit is followed by a shaper amplifier, whose purpose is to show theoretically infinite impedance to the LC tank, therefore keeping its Q factor high and to adapt the oscillator amplitude to the input dynamic range of the ADC. The noise introduced by the amplifier should be also considered. The choice of the frequency ratio between the LC tank and the ADC clock has a significant impact on the system performance. To clarify this point, remember that the phase accuracy will be high only when the measured amplitude of a given sample varies significantly with the phase : in other terms dV / d should be as high as possible. At a given frequency, the phase is proportional to the time; hence dV / dt should be high. Now, if the oscillation frequency is an integer multiple of half the sampling frequency, there is the chance that the sampling times all happen at the maxima of the cosinusoid, where the time derivative of the signal is zero; therefore the phase resolution will be very poor. On the contrary, by correctly choosing the ratio, one can make it possible that at least some of the sampling times happen on the wave nodes 共where the derivative is high as well as the phase resolution兲 for any value of the phase, i.e., of the occurrence time. Since the oscillation amplitude reduces exponentially with time, so does the derivative; therefore the final requirement is that for any arrival time, there should be some of the first samples with near zero amplitude. Another word of attention is due to the ADC specifications. In the TAC method, the linearity requirements of the ADC are very high, at least in TCPC experiments. In fact, the measurement result is the histogram of the arrival times. Each measured time is classified in a given bin and therefore a measurement distortion occurs if the amplitude of the bins is not constant: the bigger the bin, the higher the probability of classifying a random delay in it. So, high differential linearity is required on the order of 0.01 least significant bit 共LSB兲, which is a couple orders of magnitude better than that achievable by integrated high frequency ADCs. However, the present measurement estimates the phase by using a certain number of sampled voltages, which intrinsically introduce an averaging of the sampled values to obtain the phase estimation. So, if the sampled voltages are sufficiently dispersed in

the ADC dynamic range, an averaging also in the bins amplitude occurs, and the overall measurement linearity is much increased.7 Again, this can be achieved by wisely choosing the ratio of oscillation and ADC clock frequency. It is also worth noting that the oscillation frequency may be even higher than the sampling frequency. In fact, since the signal shape is known except for its occurrence time, the sampling theorem does not apply in this situation. Although it would seem interesting at a first sight to increase the oscillation frequency since time derivatives are proportionally increased, it should be noted that the overall duration of the signal would unfortunately be reduced, if the quality factor Q cannot be increased by an improved analog design of the LC tank. This is of course detrimental to the measurement accuracy since the number of significant samples would be reduced accordingly.

III. ANALYSIS METHOD

When it comes to the numerical methods employed to obtain the phase, many conflicting requirements have to be considered. A first problem relates with the measurement accuracy, which should be as high as possible. In order to address this result, it is wise to consider numerical methods similar to least mean squares 共LMS兲 to fit at best an experimental reference curve with the measurement data. Of course this requires long times, which however can be reduced if a good starting point of the iterations can be found by using a simple coarse procedure—remember that unfortunately the LMS method requires iterations when an optimum fit on the x axis is required. Such numerical method, albeit very accurate, requires significant hardware resources. We have addressed the problem of optimizing the time needed to perform a LMS routine in a field programmable gate array 共FPGA兲.8 The LMS method will be considered in the measurements as well as a method which is less accurate but also less hungry of computing resources. Such lower precision method was also devised, which can also be used for obtaining the first estimate of the phase for the LMS method. Consider the amplitude measurement obtained at a given clock period. It will provide an estimate of the phase with respect to a reference curve with some inaccuracy. Such inaccuracy will depend—in the theoretical case of no added electronic noise—on the voltage amplitude corresponding to a single ADC bin and on the time derivative of the reference curve at that time. Many such measurements can be obtained by using the voltage measurements at the various clock times. A final estimate of the phase will be obtained by using a weighted average of the phase estimates at each sampling time, where the weights are the absolute values of the time derivatives at each sampling point. One can derive a mask for the amplitude values against the time: if the sample lies within the mask limits, the corresponding time estimate is used; otherwise it will be discarded since the information is too raw and possibly biased by inaccuracies of the original voltage amplitude of the signal. In practice, the samples giving the best time estimates are the first occurring,

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Rev. Sci. Instrum. 81, 054705 共2010兲

Ripamonti, Abba, and Geraci

Amplitude [a.u.]

1 / Time resolution [a.u.]

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Time [ns] FIG. 3. 共Color online兲 Rationale of the simplified timing method: samples taken from each event are discarded if they occur outside the acceptance mask. The mask is obtained by considering the time derivative of the signal 共see text兲. The vertical axis is the digital value of the sampled data.

provided that their voltage amplitude is low 共see Fig. 3兲. We have carried out simulations in order to foresee the best ratio between the ADC sampling frequency f ADC and the wave shape oscillation frequency f osc. A typical result is shown in Fig. 4. The curve is obtained as follows: for each k = f ADC / f osc value, simulations are run at various phase values to evaluate the rms accuracy of the phase estimate. Then, the worst rms value is considered for that k value since it will be the limiting accuracy value of a measurement carried out with those parameters. Of course, various curves are obtained by changing the quality factor Q of the oscillating circuit and by using different numbers of samples. However, there is a limiting value of samples after which the estimates’ accuracy will not increase since all the added samples will have a low derivative, so they will enter the average with a low weight. In Fig. 4, many valleys are found, which is the signature of the beatings between the two frequencies involved. Both time estimate methods require acquiring a reference curve, which should also be sufficiently noiseless. Therefore averaging is required. At this time, acquiring this reference curve is a definite drawback of the method since it requires time and specific instrumentation, i.e., very accurate delay generators. It is possible to use the same ADC for measuring two or more overlapping wave shapes, especially in the case where their frequencies are different. In such case, the coarse method is more complicated to implement and it also has a lower accuracy; however, using a lower number of ADCs may reduce the overall cost of the apparatus, in particular when the measurement rate is not high; therefore respecting real time computing requirements is not an issue. Using a single ADC for two measurement channels is especially simple since summing the signals can be easily done by employing the two standard inputs of high speed differential input ADCs. Still, a lower time resolution is to be expected since the sum of the two signals should stay within the ADC dynamic range. Given that there is no a priori phase relationship between the two signals, the two of them should present

Sampling frequency/Oscillation frequency FIG. 4. 共Color online兲 Result of the analysis of the achievable time resolution in function of the ratio of the sampling frequency to the oscillation frequency. The higher the value 共in arbitrary units兲, the better the time resolution. The oscillating circuit is supposed to have Q = 30. Notice that since the shape of the curve is known a priori, it is possible to exceed the Nyquist limit for the signal bandwidth.

peak amplitude lower than the one that is allowed when just a single signal is sampled. Keeping the oscillation frequency stable is particularly important. In fact, consider an oscillation occurring at a frequency f osc + ⌬f. As time passes, the phase estimated at each measurement time will increase by a quantity 2⌬fT, where T is the measurement time. The averaging of the phase estimates at the various sampling times will generate a phase— thereby a time—error, which will be random if ⌬f is not constant. Unfortunately this problem is significant in our setup. Although we chose thermally stable capacitors and inductors, the stray 共and somewhat nonlinear兲 capacitances of the analog switches modify the oscillation frequency enough to be the limiting factor for the achievable time accuracy. We introduced therefore a frequency measurement stage in order to compensate online for the randomly varying oscillation frequency. The method requires to run a measurement at a well specified phase after each 共or after some兲 event. To fix the ideas, consider running a dummy measurement by triggering the oscillation precisely at the rising edge of the sampling clock f ADC. Now a least squares or some other method can be used to extract the frequency estimate since the phase is already known. Such frequency estimate is then used. In fact, the time axis of each measurement stream is shrunk or expanded accordingly in order to maintain the correct ratio of k = f ADC / f osc. This is not a perfect compensation but it comes out to be enough to reduce the frequency wandering effect to a negligible value. This online frequency compensation comes at a price. In fact, it is necessary to perform dummy measurements, which clearly represent a dead time for the real measurements. We believe that redesigning the analog section by using suitable electronic components, especially the switches, could mitigate the effect and eventually allow to avoid using this compensation technique.

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V. EXPERIMENTAL RESULTS

In this section we show preliminary results obtained with our simplified setup. Their purpose is not to assess the maximum rate at which the system can operate 共which is, at this time, limited by the digital resources available兲 but just to show that the analog circuit we employed is suitable to the purpose, and is, therefore, able to achieve a picosecondrange resolution. The system ADC 共Analog Devices AD9244兲 was operated at 62.5 MHz clock frequency. It digitizes with 14 bit resolution. The system clock was used as a beginning time for the time interval measurement. The same clock was then delayed by using a homemade circuit based on the Analog Devices AD9513 device. Of course, the delay should be very stable in order to allow measurements with picosecond resolution without introducing measurement degradation. In fact, with a previous version of the delay circuit, the results were much worse. For this reason, in some measurements we employed cables for generating the delay, in order to verify if the jitter of the delay circuit was not too high to correctly measure the instrument resolution. It was not possible, for obvious reasons, to perform the entire measurement set with delaying cables. The analog circuit generated an oscillating waveform having 25 MHz frequency. We obtained a Q factor of 30 which was considered sufficient. A number of samples were acquired for each event, and a set of 100 measurements was done for each delay, in order to assess the linearity 共i.e., the deviation of the average measurement from the theoretical value兲 and resolution 共i.e., the rms value of the measurement estimate with respect to the average兲. Such measurements

Estimation std [ps]

Preset Delay [ns]

Preset Delay [ns]

(c)

Estimation std [ps]

In our prototype, we limited the digital resources to a minimum. This meant to control the ADC, to acquire the relevant samples for each measurement, and to send the relevant data stream to a personal computer 共PC兲 for phase evaluation. It is not the purpose of this paper to discuss the best digital hardware to allow real time measurements at high rate, which is a nontrivial task. However, it is possible to foresee the most important issues. First, the necessity of a low noise reference curve calibrated for small delays, against which the phase should be measured. This means a relatively long file and therefore a somewhat long LMS procedure, despite the use of only a few samples for the measurement. Second, as already pointed out, the necessity of an iterative procedure. Third, and most important, the necessity to operate real time, which can be a problem for many experiments, where the rate can be as high as some millions events per second. The choice of operating with a digital signal processor 共DSP兲, while interesting as for flexibility, does not seem the best, except for ancillary tasks. On the contrary, using a FPGA approach seems to be more promising.8

Estimation std [ps]

IV. DIGITAL RESOURCES

Preset Delay [ns]

FIG. 5. Experimental results of the achievable rms resolution in function of the phase of the trigger event to the sampling comb and using the first 共a兲 15, 共b兲 two, and 共c兲 four samples. Note the different vertical scales.

were repeated for a significant number of delays to generate the curves shown in the following. A small FPGA device 共Xilinx Spartan 3兲 was used to put the data stream in local memory and successively to send the stream to the host PC. A first test was done by using 15 samples 关see Fig. 5共a兲兴. 100 measurements were done for each delay, and the resulting rms error, plotted in the figure, is shown to be always lower than 4 ps, independent of the delay or, better, of the phase between the sampling comb and the event. By using a reduced number of samples, 2 or 4, respectively, in the same experiment, one gets the results shown in Figs. 5共b兲 and 5共c兲, respectively. Using only the first two samples degrades the resolution especially when the delay to be measured is small; on the contrary using the four first samples in the time estimate does not degrade significantly the resolution, which worsens to 4.6 ps rms but reduces significantly both measurement time and mathematical burden. In a second measurement set, we deliberately changed the oscillation frequency of the analog circuit by changing the setup temperature. The oscillation frequency changes of 150 and 800 ppm were considered. Again 100 measurements

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Ripamonti, Abba, and Geraci

(a) (a)

Deviation [ps]

Deviation [ps]

(b)(b)

Preset Delay [ns]

Preset Delay [ns] (c)

Deviation [ps]

Deviation [ps]

(d)

Preset Delay [ns]

Preset Delay [ns]

FIG. 6. Deviation of the time estimate due to a thermal drift of the oscillation frequency of 150 ppm, 共a兲 before and 共b兲 after frequency compensation and due to a thermal drift of the oscillation frequency of 800 ppm, 共c兲 before and 共d兲 after frequency compensation. The first eight samples were used. Note the significantly different vertical scales.

Estimation std [ps]

(a)

Preset Delay [ns]

delay. In Fig. 8, the histogram of the resulting delay estimates is shown. Apart for an 18 ps systematic error, the estimates are reasonably Gaussian and do not show evident misshapes, given the low statistics. Again, by employing the frequency correction procedure, the systematic error was reduced to a minimum 共see Fig. 9兲.

VI. CONCLUSIONS

We have shown that the method of measuring time intervals by sampling the dumped oscillations of an LC passive network and determining from that the phase between the oscillating shape and the sampling clock is capable of picosecond resolution. Using a passive discrete network allows us to quench rapidly the oscillation after a few periods: this feature could allow high measurement repetition rates. While in our experiments we used a simple circuit which makes use

(b)

Estimation std [ps]

were done for each delay and the average value of the difference between the measured and set delays was plotted. The measurements were then repeated by employing the frequency compensation procedure described before. The results are shown in Fig. 6 for 150 and 800 ppm frequency deviations. The first eight samples were employed. Without frequency compensation, the average deviations are on the order of 3.5 and 5.5 ps, respectively; after compensation the residual error is less than 0.5 ps and less than 1 ps in the two cases, therefore, lower than the rms resolution, which is shown in Fig. 7. Results worsen when using more than eight samples in this experiment since compensating the oscillation frequency becomes more difficult when a longer time span is considered. Notice also that in both cases, the rms resolution is better than that obtained in the first experiment with 15 samples. This suggests that the last samples of the measurement carry more errors than information anyway and they would be better disregarded in any case. Finally, we used a cable for generating a minimum jitter

Preset Delay [ns]

FIG. 7. Rms resolution of the measurements shown 共a兲 in Fig. 6共b兲 and 共b兲 in Fig. 6共d兲.

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Rev. Sci. Instrum. 81, 054705 共2010兲

Ripamonti, Abba, and Geraci

Counts

054705-7

Estimated delay values [ns] FIG. 8. Results for a single measurement taken with a delay set by a coaxial cable. The frequency shift is 150 ppm. Notice the systematic error much higher than the measurement uncertainty.

of standard analog switches, a more refined circuit would eliminate or at least greatly reduce such drawbacks as frequency wandering or limited dynamic range of the oscillation compared to the ADC dynamics.

Two issues are still open and need to be solved in order to allow the use of this method as an alternative to more standard TDC or TAC setups: they are the need for a reference curve and the important amount of digital signal processing, which is necessary to derive the delay value from the raw ADC output data. We have proposed in this paper some suggestions to minimize this second problem but it has to be further investigated and better solutions should be devised. In order to minimize the 共analog兲 circuitry, many signals may be sampled by the same ADC with some price to pay in the analysis complication and in the achievable resolution: however, this possibility allows foreseeing multichannel instruments with reduced hardware need when ultrahigh time resolution is not required. ACKNOWLEDGMENTS

The authors wish to thank S. Caramanno and P. Torretta for discussions and assistance in the experiments. M. Bertolaccini and S. Cova, Nucl. Instrum. Methods 121, 547 共1974兲. D. Resnati, I. Rech, A. Gallivanoni, and M. Ghioni, Rev. Sci. Instrum. 80, 086102 共2009兲. 3 W. Becker, Advanced Time-Correlated Single Photon Counting Techniques 共Springer, Berlin, 2005兲. 4 D. M. Gersbach, Y. Maruyama, E. Labonne, J. Richardson, R. Walker, L. Grant, R. Henderson, F. Borghetti, D. Stoppa, and E. Charbon, IEEE European Solid-State Device Conference 共ESSCIRC兲, Athens, Greece, 196 共2009兲. 5 W. C. Niclass, C. Favi, T. Kluter, M. Gersbach, and E. Charbon, IEEE J. Solid-State Circuits 43, 2977 共2008兲. 6 P. Panek and I. Prochazka, Rev. Sci. Instrum. 78, 094701 共2007兲. 7 G. Ripamonti, M. Zambusi, R. Spigarolo, D. Santo, and C. Samori, IEEE Trans. Nucl. Sci. 42, 693 共1995兲. 8 A. Abba, A. Manenti, A. Suardi, and A. Geraci, Engineering of Reconfigurable Systems and Algorithms 共ERSA, Las Vegas, 2009兲. 1

Counts

2

Estimated delay values [ns] FIG. 9. Same as Fig. 8 but after frequency compensation. The systematic error is eliminated.

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High frequency, high time resolution time-to-digital converter employing passive resonating circuits Giancarlo Ripamonti, Andrea Abba, and Angelo Geraci Department of Electronics, Politecnico di Milano, via C. Golgi 40, Milano 20133, Italy

共Received 16 February 2010; accepted 29 April 2010; published online 28 May 2010兲 A method for measuring time intervals accurate to the picosecond range is based on phase measurements of oscillating waveforms synchronous with their beginning and/or end. The oscillation is generated by triggering an LC resonant circuit, whose capacitance is precharged. By using high Q resonators and a final active quenching of the oscillation, it is possible to conjugate high time resolution and a small measurement time, which allows a high measurement rate. Methods for fast analysis of the data are considered and discussed with reference to computing resource requirements, speed, and accuracy. Experimental tests show the feasibility of the method and a time accuracy better than 4 ps rms. Methods aimed at further reducing hardware resources are finally discussed. © 2010 American Institute of Physics. 关doi:10.1063/1.3432002兴

I. INTRODUCTION

Precise measurement of time intervals is required in an increasing number of applications: time-of-flight measurements and time-correlated photon counting are just two interesting examples. Since the intrinsic resolution of sensors employed in these setups is nowadays in the 10 ps range, the instrument should possibly resolve much better than that. Furthermore, there is an increasing request of high repetition rates to which the instrumentation should keep up. Finally, new multichannel setups are built, which in turn call for simple, small, energy conscious setups. These everincreasing requirements can difficultly be met by the present measurement methods, and new ideas are to be considered. The well-established method for high-accuracy time interval measurements is the time-to-amplitude conversion 共TAC兲.1,2 In this measurement approach, a ramp voltage starts synchronously with the beginning of the time interval and is stopped at its end. The reached voltage is then digitized, which is proportional to the time interval. Such approach may have a resolution of less than 10 ps full width at half maximum but has also important disadvantages: first, in order to increase the resolution, the ramp should have a high slew rate, which limits the maximum time interval that can be measured due to saturation of the analog circuits and/or of the analog-to-digital converter 共ADC兲 共hybrid solutions employing counters are used to address this issue兲; second, the linearity of the ramp and of the ADC—especially the differential linearity—should be very high. This rules out employing standard high speed ADC components, requires additional linearizing circuitry, and limits the conversion speed. All these limits notwithstanding, at this time it is the solution of choice in high accuracy measurements.3 Another method which is the subject of a growing interest is the time-to-digital conversion 共TDC兲, which has the definite advantage of an easy integration in an integrated circuit.4,5 In one basic implementation, it consists of two digital delay lines periodically bridged by flip flops. The de0034-6748/2010/81共5兲/054705/7/$30.00

lay of the two lines from a given flip flop to the following is different. The 共start and stop兲 signals will therefore penetrate the two lines at different speeds. Looking at the flip flops, the first ones will be set by the propagating waves and the following will stay reset if the slower delay line 共which resets the flip flop兲 is fed by the start signal and the faster, which sets the flip lop, propagates the stop. From this, one can determine the original delay between the start and stop signals. Such method has definite disadvantages due to the temperature dependence of the delays, the difficulty of implementing matched delays, and has therefore a worse timing resolution than the TAC approach. However, it is possible to measure long time intervals with high accuracy by exploiting a coarse-fine approach, in which the fine measurement, obtained with the above-described method, is placed after simple counters, which perform a measurement of the number of clock cycles between the start and stop occurrences. In 2007, Panek and Prochazka6 proposed a new almost digital method based on a phase measurement. The start and stop occurrences are signaled by deltalike signals. Such signals are fed to surface acoustic wave 共SAW兲 filters which synchronously output signals oscillating at a well-defined frequency and lasting less than 1 s. In turn, these oscillating signals are sampled at a frequency slightly different of the SAW filters’ and digitized by fast ADCs. The sampled data will carry the signature of the phase difference between the ADC clock and the delta pulse input to the SAW filter. This phase difference can be extracted by using a suitable software running in a dedicated digital processor. The method is really highly accurate since it is able to resolve 1 ps rms. As far as we know, nothing is reported about the digital processor complexity, so the maximum rate at which this processor can work. Indeed, the analog part is fairly simple and perhaps it would be able to withstand high repetition rates. High speed ADCs are available off the shelf. The aim of this paper is to introduce a different method for generating the oscillating shape to be sampled and whose phase is the fine timing information. We used an LC tank,

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whose capacitor is precharged at a defined voltage and connected to the inductance when the event to be timed occurs. The possible advantage of this method is the ability to quench the oscillation after a few periods, thereby allowing the detection of events at a rate possibly higher than that achievable with a passive SAW filter. A single measurement channel is sufficient when the experiment can be made somehow synchronous with the system clock. For instance, a luminescence signal acquired through time correlated single photon timing is triggered by a laser pulse train synchronous with the ADC clock signal. In other cases, this is not possible, e.g., when the laser is working in mode locking and so its frequency and phase cannot be set by the system clock: for these cases both the start and stop events should be timed with respect to the system clock. This calls for instruments with two measurement channels. In such cases a possible choice is to delay the stop signal by a fixed amount of time 共e.g., through a long cable兲 and then use the same hardware for both start and stop. However, long cables are a problem especially in case of multichannel measurements; therefore two oscillating circuits and two ADC may be used, which doubles the necessary hardware resources. In order to minimize the hardware, we evaluated the case where two oscillating signals at different frequencies are fed to the same ADC and the software is left to evaluate both phases from the resulting signal. Of course, there is no advantage to increase the detectable number of events if the algorithms used to analyze the data cannot keep the pace. So, evaluating different algorithms for efficiency and accuracy is essential. Complex hardware increases the cost of the instrumentation and its power consumption and it can eventually limit the affordability of the method. So, efforts were spent in order to address this issue. In the following, we introduce the employed analog circuit 共Sec. II兲. We discuss the mathematical methods which can be used in order to obtain real-time operation with a reasonable hardware configuration and with a reasonable timing resolution, showing possible tradeoffs between the two requests 共Sec. III兲. We discuss the digital apparatus used for the first tests 共Sec. IV兲. Finally we show and analyze some experimental results 共Sec. V兲.

Rev. Sci. Instrum. 81, 054705 共2010兲

FIG. 1. Simplified schematic of the analog circuit.

shape lasts for a time sufficient to acquire some digitized samples; then the oscillation is quenched and the capacitor is recharged to the voltage V, ready for another measurement. This mechanism allows keeping the oscillations of high amplitude along the entire measurement time—so allowing good phase measurement accuracy—and, at the same time, decouples the need for high amplitude with the requirement of a fast dumping necessary for high repetition rates. Since the oscillating circuit is passive it is simpler, at least in principle, to keep the oscillation frequency stable. In fact, it is clear that any oscillation frequency variation impacts on the phase being its time derivative. Figure 2 shows the timing diagram of the switch control signals. In the charging period, only Sw1 is closed, the capacitor is being charged, and the inductance has no current flowing through it. This phase lasts for a time sufficient to completely charge C to Vcc. When the event to be timed occurs, first Sw1 opens, then Sw2 closes, and thus the oscillation begins. When the oscillation time is ended, Sw3 closes, the inductance is shunted, and the oscillation ends. Another cycle can begin. Since we were just testing the measurement approach, we did not optimize the circuit, so we employed standard analog switches to implement Sw1, Sw2, and Sw3. This led to some problems in the measurements, which will be discussed later. However, it is worth noting that the switches should not be identical. The resistance of Sw1 impacts on the time constant with which C is charged; however its stray

II. ANALOG SHAPING

The purpose of the analog circuits is to generate an oscillating waveform synchronous with the event to be timed. In the following, the event is considered to be the rising edge of some digital signal. We will not discuss how such a signal is generated and how to make it synchronous with the physical event to be timed since such problems are very application dependent and have been thoroughly addressed in the literature. The working principle of the circuit, which is shown in Fig. 1, is to use the digital edge as a trigger. The energy stored in the capacitor C, which is already charged at the stable voltage V, is allowed to discharge on the inductor L, thereby generating an oscillating cosinusoidal shape whose amplitude decreases with a 共low兲 dumping factor. This wave

FIG. 2. Timing diagram of the relevant signals.

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nonlinear capacitance is in parallel with C. The same happens for Sw3, whose resistance limits the quenching time of the oscillation. Switch Sw2 has the most impact on the oscillation. Its resistance adds to that of the inductor, and therefore it compromises the Q factor of the oscillation if too high. When the oscillation begins, the charge stored in capacitor C is rapidly shared with that of the stray capacitance of Sw3; therefore a voltage step occurs before the oscillation can begin. This in turn reduces the oscillation amplitude if the entire wave shape should fit within the dynamic range of the ADC. Means for clipping the voltage to keep the oscillation high enough can be used; however we did not employ such method. So again, space for further improvement of the circuit is present. The choice of the oscillation frequency depends primarily on the choice of the ADC sampling frequency; then one can wisely choose the values of L and C taking into account the stray capacitances and resistances of the switches. This circuit is followed by a shaper amplifier, whose purpose is to show theoretically infinite impedance to the LC tank, therefore keeping its Q factor high and to adapt the oscillator amplitude to the input dynamic range of the ADC. The noise introduced by the amplifier should be also considered. The choice of the frequency ratio between the LC tank and the ADC clock has a significant impact on the system performance. To clarify this point, remember that the phase accuracy will be high only when the measured amplitude of a given sample varies significantly with the phase : in other terms dV / d should be as high as possible. At a given frequency, the phase is proportional to the time; hence dV / dt should be high. Now, if the oscillation frequency is an integer multiple of half the sampling frequency, there is the chance that the sampling times all happen at the maxima of the cosinusoid, where the time derivative of the signal is zero; therefore the phase resolution will be very poor. On the contrary, by correctly choosing the ratio, one can make it possible that at least some of the sampling times happen on the wave nodes 共where the derivative is high as well as the phase resolution兲 for any value of the phase, i.e., of the occurrence time. Since the oscillation amplitude reduces exponentially with time, so does the derivative; therefore the final requirement is that for any arrival time, there should be some of the first samples with near zero amplitude. Another word of attention is due to the ADC specifications. In the TAC method, the linearity requirements of the ADC are very high, at least in TCPC experiments. In fact, the measurement result is the histogram of the arrival times. Each measured time is classified in a given bin and therefore a measurement distortion occurs if the amplitude of the bins is not constant: the bigger the bin, the higher the probability of classifying a random delay in it. So, high differential linearity is required on the order of 0.01 least significant bit 共LSB兲, which is a couple orders of magnitude better than that achievable by integrated high frequency ADCs. However, the present measurement estimates the phase by using a certain number of sampled voltages, which intrinsically introduce an averaging of the sampled values to obtain the phase estimation. So, if the sampled voltages are sufficiently dispersed in

the ADC dynamic range, an averaging also in the bins amplitude occurs, and the overall measurement linearity is much increased.7 Again, this can be achieved by wisely choosing the ratio of oscillation and ADC clock frequency. It is also worth noting that the oscillation frequency may be even higher than the sampling frequency. In fact, since the signal shape is known except for its occurrence time, the sampling theorem does not apply in this situation. Although it would seem interesting at a first sight to increase the oscillation frequency since time derivatives are proportionally increased, it should be noted that the overall duration of the signal would unfortunately be reduced, if the quality factor Q cannot be increased by an improved analog design of the LC tank. This is of course detrimental to the measurement accuracy since the number of significant samples would be reduced accordingly.

III. ANALYSIS METHOD

When it comes to the numerical methods employed to obtain the phase, many conflicting requirements have to be considered. A first problem relates with the measurement accuracy, which should be as high as possible. In order to address this result, it is wise to consider numerical methods similar to least mean squares 共LMS兲 to fit at best an experimental reference curve with the measurement data. Of course this requires long times, which however can be reduced if a good starting point of the iterations can be found by using a simple coarse procedure—remember that unfortunately the LMS method requires iterations when an optimum fit on the x axis is required. Such numerical method, albeit very accurate, requires significant hardware resources. We have addressed the problem of optimizing the time needed to perform a LMS routine in a field programmable gate array 共FPGA兲.8 The LMS method will be considered in the measurements as well as a method which is less accurate but also less hungry of computing resources. Such lower precision method was also devised, which can also be used for obtaining the first estimate of the phase for the LMS method. Consider the amplitude measurement obtained at a given clock period. It will provide an estimate of the phase with respect to a reference curve with some inaccuracy. Such inaccuracy will depend—in the theoretical case of no added electronic noise—on the voltage amplitude corresponding to a single ADC bin and on the time derivative of the reference curve at that time. Many such measurements can be obtained by using the voltage measurements at the various clock times. A final estimate of the phase will be obtained by using a weighted average of the phase estimates at each sampling time, where the weights are the absolute values of the time derivatives at each sampling point. One can derive a mask for the amplitude values against the time: if the sample lies within the mask limits, the corresponding time estimate is used; otherwise it will be discarded since the information is too raw and possibly biased by inaccuracies of the original voltage amplitude of the signal. In practice, the samples giving the best time estimates are the first occurring,

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Amplitude [a.u.]

1 / Time resolution [a.u.]

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Time [ns] FIG. 3. 共Color online兲 Rationale of the simplified timing method: samples taken from each event are discarded if they occur outside the acceptance mask. The mask is obtained by considering the time derivative of the signal 共see text兲. The vertical axis is the digital value of the sampled data.

provided that their voltage amplitude is low 共see Fig. 3兲. We have carried out simulations in order to foresee the best ratio between the ADC sampling frequency f ADC and the wave shape oscillation frequency f osc. A typical result is shown in Fig. 4. The curve is obtained as follows: for each k = f ADC / f osc value, simulations are run at various phase values to evaluate the rms accuracy of the phase estimate. Then, the worst rms value is considered for that k value since it will be the limiting accuracy value of a measurement carried out with those parameters. Of course, various curves are obtained by changing the quality factor Q of the oscillating circuit and by using different numbers of samples. However, there is a limiting value of samples after which the estimates’ accuracy will not increase since all the added samples will have a low derivative, so they will enter the average with a low weight. In Fig. 4, many valleys are found, which is the signature of the beatings between the two frequencies involved. Both time estimate methods require acquiring a reference curve, which should also be sufficiently noiseless. Therefore averaging is required. At this time, acquiring this reference curve is a definite drawback of the method since it requires time and specific instrumentation, i.e., very accurate delay generators. It is possible to use the same ADC for measuring two or more overlapping wave shapes, especially in the case where their frequencies are different. In such case, the coarse method is more complicated to implement and it also has a lower accuracy; however, using a lower number of ADCs may reduce the overall cost of the apparatus, in particular when the measurement rate is not high; therefore respecting real time computing requirements is not an issue. Using a single ADC for two measurement channels is especially simple since summing the signals can be easily done by employing the two standard inputs of high speed differential input ADCs. Still, a lower time resolution is to be expected since the sum of the two signals should stay within the ADC dynamic range. Given that there is no a priori phase relationship between the two signals, the two of them should present

Sampling frequency/Oscillation frequency FIG. 4. 共Color online兲 Result of the analysis of the achievable time resolution in function of the ratio of the sampling frequency to the oscillation frequency. The higher the value 共in arbitrary units兲, the better the time resolution. The oscillating circuit is supposed to have Q = 30. Notice that since the shape of the curve is known a priori, it is possible to exceed the Nyquist limit for the signal bandwidth.

peak amplitude lower than the one that is allowed when just a single signal is sampled. Keeping the oscillation frequency stable is particularly important. In fact, consider an oscillation occurring at a frequency f osc + ⌬f. As time passes, the phase estimated at each measurement time will increase by a quantity 2⌬fT, where T is the measurement time. The averaging of the phase estimates at the various sampling times will generate a phase— thereby a time—error, which will be random if ⌬f is not constant. Unfortunately this problem is significant in our setup. Although we chose thermally stable capacitors and inductors, the stray 共and somewhat nonlinear兲 capacitances of the analog switches modify the oscillation frequency enough to be the limiting factor for the achievable time accuracy. We introduced therefore a frequency measurement stage in order to compensate online for the randomly varying oscillation frequency. The method requires to run a measurement at a well specified phase after each 共or after some兲 event. To fix the ideas, consider running a dummy measurement by triggering the oscillation precisely at the rising edge of the sampling clock f ADC. Now a least squares or some other method can be used to extract the frequency estimate since the phase is already known. Such frequency estimate is then used. In fact, the time axis of each measurement stream is shrunk or expanded accordingly in order to maintain the correct ratio of k = f ADC / f osc. This is not a perfect compensation but it comes out to be enough to reduce the frequency wandering effect to a negligible value. This online frequency compensation comes at a price. In fact, it is necessary to perform dummy measurements, which clearly represent a dead time for the real measurements. We believe that redesigning the analog section by using suitable electronic components, especially the switches, could mitigate the effect and eventually allow to avoid using this compensation technique.

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V. EXPERIMENTAL RESULTS

In this section we show preliminary results obtained with our simplified setup. Their purpose is not to assess the maximum rate at which the system can operate 共which is, at this time, limited by the digital resources available兲 but just to show that the analog circuit we employed is suitable to the purpose, and is, therefore, able to achieve a picosecondrange resolution. The system ADC 共Analog Devices AD9244兲 was operated at 62.5 MHz clock frequency. It digitizes with 14 bit resolution. The system clock was used as a beginning time for the time interval measurement. The same clock was then delayed by using a homemade circuit based on the Analog Devices AD9513 device. Of course, the delay should be very stable in order to allow measurements with picosecond resolution without introducing measurement degradation. In fact, with a previous version of the delay circuit, the results were much worse. For this reason, in some measurements we employed cables for generating the delay, in order to verify if the jitter of the delay circuit was not too high to correctly measure the instrument resolution. It was not possible, for obvious reasons, to perform the entire measurement set with delaying cables. The analog circuit generated an oscillating waveform having 25 MHz frequency. We obtained a Q factor of 30 which was considered sufficient. A number of samples were acquired for each event, and a set of 100 measurements was done for each delay, in order to assess the linearity 共i.e., the deviation of the average measurement from the theoretical value兲 and resolution 共i.e., the rms value of the measurement estimate with respect to the average兲. Such measurements

Estimation std [ps]

Preset Delay [ns]

Preset Delay [ns]

(c)

Estimation std [ps]

In our prototype, we limited the digital resources to a minimum. This meant to control the ADC, to acquire the relevant samples for each measurement, and to send the relevant data stream to a personal computer 共PC兲 for phase evaluation. It is not the purpose of this paper to discuss the best digital hardware to allow real time measurements at high rate, which is a nontrivial task. However, it is possible to foresee the most important issues. First, the necessity of a low noise reference curve calibrated for small delays, against which the phase should be measured. This means a relatively long file and therefore a somewhat long LMS procedure, despite the use of only a few samples for the measurement. Second, as already pointed out, the necessity of an iterative procedure. Third, and most important, the necessity to operate real time, which can be a problem for many experiments, where the rate can be as high as some millions events per second. The choice of operating with a digital signal processor 共DSP兲, while interesting as for flexibility, does not seem the best, except for ancillary tasks. On the contrary, using a FPGA approach seems to be more promising.8

Estimation std [ps]

IV. DIGITAL RESOURCES

Preset Delay [ns]

FIG. 5. Experimental results of the achievable rms resolution in function of the phase of the trigger event to the sampling comb and using the first 共a兲 15, 共b兲 two, and 共c兲 four samples. Note the different vertical scales.

were repeated for a significant number of delays to generate the curves shown in the following. A small FPGA device 共Xilinx Spartan 3兲 was used to put the data stream in local memory and successively to send the stream to the host PC. A first test was done by using 15 samples 关see Fig. 5共a兲兴. 100 measurements were done for each delay, and the resulting rms error, plotted in the figure, is shown to be always lower than 4 ps, independent of the delay or, better, of the phase between the sampling comb and the event. By using a reduced number of samples, 2 or 4, respectively, in the same experiment, one gets the results shown in Figs. 5共b兲 and 5共c兲, respectively. Using only the first two samples degrades the resolution especially when the delay to be measured is small; on the contrary using the four first samples in the time estimate does not degrade significantly the resolution, which worsens to 4.6 ps rms but reduces significantly both measurement time and mathematical burden. In a second measurement set, we deliberately changed the oscillation frequency of the analog circuit by changing the setup temperature. The oscillation frequency changes of 150 and 800 ppm were considered. Again 100 measurements

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(a) (a)

Deviation [ps]

Deviation [ps]

(b)(b)

Preset Delay [ns]

Preset Delay [ns] (c)

Deviation [ps]

Deviation [ps]

(d)

Preset Delay [ns]

Preset Delay [ns]

FIG. 6. Deviation of the time estimate due to a thermal drift of the oscillation frequency of 150 ppm, 共a兲 before and 共b兲 after frequency compensation and due to a thermal drift of the oscillation frequency of 800 ppm, 共c兲 before and 共d兲 after frequency compensation. The first eight samples were used. Note the significantly different vertical scales.

Estimation std [ps]

(a)

Preset Delay [ns]

delay. In Fig. 8, the histogram of the resulting delay estimates is shown. Apart for an 18 ps systematic error, the estimates are reasonably Gaussian and do not show evident misshapes, given the low statistics. Again, by employing the frequency correction procedure, the systematic error was reduced to a minimum 共see Fig. 9兲.

VI. CONCLUSIONS

We have shown that the method of measuring time intervals by sampling the dumped oscillations of an LC passive network and determining from that the phase between the oscillating shape and the sampling clock is capable of picosecond resolution. Using a passive discrete network allows us to quench rapidly the oscillation after a few periods: this feature could allow high measurement repetition rates. While in our experiments we used a simple circuit which makes use

(b)

Estimation std [ps]

were done for each delay and the average value of the difference between the measured and set delays was plotted. The measurements were then repeated by employing the frequency compensation procedure described before. The results are shown in Fig. 6 for 150 and 800 ppm frequency deviations. The first eight samples were employed. Without frequency compensation, the average deviations are on the order of 3.5 and 5.5 ps, respectively; after compensation the residual error is less than 0.5 ps and less than 1 ps in the two cases, therefore, lower than the rms resolution, which is shown in Fig. 7. Results worsen when using more than eight samples in this experiment since compensating the oscillation frequency becomes more difficult when a longer time span is considered. Notice also that in both cases, the rms resolution is better than that obtained in the first experiment with 15 samples. This suggests that the last samples of the measurement carry more errors than information anyway and they would be better disregarded in any case. Finally, we used a cable for generating a minimum jitter

Preset Delay [ns]

FIG. 7. Rms resolution of the measurements shown 共a兲 in Fig. 6共b兲 and 共b兲 in Fig. 6共d兲.

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Counts

054705-7

Estimated delay values [ns] FIG. 8. Results for a single measurement taken with a delay set by a coaxial cable. The frequency shift is 150 ppm. Notice the systematic error much higher than the measurement uncertainty.

of standard analog switches, a more refined circuit would eliminate or at least greatly reduce such drawbacks as frequency wandering or limited dynamic range of the oscillation compared to the ADC dynamics.

Two issues are still open and need to be solved in order to allow the use of this method as an alternative to more standard TDC or TAC setups: they are the need for a reference curve and the important amount of digital signal processing, which is necessary to derive the delay value from the raw ADC output data. We have proposed in this paper some suggestions to minimize this second problem but it has to be further investigated and better solutions should be devised. In order to minimize the 共analog兲 circuitry, many signals may be sampled by the same ADC with some price to pay in the analysis complication and in the achievable resolution: however, this possibility allows foreseeing multichannel instruments with reduced hardware need when ultrahigh time resolution is not required. ACKNOWLEDGMENTS

The authors wish to thank S. Caramanno and P. Torretta for discussions and assistance in the experiments. M. Bertolaccini and S. Cova, Nucl. Instrum. Methods 121, 547 共1974兲. D. Resnati, I. Rech, A. Gallivanoni, and M. Ghioni, Rev. Sci. Instrum. 80, 086102 共2009兲. 3 W. Becker, Advanced Time-Correlated Single Photon Counting Techniques 共Springer, Berlin, 2005兲. 4 D. M. Gersbach, Y. Maruyama, E. Labonne, J. Richardson, R. Walker, L. Grant, R. Henderson, F. Borghetti, D. Stoppa, and E. Charbon, IEEE European Solid-State Device Conference 共ESSCIRC兲, Athens, Greece, 196 共2009兲. 5 W. C. Niclass, C. Favi, T. Kluter, M. Gersbach, and E. Charbon, IEEE J. Solid-State Circuits 43, 2977 共2008兲. 6 P. Panek and I. Prochazka, Rev. Sci. Instrum. 78, 094701 共2007兲. 7 G. Ripamonti, M. Zambusi, R. Spigarolo, D. Santo, and C. Samori, IEEE Trans. Nucl. Sci. 42, 693 共1995兲. 8 A. Abba, A. Manenti, A. Suardi, and A. Geraci, Engineering of Reconfigurable Systems and Algorithms 共ERSA, Las Vegas, 2009兲. 1

Counts

2

Estimated delay values [ns] FIG. 9. Same as Fig. 8 but after frequency compensation. The systematic error is eliminated.

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