High Work-Function Metal Gate and High- Dielectrics for ... - IEEE Xplore

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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 12, DECEMBER 2005

High Work-Function Metal Gate and High- Dielectrics for Charge Trap Flash Memory Device Applications Sanghun Jeon, Jeong Hee Han, Member, IEEE, Jung Hoon Lee, Sangmoo Choi, Hyunsang Hwang, and Chungwoo Kim

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Abstract—We report the impact of high work-function metal gate and high- dielectrics on memory properties of NANDtype charge trap Flash (CTF) memory devices. In this paper, theoretical and experimental studies show that high gate and high permittivity (high- ) dielectrics play a key role in eliminating electron back tunneling though the blocking dielectric during the erase operation. Techniques to improve erase efficiency of CTF memory devices with a fixed metal gate by employing various chemicals and structures are introduced and those mechanisms are discussed. gate and high- maThough process optimization of high terials, enhanced CTF device characteristics such as high speed, large memory window, and good reliability characteristics of the CTF devices are obtained.

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Index Terms—Charge trap Flash (CTF) memory, electron back tunneling (ETB), erase, high- dielectric, metal gate, NAND, work function.

I. INTRODUCTION

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HARGE TRAP Flash (CTF) memory devices have received considerable attention due to the detrimental coupling effect among adjacent cells in sub-50-nm NAND type floating-gate Flash memory devices [1]. Nitride-based CTF memory devices have several advantages such as fast programming, low power operation, high density integration, good reliability characteristics, and high compatibility with conventional complementary MOS (CMOS) technology [2]–[4]. However, it is difficult to simultaneously satisfy the NAND specof 3 from 1 V at 18 V for ifications of low erase state V at 85 C 2 ms and good retention characteristics ( for ten years) because the current though the tunnel dielectric thickness critically affects both properties and the electron back tunneling (EBT) during erase operation limits the low [5], [6]. EBT is known to a serious concern for erase state meeting specification of NAND devices using Fowler–Nordheim (FN) program and erase schemes.

Manuscript received March 7, 2005; revised September 9, 2005. This work was supported by Tera Level Nano Devices though the Ministry of Science and Technology, Korea. The review of this paper was arranged by Editor R. Shivastava. S. Jeon, J. H. Han, J. H. Lee, and C. Kim are with the Devices Laboratory, Samsung Advanced Institute of Technology (SAIT), Kyungki-do 449-712, Korea (e-mail: [email protected]). S. Choi and H. Hwang are with the Department of Materials Science and Engineering, Gwangju Institute of Science and Technology, Gwanju 500-712, Korea. Digital Object Identifier 10.1109/TED.2005.859691

To reconcile this conflicting behavior, we have carried out a of metal systematic study on the impact of work-function gate and high permittivity (high- ) dielectric on the memory properties of nitride based CTF devices using both experimental and theoretical methods. In this paper, we first discuss the EBT-related technical barriers of conventional SONOS (poly Si–SiO –SiN–SiO –Si) gate and highdevices. Secondly, the benefits of highblocking dielectrics for CTF memory devices are discussed. of gate and erase Based on the dependence between the efficiency of CTF memory, various chemical and structural approaches of MANOS (metal–Al O –SiN–SiO –Si) are introduced for improving erase properties and those mechanisms are discussed. Finally, excellent memory properties including high speed, large memory window and good reliability of CTF memory devices are demonstrated. II. EXPERIMENTS AND SIMULATION A. Experiments After standard cleaning of a -type silicon wafer with a doping level of 5 10 cm , followed by a dilute 2% HF strip for 1 min, (MIS) capacitors with various stacks were fabricated using conventional Si processes. Tunnel SiO was grown by thermal oxidation in O at 850 C, and post annealed in N O at 850 C to improve reliability. For better program and erase speed, Si-rich SiN as a trapping layer was prepared by adjusting the ratio of dichlorosilane (DCS) to NH in a low-pressure chemical vapor deposition (LPCVD) system. For ONO devices, top SiO was deposited by LPCVD. For comparison, Al O dielectrics as a blocking dielectric were deposited by means of an atomic layer deposition (ALD) system. As a post metal annealing process, forming gas (97 N –3 H ) annealing was performed at 450 C for 30 min. To observe the on memory properties, various metal gates effect of gate of metal on ANO stacks were prepared. To determine the gates, dielectrics of various thickness were used and calculated versus 1 plots [7]. As a chemical approach to by improve erase properties of devices, a plasma process on the device in various ambient was performed. In addition, as a structural approach for the same purpose, the structure of the interfacial metal near the blocking dielectric was modified. The , which was extracted charged state was characterized by of the MIS capacitors. In our system, the calculated from

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JEON et al.: HIGH WORK-FUNCTION METAL GATE AND HIGH- DIELECTRICS

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Fig. 1. Erase characteristics of n poly Si/ONO structure. The thickness A, of tunnel SiO , trapping SiN, and blocking SiO was 26, 60, and 60 respectively. At higher erase bias, EBT) was observed due to low electron barrier height.

Fig. 2. Simulation results for program and erase characteristics of the ONO stack with respect to a metal gate work function (8 ). With increasing 8 , dramatic improvements in erase characteristics were achieved due to the increasing electron barrier height while program characteristics show negligible 8 dependence.

was normally 0.5 V. Since program and erase conditions of NAND Flash devices are 17 V for 20 s and 18 V for 2 ms, respectively, the programmed state and erased state were of 3 and 1 V, respectively. taken at 20 s and 2 ms from

top SiO and n poly Si gate. Due to “back tunneling,” the effectiveness of high erase voltage worsens and it may not be possible for the device to reach the specification. On the other hand, reducing the gate voltage decreases backtunneling, but will also undesirably increase the time needed for erase operation. To study the program and erase characteristics of ONO with but without any side effects such as boron penedifferent tration for p poly Si gate, and poor adhesion between the top gate, a simulation study was performed. SiO and the high As shown in Fig. 2, program and erase speed with respect to of a gate was plotted. The dependence of the gate the on program speed was negligible. However, the strong depenon erase characteristics was clearly found. dence of the gate For a gate with of 4.1 eV, poor erase characteristics were observed due to the low electron barrier height. However, with , dramatic improvements in erase characteristics increasing were monitored due to the increased electron barrier height. gate is crucial in attaining minimum erase state Thus, a highwhile not affecting program characteristics. However, even with the relatively thin tunnel SiO used in the simulation study of Fig. 2 and experimental results, attaining an erase state value of 3 V under given erase conditions is still difficult using an ONO stack. This motivated us to try high- dielectrics as a blocking oxide. Fig. 3 shows simulation data of erase characteristics for an . To make use ONO and ANO device with the same gate of the benefit of the highblocking dielectric, a 140- -thick Al O with an equivalent SiO oxide thickness (EOT) of 60 was compared to a 100- -thick blocking SiO with erase bias of 16 and 18 V. As expected, a device with Al O blocking dielectric shows better erase characteristics and less EBT phenomena than a device with SiO because the current density of Al O at high negative bias is lower than that of SiO (shown in inset). on program and To experimentally confirm the effect of erase characteristics of an ANO device, program and erase states of various metal gated ANO stacks were monitored. All devices

B. Theoretical Model For a theoretical investigation, Gritsenko’s simulator was utilized [8]. In our simulation study, a one-dimensional two-bands model of charge transport was used, which considers the Shockley–Read–Hall method for trap population, continuity, and Poisson equation. In addition, double carrier injection from both the substrate and the opposite gate electrode was taken into for electrons and holes account, and the number of traps was assumed to be same. For trap ionization probability (P), we employed multiphonon model, which has good agreement with experimental results of charge transport in MNOS [9]. In this model [10], we assume that the optical energy of trap , the energy of thermal ionization , and ionization the phonon energy for electron and hole traps are the same. This hypothesis was verified by experimental results [11]. For electron and hole injection, we used an FN tunneling scheme. For the simulation of SONOS device, we used the typical values of bandgap, and barrier height [8]. For SANOS device with top Al O dielectric, we used an electron barrier of 2.0 eV at the n poly Si/Al O interface and an Al O bandgap of 7 eV. No traps in the tunnel SiO , blocking Al O and blocking SiO were considered in this simulation work. III. RESULTS AND DISCUSSIONS Fig. 1 shows experimental data of erase characteristics for a n poly Si/ONO stack. By applying a higher erase voltage on the gate, electrons stored in the nitride layer can be displaced more quickly. However, at higher erase voltages, more electrons can tunnel from the gate into the nitride layer. This phenomenon is referred to as “electron backtunneling” [5], [6] and is caused by the low electron barrier height at the interface between the

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Fig. 3. Simulation results for erase characteristics of an ANO and ONO stack with erase bias of 16 and 18 V at a fixed gate 8 . For a blocking oxide, the A, respectively. ANO devices thickness of Al O and SiO were 140 and 100 show better erase characteristics due to relative thick physical thickness of Al O . Inset shows low current density of Al O with EOT of 88 A compared A. to SiO with EOT of 101

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were easily programmed to a of more than 1 V from 3 V with a program condition of less than 15 V/20 s (program of 1 V from 3 V for 17 V/20 s). The depenspecification: on program speed was negligible. However, the dence of on erase characteristics of ANO stack was found effect of to be very strong, as shown in Fig. 4. Al-gated 4.0 eV stack demonstrates program behavior regardless of erase bias never approaches 1 V. conditions. Once it is programmed, Negative erase bias conditions further program the devices by electron injection though the blocking dielectric from the gate. Further applying the erase bias for a few seconds erases the finally saturates to 0 V (data not device a bit more and shown). Thus, erasing for the given bias condition is not possible for Al gate on ANO device due to the low barrier height of metal to highdevices, even for 140- -thick Al O . Conbetween Al gate and n poly Si gate, sidering the similar conventional n poly Si gates should not be used for ANO stacked CTF memory devices. Erase properties of the TiAl gate 4.5 eV show more improvement than the Al gate but still exhibit poor erase properties. On the other hand, Pd gate than Al and TiAl clearly shows ( 4.9 eV) with a higher erase bias dependence and an improved erase state. It should be as slight as 0.3 to 0.5 eV causes a noticed that a change in dramatic change in erase efficiency, which can be explained by the following equation: 4

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Here, J is FN current density, q is the charge of single electron, h is Plank’s constant, is the energy barrier height, m is is the effective mass of an electhe mass of a free electron, tron, and is the electric field at the injecting interface. During erase operation, electrons from the gate can tunnel though the blocking oxide to the charge storage dielectric via FN tunneling and the FN tunneling current density is the strong

Fig. 4. Erase characteristics of various metal gates (Al, TiAl, and Pd) on ANO stack. For monitoring erase characteristics, the starting reference V for the program state was 1 V, and the erase pulse time was 2 ms. Dramatic change in erase properties with respect to 8 was observed. In particular, Al gated stack, even with erase bias condition, shows program states such as V of more than 1 V.

Fig. 5. Erase characteristics versus erase bias at 2 ms for metal gated ANO stacks with various process ambient. H plasma treated device shows degraded erase characteristics and highly reactive gas plasma treated devices show improved erase characteristics. Inset shows erase speed characteristics at erase bias of 18 V.

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function of barrier height. Thus, a slight change in and barrier height dramatically changes the current density though blocking oxide and erase property. Based on this result, we begate stack is needed for charge trap Flash lieve that a higher memory devices. A plasma process in various ambient was performed for Pd gated ANO devices to determine the effect of post-processes on erase efficiency. Fig. 5 shows bias dependence on the erase state for the aforementioned devices. Inset shows the erase speed with an erase bias of 18 V. Compared to the as-prepared sample, O and CF -plasma treated Pd gate/ANO device shows more improvement in erase characteristics while pure H -plasma treated Pd gate/ANO samples show the degradation of erase characteristics. Among various electrical results of plasma treated debevices, it was found that the flat band voltage shift fore and after the process is deeply related to erase efficiency.


Fig. 6. TEM analysis on 1500- A-thick TiN/ANO (a) and 1500-A TiN/6-nm-thick structural modified MN-M-MN/ANO stack (b). d denotes the structural modified region (15-nm ZrN/15-nm TiN/15-nm Ti/15-nm TiN) Compared to single gate stack, structural modified stack shows multilayer structure and dots at the interface.

Compared to the as-prepared device, the H -plasma treated dewhile O - and CF - plasma treated vice shows a negative . This indicates a change in , devices show a positive versus 1 plot for referwhich is also confirmed by the ence samples. The calculated metal work function of H -, O -, and CF - plasma treated Pd was found to be 4.6, 5.0, and 5.1 eV, respectively. As shown in (2), the is affected by both bulk property and surface property (2) where

depends on the bulk electron density. The term is due to the surface space-charge potential that must be overcome by the electrons in the solid in order to exit into the is Fermi energy [12]. Thus, is dependent vacuum and on surface states such as crystalline phase, ion size, roughness, and chemical absorption. The surface space charge or surface dipole causes an electric field that influences atoms or molecules that may absorb. Even inert gas atoms such as Ar and Xe respond to this field upon absorption. The charge distribution of these atoms will be slightly altered in a way that raises or lowers the of an absorbing metal. Generally, electron acceptor elements or nonmetal gas adsorbates such as O, Cl, F, and N raises the of metal, and electron donor elements or metal adsorbates such of metal. Thus, the work funcas Li, Na, and K lowers the tion is changed by chemisorption [12]. Consistent with earlier works in surface chemistry and science [12], electron acceptor of gas such as O and CF gas plasma process increases the gate and electron donor gas such as H plasma process decreases the of gate. Among electron acceptor gas atoms, halogen gas atom which has a high electronegativity is more reactive to get electron from the metal, which causes to increase electron binding energy in metal. That’s why F incorporated Pd shows the in our investigation. Since as prepared Pd on ANO highest devices shows significant suppression of EBT, the positive effect for O and CF plasma treated devices from the increase in was relatively less affected. However, the negative effect due to for H plasma treated device is strongly dethe decrease in scribed, in Fig. 5. Even though gas elements or processes used in this paper are not practical for real production of NAND SONOS type Flash memory devices, suitable gas annealing and doping

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Fig. 7. Erase speed characteristics of single TiN gate on ANO and structural modified interfacial MN on ANO stack. Compared to a single layer gate, structural modified gate stack shows improvement of erase characteristics.

techniques using surface science and chemistry may positively suggest a method of producing better memory properties of Flash memory devices. Another approach, structural modification of interfacial metal near the blocking dielectric, was also considered to increase . Elementary metals with high are normally noble the and thus have etching issues especially for nano-scaled devices. metal Recently, there were a few studies on various high composite nitrides (for example, TiAlN [13], WN [14], and so on) and fully silcide (FUSI) with doping technique [15], but process compatibility issues were not completely solved. Thus, of a well-understood the structural approach to increase gate electrode is quite practical to apply in a production line of by structural Flash memory devices. Possible changes in modification has been reported and applied to gate oxide applications [16]. As shown in Fig. 6, we prepared two different electrode schemes for ANO stack. One is a 1500- -thick single metal nitride (TiN) on ANO (A) and the other one is a structural modified stack of interfacial metal nitride between the 1500 -thick metal nitride (TiN) and blocking dielectric (B). For the structural modification of interfacial metal nitride near the blocking dielectric, 1.5-nm-thick ZrN/1.5-nm-thick TiN/1.5-nm-thick Ti/1.5-nm-thick TiN were deposited before the deposition of 1500 -TiN gate electrode. Compared to a single gate in Fig. 6(a), Fig. 6(b) shows the structurally modified region at the interface between TiN and Al O blocking dielectric. We also observed of small crystalline grains in the interfacial metal nitride region near the blocking dielectric of both stacks, the of by HR TEM. Monitoring structurally modified gate increases up to 0.4 eV. So far, the is not clear. However a mechanism of the increase in possible explanation can be given by the grain boundary effect [17]. The single dangling electron at each atomic site along the grain boundary is usually considered an acceptor, attracting an electron to lower its energy from higher energy states to lower energy states. Thus, small crystalline metal nitride region at the . Due to the increase in , interface cause the increase in interfacial metal nitride region inserted in the gate stack show the improvements in erasing speed at different erasing bias condition (Fig. 7) while maintaining other memory properties

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IV. CONCLUSION

Fig. 8. Program bias dependent program state of optimized ANO stack with . For monitoring program states, the starting reference V as an erase high state was 3 V, and program time was 20 s. Inset shows V distribution for achieving possible 2-bit operation.

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metal We report the impact of high work-function gate and high- dielectrics on memory properties of NAND type charge trap Flash (CTF) memory devices. By theoretical gate and and experimental studies, it was found that high high- dielectrics play a key role in eliminating EBT though the blocking dielectric during the erase operation. As techniques to improve the erase efficiency of CTF memory devices with a fixed metal gate, chemical and structural approaches of metal gate were introduced and those mechanisms were discussed. For improving erase efficiency, suitable gas plasma process and structural modification of the interfacial metal near the blocking dielectric are found to be effective ways. This can be explained by chemical absorption induced charge transfer and grain . Since the boundary effects leading to a change of gate of a given metal gate is tunable by these techniques, it may pave the way for a widening degree of freedom in choosing the appropriate metal gate material for charge trap Flash memory gate and highdevice applications. With the aid of high materials, high speed, large memory window, and good reliability characteristics of CTF devices were demonstrated. REFERENCES

Fig. 9. Retention characteristics of ANO stack at 250 C. Retention at 250 C for 2 h bake retention condition shows V of less than 0.3 V which is equivalent to 85 C/ten-year retention test in our paper. Inset shows excellent endurance characteristics of ANO stack.

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including programming speed, retention characteristics, and interfacial quality. with respect to bias. Program Fig. 8 shows the program state was taken from an erase state of 3 V by applying 13 to 17 V for 20 s. For achieving 2-bit operation in a NAND type cell, 3 program states of 0.6, 1.8 and 3.5 V are needed as shown in inset. Thus, well controlled and high program states up to 4 V in an allowed program condition shows possible multibit operation. Fig. 9 shows retention characteristics of ANO stack at a measurement temperature of 250 C. Based on the acceleration factor used in our retention study, a bake of 250 C for 2 h was found to be equivalent to 85 C for ten years for the same shift. Charge loss of 0.29 V among 30 devices after 250 C for 2 h was observed. The acceptably good retention characteristics were obtained by relatively thick tunnel SiO with the aid of optimized high gate and highblocking dielectrics. Inset shows good endurance characterisprogram and erase cycles. tics up to

[1] J.-D. Lee, S.-H. Hur, and J.-D. Choi, “Effects of floating-gate interference on NAND Flash memory cell operation,” IEEE Electron Device Lett., vol. 23, no. 5, pp. 264–266, May 2002. [2] M. H. White, D. A. Adams, and J. Bu, “On the go with SONOS,” IEEE Circuits Devices Mag, vol. 16, no. 4, pp. 22–31, Apr. 2000. [3] M. K. Cho and D. M. Kim, “High performance SONOS memory cells free of drain turn-on and over-erase: Compatibility issue with current Flash technology,” IEEE Electron Device Lett, vol. 21, no. 8, pp. 399–401, Aug. 2000. [4] C. W. Oh, S. D. Suk, Y. K. Lee, S. K. Sung, J.-D. Choe, S.-Y. Lee, D. U. Choi, K. H. Yeo, M. S. Kim, S.-M. Kim, M. Li, S. H. Kim, E.-J. Yoon, D.-W. Kim, D. Park, K. Kim, and B.-I. Ryu, “Damascene gate FinFET SONOS memory implemented on bulk silicon wafer,” in IEDM Tech. Dig., 2004, pp. 893–896. [5] C. H. Lee, K. I. Choi, M. K. Cho, Y. H. Song, K. C. Park, and K. Kim, “A novel SONOS structure of SiO =SiN=Al O with TaN metal gate for multigiga bit Flash memories,” in IEDM Tech. Dig., 2003, pp. 613–616. [6] H. Reisinger, M. Franosch, B. Hasle, and T. Bohm, “A novel SONOS structure for nonvolatile memories with improved data retention,” in VLSI Symp. Tech. Dig., 1997, p. 113. [7] S. M. Sze, Physics of Semiconductor Devices, 2nd ed. New York: Wiley, p. 395. [8] V. A. Gritsenko, K. A. Nasyrov, Y. N. Novikov, A. L. Aseev, S. Y. Yoon, J.-W. Lee, E.-H. Lee, and C. W. Kim, “A new low voltage fast SONOS memory with high- dielectric,” Solid State Electron., vol. 47, pp. 1651–1656, 2003. [9] K. A. Nasyrov, V. A. Gritsenko, M. K. Kim, H. S. Chae, S. D. Chae, and W. I. Ryu et al., “Charge transport mechanism in metal-nitride-oxide-silicon structures,” IEEE Electron Device Lett., vol. 23, no. 4, pp. 336–338, Apr., 2002. [10] S. Makram-Ebeid and M. Lannoo, “Quantum model for phononassisted tunnel ionization of deep levels in a semiconductors,” Phys Rev B, Condens. Matter, vol. 25, pp. 6406–6424, 1982. [11] V. A. Gritsenko, Silicon Nitride in Electronics. New York: Elsevier, 1988, pp. 138–237. [12] G. A. Somorjai, Introduction to Surface Chemistry and Catalysis. New York: Wiley, 1994, pp. 366–371. [13] D.-G. Park, T.-H. Cha, K.-Y. Lim, H.-J. Cho, T.-K. Kim, S.-A. Jang, Y.-S. Sug, V. Mirsa, I.-S. Yeo, J.-S. Roh, J. W. Park, and H.-K. Yoon, “Robust ternary metal gate electrodes for dual gate CMOS devices,” in IEDM Tech. Dig., 2001, pp. 671–674. [14] D.-G. Park, “Thermally robust dual-work function ALD-MN MOSFET’s using conventional CMOS process flow,” in VLSI Symp. Tech. Dig., 2004, pp. 186–187. [15] E. P. Gusev et al., “Advanced gate stacks with fully silicided (FUSI) gates and high- dielectrics: enhanced performance at reduced gate leakage,” in IEDM Tech. Dig, 2004, pp. 79–82.


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Sangmoo Choi received the B.S. degree in electrical, electronic, and computer engineering in 2000 from Sungkyunkwan University, Suwon, Korea and the M.S. degree in materials science and engineering in 2002 from Gwangju Institute of Science and Technology, Gwangju, Korea, where he is currently pursuing the Ph.D. degree in materials science and engineering. His current research interests are design, scaling, modeling, and reliability of SONOS-type nonvolatile memory devices.

Sanghun Jeon received the B.S. degree (with the highest GPA) in materials science and engineering from Chonbuk National University, Chonbuk, Korea in 1997, and the M.S. and Ph.D. degrees in electronic materials program from the Gwangju Institute of Science and Technology, Gwanju, Korea, in 1999 and 2003, respectively. In 2002, he visited Oak Ridge National Laboratory, TN, where he was working on the MBE growth of epitaxial SrTiO on silicon for gate dielectric application and its electrical characterization. In 2003, he joined Samsung Advanced Institute of Technology as a Senior Research Engineer where he worked on nano-memory research projects including CTF memory devices, ReRAM, and MBM devices. He is currently with the Advanced Technology Development Team of Samsung Electronics Company, Ltd., where he is responsible for 32-Gb NAND Flash memory devices as a Process Integration Engineer. His research interests include cell structure design, cell reliability, high- dielectric, metal gate, data retention, and endurance characteristics. He has published more than 28 international journal papers, 35 conference papers, and extended abstracts in the field of high- dielectric and metal gate for MOS and Flash memory devices applications. He also has 16 U.S. patents pending related to novel device and materials. Dr. Jeon is a member of the IEEE Electron Devices Society. He received the Presidential Award from Chonbuk National University, and the Best Paper Award with graduation honors from the Gwangju Institute of Science and Technology in 1996, and 2003, respectively. He also received Young Researcher Award at the International Conference on Solid State Devices and Materials (SSDM), in Nagoya, Japan, 2002.

Jeong Hee Han (M’00) received the B.S., M.S., and Ph.D. degrees in electrical and computer engineering from the University of Texas at Austin in 1997, 1999, and 2002, respectively. In 2003, he joined Samsung Advanced Institute of Technology, Kyungki-do, Korea, as a Senior Research Engineer where he researched high- materials and nitride-based structures for memory applications. In 2005, he moved to the Emerging Technologies Group of Samsung Electronics Company, Ltd. where he is currently investigating and developing nano-structures for use in next-generation nonvolatile memories.

Jung Hoon Lee received the B.S. degree in physics from Korea Advanced Institute of Science and Technology (KAIST), Daejon, Korea, in 1996 and the Ph.D. degree in condensed matter physics from the University of Texas at Austin in 2003, with research on the electron dynamics in few body systems. He joined Samsung Advanced Institute of Technology, Kyungki-do, Korea, in 2004, and has worked on transport in nanodevices.

Hyunsang Hwang received the B.S. degree in metallurgical engineering from Seoul National University, Seoul, Korea, in 1988, and the Ph.D. degree in materials science from the University of Texas at Austin in 1992. From 1992 to 1997, he was with the LG Semicon Corporation, Cheongju, Korea, as a Principal Researcher. In 1997, he joined the faculty at Gwangju Institute of Science and Technology, Gwangju, Korea, as a Professor in the Department of Materials Science and Engineering. In 2002, he was a Visiting Research Professor in Oak Ridge National Laboratory, Oak Ridge, TN, where he was working on MBE growth of epitaxial SrTiO on silicon for gate dielectric application and its electrical characterization. In recent years, he has engaged in research on process and device design of deep submicrometer MOSFET, MOSFET device reliability, epitaxial growth of high- gate dielectrics, characterization of ultrashallow junction, nano-electronic devices, and nonvolatile memory devices such as ReRAM and Flash memory devices.

Chungwoo Kim received the M.S. and Ph.D. degrees in materials science and engineering from The University of Utah, Provo. He is presently a Principal Engineer and Project Leader for nanoscale nonvolatile memory devices at the Process Development Team, Samsung Electronics Company, Ltd., Kyungki-do, Korea. He has also served as the Principal Investigator for the project of Terabit level Si based nonvolatile memories for teralevel nano devices though MOST since 2001. His research team includes six domestic universities in Korea and two foreign universities such as Cornell University in the U.S. and Institute of Semiconductor Physics in Russia. He holds over 36 U.S. patents (registered or filed) and has authored 68 journal papers and conference proceedings in semiconductor devices and process technologies. His current research interests include design, fabrication, and characterizations of nanoscale SONOS memory, charge transport mechanism and related measurements, and the study of single electron effects.