2009 2nd International Workshop on Electron Devices and Semiconductor Technology
Highly Robust Nanoscale Planar Double-Gate MOSFET Device and SRAM Cell Immune to Gate-Misalignment and Process Variations Angada B. Sachid*, Giri S. Kulkarni, Maryam S. Baghini, Dinesh K. Sharma, V. Ramgopal Rao Center for Excellence in Nanoelectronics, Department of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai, India, Telephone: +91-22-2576-7456, Fax: +91-22-2572-3707 E-mail: *
[email protected] Abstract – Gate misalignment and process variations are important challenges in sub-20 nm gate length planar double-gate (DG) MOSFET devices. For the first time, we demonstrate a misalignment- and process variations-aware device optimization strategy for a DG-MOSFET. Using underlaps and high-κ offset-spacers, we show that the robustness of the device to gate misalignment and process variations can be improved. A standard 6T-SRAM cell designed using the optimized devices shows better read and hold static noise margins, and lower variations in SNM and leakage power compared to a conventional DG-MOSFET. I. INTRODUCTION Scaling has been the chosen method to improve the performance of integrated electronic systems over several decades. The ubiquitous planar single-gate MOSFET suffers from degraded short-channel performance at extremely scaled technologies. Devices with two or more gates like planar double-gate, FinFET, tri-gate, MuGFET, Omega-gate etc were proposed as a method to achieve better short-channel performance at these technology nodes [1]. The planar double-gate devices suffer from the gate misalignment problem [2]. The problems with quasi-planar devices like FinFETs are multi-fold. Fin and gate pattering are the main manufacturing problems. Electrically, they have additional 3D capacitances when compared to an equivalent planar device [3]. When compared to planar devices, the quasi-planar devices are layout inefficient for minimum width devices [4]. From these advantages of DGMOSFETs, it is essential to re-evaluate the planar doublegate MOSFET and address the problems arising due to gate misalignment and process variations. For the first time, the effect of gate misalignment and process variations are considered together while optimizing a planar double-gate MOSFET. The paper is organized as follows – In section 2, the device structure and the simulation methodology followed in this work is explained. In section 3, we explain our gatemisalignment aware device optimization strategy. In section 4, we demonstrate the robustness of the optimized misalignment-tolerant device to process variations. In section 5, we design an SRAM cell and demonstrate its robustness to gate misalignment and process variations.
978-1-4244-3832-7/09/$25.00 ©2009 IEEE
II. SIMULATION SETUP The gate length (LG) of the devices is 18 nm. A high-κ gate dielectric (HfO2-based, κ = 20) with effective oxide thickness (EOT) of 0.9 nm and the supply voltage (VDD) of 1 V is used [5]. The offset spacer has κ = 7.5 and 20 for overlapped and underlapped devices respectively [6]. Underlap length (LUN) is varied from -2 nm to 12 nm and the silicon body thickness (TSI) is varied from 6 nm to 12 nm for device optimization. The channel is lightly doped with 1015 cm-3 [7]. The source/drain doping is 1020 cm-3 having a Gaussian source/drain doping profile with a slope of 1 nm/decade [7]. IOFF is fixed at 10-7 A/µm by tuning the gate work function for the nominal DG-MOSFET device. Nominal device is defined as the DG-MOSFET having the above mentioned device parameters and with no gate misalignment (∆ = 0). In this work, ∆ is varied from -12 nm to +12 nm (Fig. 1). Device and mixed-mode simulations are carried out using the Sentaurus TCAD suite [8]. Drift-diffusion transport model along with MLDA quantum correction models for electrons and holes are used. These models are calibrated with experimental data as shown by us in [7]. Contact resistance is modeled using a distributed resistance of 5 × 10-8 Ω-cm2 [7]. III. MISALIGNMENT-AWARE OPTIMIZATION To minimize the variations due to gate misalignment in planar DG-MOSFET, device optimization is carried out taking into account not only the performance of the nominal device but also devices with misalignment between the front and back gates. For the optimization, LUN, TFIN and gate work function are tuned. The optimization strategy used is as follows – (a) for a particular combination of device dimensions, the gate work function is adjusted to set IOFF = 10-7 A/µm for the nominal device, (b) ∆ is varied from -12 nm to +12 nm and its effect on the device characteristics like ION, IOFF, VT and SS is observed, and (c) the device that shows low variation in IOFF, VT, SS and ION over ∆ = ±12 nm, and at the same time shows a high value of ION at ∆ = 0 (nominal device) is considered to be the optimal device (Opt-DG). To optimize a device for SRAM applications, VT and IOFF should not be very sensitive to ∆. The stability and power consumption of an SRAM cell are very sensitive to variations in VT. Fig. 2 shows that the sensitivity of IEEE Catalog Number: CFP0926C ISBN: 978-1-4244-3832-7 Library of Congress: 2009900354
threshold voltage (VT), subthreshold swing (SS), draininduced barrier lowering (DIBL), ON-current (ION), OFFcurrent (IOFF) and ION/IOFF to ∆. The variation in near-VT and sub-VT parameters of the devices decreases with increase in LUN (Fig. 2(a)–2(d)). In the OFF-state, devices with underlaps have a larger effective channel length (LEFF) than the metallurgical gate length (LG). LEFF can be modeled as [9] – LEFF ≈ LG + 2 LUN in weak inversion and LEFF ≈ LG in strong inversion. The OFF-state LEFF increases with increase in LUN. Figs. 2(e)-(f) show – (a) ION and ION/IOFF are maximum at LUN = 4 nm and TSI = 9 nm, and (b) variation in ION with ∆ is comparable to the other devices under study. Hence, the above mentioned device (Opt-DG) is considered to be optimized for variations in ∆. IV. VARIABILITY Planar DG-MOSFET devices can have any ∆ when fabricated. Hence, it is important to study the variability performance of these devices over the complete range of expected ∆ (3σ(∆) = ±9nm [5]). The variability performance of a conventional overlapped DG-MOSFET (Ov-DG) and Opt-DG are compared. For this analysis, 3σ values of LG, EOT and TSI is ±2 nm, ±0.1 nm and ±1 nm respectively are chosen [7]. Fig. 3 shows the variability observed in IOFF, VT and ION of Ov-DG and Opt-DG for 3σ variations in LG, EOT and TSI. Variation in LG is the most important parameter resulting in variations in Ov-DG. Due to underlaps in Opt-DG, when compared to Ov-DG, variation in LG is reduced by ~50% due to its larger LEFF. Variation in TSI also causes appreciable variations in the device characteristics of both the devices, but it is not as dominant as variations in LG in Ov-DG. Using Opt-DG, the variations due to LG and TSI are reduced, which relaxes the requirements of LG and TSI controllability. Also, the contributions of variations in LG and TSI to the overall variations become almost equal [7]. Variation due EOT is negligible and hence not shown here. Opt-DG is more robust to process variations than Ov-DG. V. 6T-SRAM CELL SRAM is a large block occupying a large portion of chip area. Due to their low activity factor, the power consumption in a SRAM cell is dominated by the leakage power of the SRAM cell. Leakage power, read and hold static noise margin (SNM) are important parameters in SRAM design. A standard 6T-SRAM cell (Fig. 4) is used to study the effect of gate misalignment on SNM and power. SRAM cell using Ov-DG and Opt-DG devices is referred to as Ov-SRAM and Opt-SRAM respectively. Leakage current of the SRAM cell is mainly due to the source-drain leakage (ISD-LEAK) of the transistors if the gate leakage can be neglected. In this work, since devices with high-κ gate dielectric are considered, the gate leakage is neglected. ISD-LEAK decreases with increase in LEFF of the devices. SNM depends on the gain of the inverter stage
which depends on the output resistance (ROUT) of the devices making the inverter. As LEFF increases, so does ROUT. When compared to Ov-SRAM, Opt-SRAM shows (Fig. 5 – Fig. 9) – (a) higher read and hold SNM due to its higher output resistance even at low-VDD, (b) lower sensitivity in read and hold SNM to ∆ of the N- and P-type devices, and (c) lower sensitivity in cell leakage power to ∆ due to its longer LEFF in the OFF-condition (Fig. 7). The cell leakage power of Ov-SRAM and Opt-SRAM is same for ∆ = 0 as the devices have been tuned to have the same IOFF for ∆ = 0. V. CONCLUSIONS For the first time, the effect of gate-misalignment and process variations was considered while optimizing a planar DG-MOSFET. We show that with underlaps and high-κ offset spacers, DG-MOSFET (Opt-DG) devices and SRAM cells using such devices show lower sensitivity to gate-misalignment and process variations. Additionally, SRAM cells with Opt-DG show higher read- and holdSNM and lower variations in SNM and cell leakage power. Opt-DG is presented as a potential device to continue scaling. ACKNOWLEDGEMENT Synopsys Inc. is gratefully acknowledged for its generous TCAD support. Prof. A. Bharadwaj (IISc Bangalore) and the Technology-Aware Design group at IIT Bombay is thanked for stimulating discussions. R. Francis is thanked for his support with SRAM parameter extraction. REFERENCES [1] J.A. Huchby et al, “Extending the road beyond CMOS”, IEEE Circuits and Devices Magazine, Vol. 18, No. 2, pp. 2841, March 2002 [2] J. Widiez et al, “Experimental evaluation of gate architecture influence on DG SOI MOSFETs performance,” IEEE Transactions on Electron Devices, Vol. 52, No. 8, pp. 17721779, August 2005 [3] Manoj C.R. et al, “Impact of fringe capacitance on the performance of nanoscale FinFETs”, submitted to IEEE Electron Device Letters [4] A.B. Sachid et al, “A fresh look into the layout efficiency of FinFETs”, to be submitted to IEEE Transactions on Electron Devices [5] International Technology Roadmap of Semiconductors [Online http://public.itrs.net] [6] A. B. Sachid, C.R. Manoj, D.K Sharma, and V.R. Rao, “Gate fringe-induced barrier lowering in underlap FinFET structures and its optimization,” IEEE Electron Device Letters, Vol. 29, no. 1, 128-130, 2008 [7] A.B. Sachid et al, “Sub-20 nm gate length FinFET design: Can high-κ spacers make a difference”, IEDM Tech. Digest, pp. 697-700, 14-17 December 2008 [8] Sentaurus TCAD [Online http://synopsys.com] [9] J.G. Fossum et al, “Pragmatic design of nanoscale multi-gate CMOS”, IEDM Tech. Digest, pp 613-616, 13-15 Dec. 2004
(b)
(a)
(c)
TSI = 6 nm
Red : LUN = 4 nm
TSI = 9 nm
Blue : LUN = 9 nm
TSI = 12 nm
-10
-5
0
5
10
Gate Misalignment, ∆ ( nm ) 1.1 1.0 0.9
DIBL ( V / V )
0.8
15
TSI = 6 nm
Red : LUN = 4 nm Blue : LUN = 9 nm
TSI = 9 nm TSI = 12 nm
0.5 0.4 0.3 0.2 0.1 0
5
160 140 120 100 80 60 -15
10
0.6
-5
180
10
Gate Misalignment, ∆ ( nm )
15
10
10
-6
10
-7
10
-8
ION / IOFF ( X 1000 )
ON-Current, ION ( mA / µm )
Red : LUN = 4 nm Blue : LUN = 9 nm
TSI = 6 nm TSI = 9 nm TSI = 12 nm
-15
0
5
Gate Misalignment, ∆ ( nm )
Red : LUN = 4 nm Blue : LUN = 9 nm
12
10
(e)
15
-10
-5
0
5
10
TYP
100 50
MIN
0
Black: LUN = -2 nm
-50
Red : LUN = 4 nm
Black: LUN = -2 nm Red : LUN = 4 nm
Blue : LUN = 9 nm
Blue : LUN = 9 nm
-100 -12 -9 -6 -3 0
6 9 -12 12 -9 -6 -3 0 3 Gate Misalignment, ∆ ( nm )
15
10
-4
10
-5
10
-6
10
-7
10
-8
10
-9
3
Black: LUN = -2 nm
Red : LUN = 4 nm
Blue : LUN = 9 nm
Blue : LUN = 9 nm
MIN
3σ (TSI) = 1 nm
-12 -9 -6 -3 0 3
TSI = 9 nm
Red : LUN = 4 nm
TSI = 12 nm
Blue : LUN = 9 nm
8 6 4
-10
-5
0
5
Gate Misalignment, ∆ ( nm )
10
6
9 -12 12 -9 -6 -3 0 3
Gate Misalignment, ∆ ( nm ) 1.5
Black: LUN = -2 nm
15
(f)
Fig. 2: Misalignment-aware optimization of N-channel DG-MOSFET for LUN = -2, 4, 9 nm, and TSI = 6, 9, and 12 nm for gate misalignment (∆) between -12 nm to +12 nm. (a)(f) shows VT, SS, DIBL, IOFF, ION and ION/IOFF performance of these devices under gate misalignment. (VDD = 1 V. Constant current method is used for VT extraction)
6 9 12
(a)
Black: LUN = -2 nm
Red : LUN = 4 nm
(d)
TSI = 6 nm
3σ (TSI) = 1 nm
150
3σ (LG) = 2 nm
10
0 -15
MAX
200
(b)
2
0.4 -5
15
TSI = 12 nm
-5
(c)
Black: LUN = -2 nm
-10
10
Gate Misalignment, ∆ ( nm )
1.2
-15
5
TSI = 6 nm TSI = 9 nm
14
0.6
0
250
-4
16
0.8
-5
Black: LUN = -2 nm
1.4
1.0
-10
(a)
Black: LUN = -2 nm
-10
200
Gate Misalignment, ∆ ( nm )
0.7
0.0 -15
TSI = 12 nm
3σ (LG) = 2 nm
MAX
-0.1 -15
Black: LUN = -2 nm
Blue : LUN = 9 nm
300
OFF-Current, IOFF ( A / µm )
0.0
TSI = 6 nm TSI = 9 nm
TYP
0.1
220
350
Black: LUN = -2 nm Red : LUN = 4 nm
Threshold Voltage, VT ( mV )
0.2
240
ON-Current, ION ( mA / µm )
0.3
260
OFF-Current, IOFF ( A / µm )
Threshold Voltage, VT ( V )
0.4
Subthreshold Swing, SS ( mV / decade )
Fig. 1: Schematic of planar DG-MOSFET device showing perfect alignment and misalignment between the top and bottom gates (The device structure is adapted from SEM pictures published in [2]
3σ (LG) = 2 nm
6
9 12
(b)
3σ (TSI) = 1 nm
1.4 MAX
1.3 1.2 1.1 1.0
MIN
TYP
Black: LUN = -2 nm
Black: LUN = -2 nm
Red : LUN = 4 nm
Red : LUN = 4 nm Blue : LUN = 9 nm
Blue : LUN = 9 nm
0.9 -12 -9 -6 -3 0
3 6 9 -12 12 -9 -6 -3 0 3 6 9 12
Gate Misalignment, ∆ ( nm )
(c)
Fig. 3: Effect of process variations in LG (Left) and TSI (Right) at different gate misalignment (∆) for N-channel DGMOSFET devices with and without underlap.
50
0 -15
Fig. 4: Schematic of standard 6T-SRAM cell with DG-MOSFET devices
Hold SNM ( mV )
-10
-5
0
5
350
350
300
300
250 200 150 VDD = 1.0 V VDD = 0.8 V
10
0 -15
15
-10
-5
0
10
Gate Misalignment, ∆ ( nm )
Gate Misalignment, ∆ ( nm )
(c)
0 -15
Read SNM (mV)
110 100
0
-5
0
5
10
10
15
(a)
2
10
1
ent (
6
nm
9
)
-6
-3
0
-9
-15
-10
-5
0
5
Gate Misalignment, ∆ ( nm )
10
(b)
15
Fig. 7: Effect of gate misalignment on cell leakage power of Ov-SRAM and OptSRAM. ∆(N- DG-MOSFET) = ∆(P- DGMOSFET)
90 80 -9
-6
N- M is
-6
10
-7
-3
0
3
align 6 men t ( nm )
-9
9
-6
-3
0
3
9
6
(b)
-6
-7
10
-8
- Mis
align m
0
3
ent (
6
nm )
9
0 -3 -6
3
6
9
-9 12 -12
12
nm
-9
10 -12 -9 -6 -3 N
)
10
en t(
-1
10
15
(d)
100
(a)
PM i sa lig nm
0
10
110
70
10
10
5
Fig. 8: Read SNM and Hold SNM of the Ov-SRAM and Opt-SRAM with cell ratio, β = 1. Opt-SRAM shows higher read and hold SNM values and better stability to ∆. Here, ∆(N- DG-MOSFET) and ∆(P- DG-MOSFET) are different. 10
Ov-SRAM Opt-SRAM
3
9
nm en t
-3
isali gnm
6
M sa lig
-6
-9
-10
0
120
P-
-9
3
)
90
70
Gate Misalignment, ∆ ( nm )
Change in SRAM Leakage Power
120
N- M
-15
-5
Gate Misalignment, ∆ ( nm )
(n m
V) Read SNM (m
-8
-10
130
80
10
VDD = 0.6 V VDD = 0.4 V
Opt-SRAM
140
) kage Power ( W SRAM Cell Lea
SRAM Cell Leakage Power ( W )
10
VDD = 1.0 V VDD = 0.8 V
100
130
-6
10
10
150
15
140
-7
15
(b)
Fig. 5: Read SNM and Hold SNM of the Ov-SRAM and Opt-SRAM with cell ratio, β = 1. Opt-SRAM shows higher read and hold SNM values and better stability to ∆. It is assumed that ∆(N- DG-MOSFET) = ∆(P- DG-MOSFET).
Fig. 6: Change in read SNM of Ov-SRAM and Opt-SRAM around ∆=0. Opt-SRAM is highly robust to gate misalignment.
Ov-SRAM Opt-SRAM
10
200
50
5
5
250
VDD = 0.6 V VDD = 0.4 V
Ov-SRAM
0
nm )
-15
400
50
-5
Gate Misalignment, ∆ ( nm )
400
100
-10
(a)
10
-8
-9
10 -12 -9 -6 -3 n -Mis
alig
0
nme nt
3 (nm )
6
9
12
-9 -12
0 -3 -6
3
6
9
12
)
Black: Ov-SRAM Red : Opt-SRAM
-80
(a)
(n m
-60
0 -15
15
lig nm en t(
VDD = 0.4 V
10
VDD = 0.6 V VDD = 0.4 V
en t
VDD = 0.6 V
5
25
isa
VDD = 0.8 V
0
VDD = 1.0 V VDD = 0.8 V
gn m
VDD = 1.0 V
-5
50
PM
∆ Read SNM ( % )
-20
-10
Gate Misalignment, ∆ ( nm )
0
-40
75
25
BL
BLB
75
isa li
NR
100
M
NL
100
125
P-
NAR
NAL
Read SNM ( mV )
50 fF
125
Opt-SRAM
150
VDD = 0.6 V VDD = 0.4 V
ge Power ( W ) SRAM Cell Leaka
50 fF
175
VDD = 1.0 V VDD = 0.8 V
Ov-SRAM
150
PR Read SNM ( mV )
PL
175
WL
Hold SNM ( mV )
VDD
WL
(b)
Fig. 9: SRAM cell leakage power of the Ov-SRAM and Opt-SRAM with cell ratio, β = 1. Opt-SRAM and Ov-SRAM show similar power for ∆=0 as IOFF of the DGMOSFETs are equal. Opt-SRAM shows better stability to ∆.
