Hybrid silicon evanescent devices - CiteSeerX

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1Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA 93106, USA. 2Intel Corporation, 2200 Mission College Blvd, ...
Hybrid silicon evanescent devices Si photonics as an integration platform has recently been a focus of optoelectronics research because of the promise of low-cost manufacturing based on the ubiquitous electronics fabrication infrastructure. The key challenge for Si photonic systems is the realization of compact, electrically driven optical gain elements. We review our recent developments in hybrid Si evanescent devices. We have demonstrated electrically pumped lasers, amplifiers, and photodetectors that can provide a low-cost, scalable solution for hybrid integration on a Si platform by using a novel hybrid waveguide architecture, consisting of III-V quantum wells bonded to Si waveguides. Alexander W. Fang1*, Hyundai Park1, Ying-hao Kuo1, Richard Jones2, Oded Cohen3, Di Liang1, Omri Raday3, Matthew N. Sysak1, Mario J. Paniccia2, and John E. Bowers1 1Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA 93106, USA 2Intel Corporation, 2200 Mission College Blvd, SC12-326, Santa Clara, CA 95054, USA 3Intel Corporation, S.B.I. Park Har Hotzvim, Jerusalem, 91031, Israel *E-mail: [email protected]

The indirect bandgap of Si has been a key hurdle in the

We are developing wafer-scale approaches that could result in the

achievement of optical gain elements. Raman lasers and

simultaneous fabrication of thousands of lasers on a single Si wafer.

amplifiers1-3 have been demonstrated, and optical gain in

Recently, we demonstrated an electrically driven laser5 and amplifier6

nanopatterned Si4 has also been observed, but an electrically

based on a hybrid waveguide structure that uses III-V quantum wells

pumped all-Si gain element has yet to be realized. An alternative

bonded to Si waveguides to achieve optical gain. In addition, under

to creating an electrically pumped all-Si gain mechanism is to take

reverse bias operation, the same structure acts as a photodetector7.

prefabricated lasers and couple them to Si waveguides. However,

The lateral homogeneous nature of the III-V quantum layer structure

because of the tight alignment tolerances of the optical modes

allows the optical mode to be defined by the Si waveguide, leading to

and the need to align each laser individually, this method has a

an alignment-free bonding process. Moreover, the mode lies primarily

limited scalability and it is difficult to envision die attaching more

in the Si region, leading to low coupling losses from the active hybrid

than a few lasers to each chip without prohibitive costs.

waveguide to passive Si waveguide regions. This architecture allows for

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MT1007_p28_35.indd 28

JULY-AUGUST 2007 | VOLUME 10 | NUMBER 7-8

ISSN:1369 7021 © Elsevier Ltd 2007

06/06/2007 15:05:01

Hybrid silicon evanescent devices

REVIEW

of the wafer could be designed to have wide waveguide widths to increase the saturation power of the amplifier.

Plasma-assisted low-temperature wafer bonding A key step in the fabrication of this device platform is the bonding of the InP-based epitaxial layer structure to Si. Wafer bonding follows the Fig. 1 Cross section of the hybrid Si evanescent device. (Reprinted with permission from8. © 2007 Optical Society of America.)

Si waveguide processing on an SOI substrate and the growth of the

thousands of lasers, amplifiers, and photodetectors to be fabricated in a

rigorous surface cleaning that involves a solvent clean and a rinse with

single bonding step.

Tergitol, a mild detergent. The surface is inspected for particles under

III-V epitaxial layer structure on an InP substrate. The wafers undergo a

a Nomarski microscope at 20x magnification and the cleaning process

Device structure and optical mode characteristics

is repeated until no particles are present. After cleaning, the surface

The cross section of the hybrid Si evanescent waveguide device is

respectively. After oxide removal, the samples are inspected, cleaned

shown in Fig. 1. It consists of a III-V multiple quantum well epitaxial

if necessary, and then undergo an ozone cleaning treatment. Next the

oxides of the Si and InP are removed with buffered HF and NH4OH,

layer structure bonded to a Si-on-insulator (SOI) rib waveguide. The

surfaces are treated with an O2 plasma. The samples are then dipped

device fabrication process can be divided into three major parts. First,

in deionized (DI) water, dried with N2, and the top surfaces are placed

the Si waveguides and any other desired Si devices are fabricated in

in physical contact. At this point, a weak spontaneous bonding occurs.

a complementary metal-oxide-semiconductor (CMOS) fabrication

To strengthen the bond, the wafers are held together under vacuum

facility. Next, the III-V epitaxial layer structure is transferred to the Si

at a pressure of 2 MPa and a temperature of 300°C for 12 hours. After

waveguides through an O2 plasma-assisted, low-temperature bonding

bonding, the InP substrate is removed in a HCl solution.

process. Finally, post-processing of the III-V layers is done after bonding to control the flow of current through the structure to ensure efficient

Because of the thermal expansion coefficient mismatch of Si and InP (αSi = 2.6 x 10-6 K-1, αInP = 4.8 x 10-6 K-1), a low-temperature,

optical gain to the waveguide mode. The details of the transferred

O2 plasma-assisted bonding (