Hybrid Soft/Hard Decision Multilevel Coded Modulation for Beyond 100Gbps Optical Transmission (1)
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Fan Yu , Deyuan Chang , Nebojsa Stojanovic , Changsong Xie , Mo Li , Lili Jin , (1) (1) (1) Zhiyu Xiao , Xiaozhong shi , Liangchuan Li (1)
Huawei Technologies Co., Ltd., Network Research Department, Shenzhen, 518129, China
[email protected] Huawei Technologies Duesseldorf GmbH, European Research Center, Riesstrasse 25, D-80992 Munich, Germany
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Abstract We propose a hybrid soft/hard decision multilevel coded modulation scheme (HMLC) which improves the performance-complexity ratio compared with conventional single LDPC scheme. An iterative multi-stage decoding algorithm between LDPC and BCH codes is presented. Introduction Driven by explosive growth of internet services, transmission rate in a signle wavelength channel has raised from 10G/40Gbps to 100Gbps, and is still developing rapidly towards 400Gbps or even 1Tbps. To inrease spectral efficiency in optical systems, higher order modulation formats, such 1 as 16QAM (Quadrature Amplitude Modulation) , 2 3 32QAM , and 64QAM , are intensively investigated. In today’s commercial optical systems normally utilizing on-off-keying, opticalduobinary or quadrature-phase-shift-keying modulation formats, coding and modulation are performed separately. With the transmission rate moving up beyond 100Gbps, researchers begin to focus on coded modulation which integrates channel coding and modulation to make transmission systems more efficient. Currently, there are three very hot reaserach topics related to coded modulation in optical 4-5 systems: a) trellis-coded modulation , b) bit interleaved coded modulation (BICM) with shaped constellation, such as iterative polar modulation (IPM), non-uniform QAM (NU-QAM), 6-9 and 4-dimensional coded modulation , and c) multilevel coding (MLC) scheme with lowdensity parity-check (LDPC) as component 10 codes . Although all these techniques can improve coding gain, decoding complexity prohibits their implementation in the near-future. For example, in case of LDPC-based MLC with limited coding overhead (7%~30%) in highspeed optical systems, the LDPC code at high Transmitter LDPC encoder
L1
BCH encoder
b1b4 Interleaver b2b5
L2
HMLC scheme The block diagram of the proposed HMLC scheme with 64QAM mapping is shown in Fig. 1. At the transmitter side, similar to the 12 previously reported MLC scheme , the source bits are partitioned into three levels, and each level is encoded with different code rates for unequal protection. In our HMLC scheme, Level 0 (L0) is encoded by a LDPC encoder (soft decoding), Level 1 (L1) is encoded by a Biosafety Clearing-House (BCH) encoder (hard decoding), and Level 2 (L2) is left uncoded. An interleaver is introduced in L1 to mitigate the effect of error propagation, while it is not required for L0 due to the built-in interleaving property of LDPC. Then, the coded and
Receiver
b0b3
64 QAM mapping
Bit partition
L0
level suffers from even more serious complexity issues due to both further reduced overhead and higher throughput. Although MLC using 11 hard-decision component codes can dramatically reduce the implementation complexity, the corresponding reduced coding gain makes it as less competitive solution. In order to increase coding gain at relatively low implementation complexity, we propose a hybrid soft/hard decision multilevel coding (HMLC) scheme which employs soft-decision lower level component code and hard-decision higher level component code. HMLC with 16, 32 and 64QAM are investigated and performance analysis demonstrates the performancecomplexity ratio improvement of 0.15~0.4dB at a -6 BER of 10 for almost no extra complexity.
channel
L0 Demapper
LDPC Decoder
L1 Demapper
Deinterleaver
L2 Demapper
L0
BCH Decoder
L1 Interleaver
L2
Fig. 1: Block diagram of HMLC scheme -7
-5
111 110
-3
-1 0 1
101 100
3
011 010
5
7
001 000
I b2b1b0
Fig. 2a: 64QAM single dimension mapping
-3
-1
11
10
0
1
3
I
00
01
b 1 b0
Fig. 2b: 16QAM single dimension mapping
uncoded bits are combined for mapping to QAM 12 symbols by Ungerboeck's mapping . For 64QAM, the constellation can be designed as symmetry constellation and thus the twodimensional constellation is decomposed into a one-dimensional, as shown in Fig. 2a. Bits of L0, L1, and L2 are mapped into b0b3, b1b4 and b2b5, respectively. At the receiver side, a hybrid soft/hard decision iterative multi-stage decoding (MSD) algorithm is particularly designed for decoding the proposed HMLC to enable higher coding gain. In the beginning, the L0 demapper has no information from other two levels. It only uses the pure received signal to generate log– likelihood ratios (LLRs) of L0 bits. After L0 bits decoding by the soft-decision LDPC decoder, the soft information of L0 bits is provided to the L1 and L2 demappers as a priori information to support the decoding of L1 and L2 bits (LLR calculation). In the next step, hard-decisions from L1 demapper are de-interleaved and decoded by a BCH decoder module. Decoded bits of L1 are interleaved and transferred to the next L2 level demapper. After the decoded bits of L2 are available from L2 demapper, the first decoding step for all levels is finished. At this time, the information from all levels is available, and the decoder starts from L0 level again. Now, each demapper utilizes both the channel symbol signals and the decoded bits of other two levels from the previous iteration to do demapping. The decoding performance can be significantly improved only in several iterations. The most important in the decoding process is the demapping algorithm which combines both soft and hard information. In our analysis and simulations, we assume an additive white Gaussian noise (AWGN) channel. By definition, k the LLR of a bit bi of a received symbol R is given by: LLR(bik ) log[ p(bik 0 / R k ) / p(bik 1 / R k )] , where
p(bik
X / Rk ) / X
0,1
represents
the
conditional probability density function of the k received symbol R .
¦ ^p(b 1
LLR(b kj ) / j
1, 4
log
i 0 1
k j
¦ ^p(b
k j
In the L0 demapper, the hard information of L1 and L2 are fed back as a priori information. So, LLRs of b0b3 can be calculated by p(b kj 0 / R k , b1 , b2 , b4 , b5 ) , ˄1˅ LLR(b k ) / log j
j 0, 3
p(b kj
1 / R k , b1 , b2 , b4 , b5 )
In the L1 demapper, calculation expression of LLRs of b1b4 is given in (2) while the soft information of L0 and hard information of L2 are used as a priori information. LLRs of b2b5 can be calculated in the same way. Without loss of generality, we just take 64QAM constellation demapping as an example to describe our proposed scheme. However the M method can be extended to arbitrary 2 -QAM modulation demapping. The 16QAM onedimensional constellation mapping is shown in Fig. 2b. In case M is an odd number, the constellation mapping is different but also can be designed based on Ungerboeck set partitioning strategy. A 32QAM constellation map design is shown in Fig. 3, which is called double-square constellation. The minimum intrasubset Euclidean distance is equal for subset b0 and b1 which are partitioned as the lowest level L0, and subset b2 is partitioned as L1. b4b3b2b1b0 Q 01110 01101 00110 00101 01111 01100 01001
00111
00100
01010
00001 00010
01000 01011
00000
11110
11101
11111 11001
10110 10101
11100
11010
00011
10111
I
10100
10001 10010
11000 11011
10000
10011
Fig. 3: Mapping of 32QAM double-square constellation
Result and Discussion We simulated the performance of our proposed scheme with 16, 32 and 64QAM, and compared results with corresponding single LDPC 13-14 schemes reported previously . Component codes employed for each modulation format are
0 / R k , b2 , b5 , bi
0) u exp( LLR(bik )) p(b kj
0 / R k , b2 , b5 , bi
1)`
1 / R k , b2 , b5 , bi
0) u exp( LLR(bik )) p(b kj
1 / R k , b2 , b5 , bi
1)`
˄2˅
i 0
Tab. 1: Component codes employed in HMLC schemes (B-INLV: block interleaver; C-INLV: convolutional interleaver)
scheme 64QAM 64QAM-C 16QAM 16QAM-C 32QAM
L0 LDPC-BC(18360,4,8) LDPC-CC(18360,4,8) LDPC-BC(18360,4,12) LDPC-CC(18360,4,12) LDPC-BC(18360,4,10)
L1 BCH(4590,4343), 100*18360 B-INLV BCH(4590,4421), 400*4590 C-INLV BCH(4590,4460), 100*18360 B-INLV BCH(4590,4486), 400*4590 C-INLV BCH(4590,4382), 100*18360 B-INLV
L2 uncoded uncoded no no uncoded
overhead 22.60% 21.80% 22% 21.6% 20.35%
listed in Tab.1. The overall overhead is designed to be close to 20%. The numerical results are shown in Fig. 4. In decoding of the 64QAM HMLC scheme, we used 30 iterations of sumproduct algorithm for LDPC decoder and 3 out iterations between levels (denoted by 3*30iter), while in decoding of the single LDPC-BC scheme we also used 30 iterations to fairly compare both schemes. Further increasing the number of iterations did not bring significant gain. From the performance point of view, it can be seen that the 64QAM HMLC scheme outperforms the single LDPC-BC one by about -6 0.35dB in SNR at BER of 10 , and this gain further increases at lower BERs due to the excellent waterfall performance of the proposed 14 decoder. When LDPC-CC(18360,4,8) is employed as the component code, denoted as 64QAM-C scheme in Tab.1, the performance is further improved by 0.1dB, which is still better than single LDPC-CC scheme. From the implementation complexity point of view, because only one third of bits are processed by LDPC-CC in the HMLC scheme and the complexity of BCH decoder is much lower than that of LDPC-CC, it can be roughly estimated that HMLC with 3*10iter has similar complexity as LDPC-CC with 10 iterations, but brings an -6 additional gain of 0.15dB at BER of 10 . Also, HMLC with 3*10iter shows the same performance as LDPC-CC with 30 iterations, that is achieved by about 1/3 of LDPC-CC complexity. Because 4-bit symbols of 16QAM are partitioned into 2 levels, LDPC-CC(18360,4,12) is employed to fit 20% overhead in the 16QAM HMLC scheme. Although the HMLC scheme shows no significant improvement comparing to the single LDPC-CC after 30 iterations, when iteration number is reduced to 6, which is a feasible number of iterations in practical systems, the HMLC after 2*6iter provides 0.2dB more coding gain than single LDPC-CC after 6 10
10
10
-2
A novel HMLC scheme for beyond 100Gbps optical transmission systems was proposed. By employing SD FEC for low level component codes and HD FEC for higher level component codes, the HMLC scheme provides a coding -6 gain improvement of 0.15~0.4dB at BER of 10 with different constellation mapping at almost no extra complexity. The improved performancecomplexity ratio makes it a promising FEC solution for high-speed optical systems with higher order modulation formats. Particularly, when the system migrates from QPSK to 16QAM, the proposed HMLC scheme can double the throughput and provide more than 0.2dB coding gain at no extra complexity. References [1] H. Takahashi et al., ECOC’08, PDP Th.3.E.4. [2] X. Zhou et al.,OFC’11,PDPB3 (2011). [3] A. H. Gnack, et al., OFC’11, PDPB2 (2011). [4] T. Sakamoto et al., ECOC’09, paper P.3.17. [5] Xiang Liu et al., OFC’10, OMR3 (2010). [6] Ivan B. Djordjevic et al., OFC’10, OMK2. [7] Xiang Liu, et al., OFC’12, PDP5B.3 (2012). [8] J. Zhang et al., OFC’12, OW1H.2 (2012). [9] J. Renaudier et al., OFC’13, OTu3B.1 (2013). [10] Ivan B. Djordjevic et al., J. of Lightwave Technol. 24, 420, (2006). [11] Ramtin Farhoudi et al., OFC’13, OM3C.6. [12] Udo Wachsmann et al., information theory, Vol. 45, NO. 5, 1361-1391(1999). [13] D. Chang, et al., OFC’11, OtuN2 (2011). [14] D. Chang, et al., OFC’12, OW1H.4 (2012). 10
32QAM
0
LDPC-BC,30iter HMLC(LDPC-BC),3*30iter
BER
LDPC-BC,30iter HMLC(LDPC-BC),2*30iter LDPC-CC,30iter HMLC(LDPC-CC),2*30 -2 10 LDPC-CC,6iter HMLC(LDPC-CC),2*6iter
-4
10
-4
10
0.35dB 10
Conclusions
16QAM
0
LDPC-BC,30iter HMLC(LDPC-BC),3*30iter LDPC-CC,30iter HMLC(LDPC-CC),3*30iter -2 LDPC-CC,10iter 10 HMLC(LDPC-CC),3*10iter
BER
10
64QAM
0
iterations with the comparable implementation complexity. For 32QAM with odd number of bits per symbol, the performance curves shown in Fig. 4 indicate that the proposed HMLC scheme based on LDPC-BC component codes provides 0.4dB -6 coding gain improvement at BER of 10 . The additional improvement compared to the 64QAM (or 16QAM) case comes from the specially designed double-square constellation mapping.
0.4dB
0.3dB -6
-6
16.8
17
17.2
-4
10 17.4 11.3
11.4
11.5
11.6 11.7 SNR(dB)
11.8
10
-6
14.2
14.4
14.6
14.8
Fig. 4: performance curves for HMLC and single LDPC schemes with 64QAM, 16QAM and 32QAM
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