IBM Presentations: Blue Pearl Basic template

IBM Research

A Low Power 10 Gb/s Serial Link Transmitter in 90-nm CMOS Alexander Rylyakov and Sergey Rylov IBM T.J. Watson Research Center, Yorktown Heights, NY, USA

CSIC Symposium

November 2, 2005

IBM Research

Transmitter Top-Level Block Diagram 4 x 2.5 Gb/s Input Buffers

2 x 5 Gb/s 4:2 MUX

5GHz CLOCK

4 x 10 Gb/s

4-tap FFE

10 Gb/s

DAC/Driver

DAC settings

Key transmitter goals • Demonstrate half-rate architecture at 10 Gb/s with reduced power dissipation •

Demonstrate modified DAC design with improved bias current mirroring, reduced leakage sensitivity and improved voltage reference switch

•

Explore key performance metrics (power, output voltage swing, jitter, duty cycle distortion) at different temperatures and supply voltage conditions

¾ Tx is a wirebond breakout testsite of the SerDes for chip-to-chip communications: “A 10Gb/s 5-tap DFE / 4-Tap FFE Transceiver in 90nm CMOS Technology” M. Meghelli et al., accepted for ISSCC 2006 2

CSIC Symposium | November 2, 2005

IBM Research

Equalization in time domain the signal, after passing through the channel, will spread over adjacent sampling points, resulting in inter-symbol interference (ISI). Feed-Forward Equalizer (FFE) attempts to correct for that by reshaping the signals before sending them into the channel. 1st

main tap

postcursor

n-1

n

channel

n+1 time

FFE

frequency FFE + channel

ISI in frequency domain this means attenuating low-frequency components of the signal and amplifying high-frequency components The resulting transfer function is more broadband with less ISI 3


IBM Research

Equalization (1-tap example)

yn = xn - α* xn-1

1-tap FFE:

if xn = xn-1 then yn = (1 - α) * xn if xn ≠ xn-1 then yn = (1 + α) * xn FFE de-emphasizes low-frequency components (1, 1 or -1,-1) and pre-emphasizes high-frequency components (1,-1 or -1, 1) FFE

1

1

4

1

-1

-1

channel

1


1

1

-1

-1

1

1

1

-1

-1

IBM Research

4:2 MUX

VDDA

4-tap FFE

chip edge

Transmitter Chip Block Diagram AVTT

DAC/Drivers

CLOCK 2

channel

19

2

IDAC SEL0

DIV 2

XOR0 tap 0 1:4

CLOCK 4 DATA 0 DATA 2 DATA 1 DATA 3

SEL1

1:4

XOR1

MUX0

5

tap 1

6

MUX1 SEL2

6

XOR2

1:4 SEL3

tap 2

5

XOR3

tap 3

1:4

Three circuit design styles with different power and clock domains: • analog (AVTT, no clock) • high-speed digital (VDDA, CLOCK2 and 4) • standard CMOS (VDDD, low-speed clock) 5


4 sign bits serial interface

8 power down

19 tap weights

VDDD

IBM Research

CML Sub-blocks Design Highlights 4:2 MUX

5 GHz

CLOCK 2

DIV 2

VDDA

4-tap FFE

2 x 5 Gb/s

CLOCK 4 DATA 0 DATA 2 DATA 1 DATA 3

SEL0

XOR0

10 Gb/s (precursor)

SEL1

XOR1

10 Gb/s (main tap)

SEL2

XOR2

10 Gb/s (1st postcursor)

SEL3

XOR3

MUX0

MUX1

4 x 2.5 Gb/s 10 Gb/s (2nd postcursor)

Aggressively scaled for low-power CML ( current-mode-logic) blocks (buffers, latches, selectors). The 2.5 Gb/s latches have 150 µA tail currents (4 kΩ resistor loads) and the 5.0 Gb/s latches have 300 µA tail currents (2 kΩ resistor loads). The timing condition between the 5 GHz CLOCK2 and the 5 Gb/s data at the input of the FFE has to be satisfied across process, voltage and temperature variations. 6


IBM Research

DAC/Drivers

• The output driver IDAC features novel current mirrors (with opamp-like structures) and dummy loads in the lower 4 bits, to match the leakage in the voltage reference nodes and improve linearity.

chip edge

IDAC and Output Drivers Design Highlights AVTT

channel

19

2

IDAC

tap 0 1:4

• Output stages (drivers, predrivers and pre-predrivers) carefully designed for timing with matching loads and symmetric layout.

1:4 5

• High-current carrying nodes are compliant with electro-migration rules, all chip I/O is ESD protected.

tap 1

6

• Can drive both AC- and DC-coupled (50 Ω to AVTT) channels. AC-coupling is more challenging because DC and AC signals are loaded differently and that reduces maximum voltage swing, distorts the signal.

6 1:4

tap 2

5 tap 3

1:4 8 power down serial interface 7


19 tap weights

VDDD

IBM Research

Transmitter Core Layout The wirebond padcage of the chip (1.7mm x 1.7mm) is not shown.

10 Gb/s

Transmitter Core Dimensions: 700um x 550 um (the C4 version built of the same blocks is smaller) CML CORE : 120um x 140um

ESD

Drivers IDAC

IDAC

140 µm

CML Core

2.5 Gb/s

SI

2.5 GHz

Clock Receiver

ESD 120 µm

8

2.5 Gb/s


5 GHz

IBM Research

Test Setup

one of the differential 10 Gb/s output signals is directly observed on the oscilloscope, while another is applied to BERT to continuously verify error-free operation.

testing is done on-wafer with high-speed picoprobes and high-bandwidth cables, the output is AC-coupled to the oscilloscope and BERT on-chip divider performance is monitored on the spectrum analyzer

Spectrum Analyzer

2.5GHz CLOCK 4 x 2.5Gb/s DATA PRBS Generator

Oscilloscope

Transmitter Chip

10Gb/s DATA BERT

~

oscilloscope can be triggered either by a subrate clock signal (for eye diagram) or by a bitframe signal (for bit pattern)

9


5GHz CLOCK

Trigger

IBM Research

10 Gb/s Transmitter Output (Unequalized) AVTT=1.65V / 42mA VDDA=1.2V / 32mA T=25C, 27-1 PRBS, tap0=tap3=0

10

tap1= +111100


tap2= -00000

IBM Research

10 Gb/s Transmitter Output (with Equalization) AVTT=1.65V / 50.4mA VDDA=1.2V / 32mA T=25C, 27-1 PRBS, tap0=tap3=0

11

tap1= +111100


tap2= -11100

IBM Research

10 Gb/s Transmitter Output AVTT=1.65V / 42mA VDDA=1.2V / 32mA T=25C, 27-1 PRBS, tap0=tap3=0

12

tap1= +111100


tap2= -00000

IBM Research

10 Gb/s Transmitter Output AVTT=1.65V / 45.5mA VDDA=1.2V / 32mA T=25C, 27-1 PRBS, tap0=tap3=0

13

tap1= +111100


tap2= -10000

IBM Research


14

tap1= +111100


tap2= -01000

IBM Research


15

tap1= +111100


tap2= -11000

IBM Research


16

tap1= +111100


tap2= -00100

IBM Research


17

tap1= +111100


tap2= -10100

IBM Research


18

tap1= +111100


tap2= -01100

IBM Research


19

tap1= +111100


tap2= -11100

IBM Research


20

tap1= +111100


tap2= -00010

IBM Research


21

tap1= +111100


tap2= -11110

IBM Research


22

tap1= +101100


tap2= -11110

IBM Research


23

tap1= +111000


tap2= -11110

IBM Research


24

tap1= +001000


tap2= -11110

IBM Research


25

tap1= +100000


tap2= -11110

IBM Research

10 Gb/s Eye Diagram at 25° C error-free operation at 231-1 PRBS, AC-coupled load tap0 = tap3 = 0, tap 1 = +111111, tap2= -00100 AVTT = 1.2V (38mA), VDDA = 1.2V (43mA), Vpp = 295mV (x2), Jitter p-p = 23ps

26


IBM Research


27


IBM Research


28


IBM Research


29


IBM Research

Performance Summary error-free operation at 10 Gb/s, 231-1 PRBS, AC-coupled load AVTT T, °C

30

VDDA

Vpp, mV

Power, mW V

mA

V

mA

125

468 x2

1.65

80

1.2

35

174

125

302 x2

1.2

51

1.2

27

94

100

497 x2

1.65

82

1.2

27

167

100

339 x2

1.2

52

1.2

27

95

70

535 x2

1.65

83

1.2

28

171

70

380 x2

1.2

51

1.2

28

95

70

235 x2

1.0

34

1.0

23

57


IBM Research

Equalization of a 16” link (standard Tyco HM-Zd XAUI test backplane)

unequalized

equalized

• Data rate: 6.3 Gb/s • Test sequence: 27-1 PRBS • BER (of equalized data): < 10-11 • All 4 FFE taps are used to open the eye • Data rate is limited by the sensitivity of the single-ended BER tester ( no filtering on the Rx side) • Test backplane introduces ~20dB of losses at 3GHz 31


IBM Research

Conclusions 10 Gb/s error-free operation is demonstrated at 125 °C (231-1 PRBS, 0.9 Vppd into AC-coupled channel, 170mW total power). Maximum Vppd is higher at lower temperatures. Maximum error-free data rate: 14 Gb/s at 25 °C Low-power CML part is error-free at 1.0V supply at up to 70 °C, and at 1.2V at higher temperatures Integrated version of the Tx successfully evaluated, will be reported in paper “A 10Gb/s 5-tap DFE / 4-Tap FFE Transceiver in 90nm CMOS Technology” M. Meghelli et al., accepted for ISSCC 2006

32


IBM Research

Backup slides

33


IBM Research

6-bit IDAC Performance tap0 = tap2 = tap3 = 0 AVTT = 1.65V, T=100°C

• bits 1:4 are linear • current jumps when bits 5 and 6 are turned on • headroom compression clearly visible at high currents

75 70 65 60

AVTT current ( mA )

55 50 45 40 35 30 0

16

32

bit settings (tap1) 34


48

64

IBM Research

TX Only Characterization* 10Gb/s Eye Diagrams

10Gb/s Eye with -15% on FFE tap2 Main tap 600mVpd

27-1 ¼ rate data inputs leading to a serial PRBS length of 505 (serial output measured with a spectrum analyzer)

* “A 10Gb/s 5-tap DFE / 4-Tap FFE Transceiver in 90nm CMOS Technology” M. Meghelli et al., accepted for ISSCC 2006 35


IBM Research

10Gb/s Channel Equalization Experiment Tyco 16” Channel (Hm-Zd XAUI Test Backplane) The evaluation channel Includes: Tx package->Evaluation board->12” cable->16” Tyco backplane->12” cable->Evaluation board->Rx package

33.4dB losses at 5GHz

36
