IEEE ELECTRON DEVICE LETTERS, VOL. 22, NO. 10, OCTOBER 2001
487
Sub-60-nm Quasi-Planar FinFETs Fabricated Using a Simplified Process Nick Lindert, Leland Chang, Yang-Kyu Choi, Erik H. Anderson, Wen-Chin Lee, Tsu-Jae King, Senior Member, IEEE, Jeffrey Bokor, and Chenming Hu, Fellow, IEEE
Abstract—N-channel double-gate metal-oxide-semiconductor field-effect transistor (MOSFET) FinFETs with gate and fin dimensions as small as 30 nm have been fabricated using a new, simplified process. Short channel effects are effectively suppressed when the Si fin width is less than two-thirds of the gate length. Drive current for typical devices is found to be above 500 A m (or 1mA m, depending on the definition of the width of the Vt = Vd = 1 V. The electrical double-gate device) for Vg gate oxide thickness in these devices is 21A, determined from the first FinFET capacitance-versus-voltage characteristics obtained to date. These results indicate that the FinFET is a promising structure for the future manufacturing of integrated circuits with sub-60-nm feature size, and that double-gate MOSFETs can meet international technology roadmap for semiconductors performance specifications without aggressive scaling of the gate-oxide thickness. Index Terms—Double-gate, double-resist process, fin, FinFET, MOSFET, short-channel effects, SiGe gate.
I. INTRODUCTION
T
HE double-gate metal-oxide-semiconductor field-effect transistor (MOSFET) structure minimizes short channel effects to allow for more aggressive device scaling [1]. Simulations have shown that it should be scalable to 10-nm gate length [2], [3]. In the past, process complexity posed a serious technological barrier to the development of double-gate devices. In 1998, Hisamoto et al. introduced the FinFET and demonstrated a process that yielded n-channel devices with promising performance and scalability [4]. The FinFET uses a single poly-Si layer deposited over a silicon fin patterned to form perfectly aligned gates straddling the fin structure for optimal performance. P-channel FinFETs were subsequently demonstrated using a and similar fabrication process and showed excellent characteristics [5]. In this letter, we present a new FinFET fabrication process that is simpler and results in lower gate-to-drain capacitance, as compared with the original process. This improved process is demonstrated to yield devices with excellent Manuscript received June 27, 2001; revised July 30, 2001. This work was sponsored by DARPA AME Program under Contract N66001-97-1-8910 and by Semiconductor Research Corporation under Contract 2000-NJ-850. The review of this letter was arranged by Editor A. Chatterjee. N. Lindert, L. Chang, Y.-K. Choi, T.-J. King, J. Bokor, and C. Hu are with the Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94709 USA. E. H. Anderson is with the Lawrence Berkeley National Laboratory, Berkeley, CA 94720 USA. W.-C. Lee is with Intel Corporation, Hillsboro, OR 97006 USA (e-mail:
[email protected]). Publisher Item Identifier S 0741-3106(01)08866-8.
Fig. 1. (a) Three-dimensional illustration of the quasi-planar FinFET. (b) Layout view and cross-sectional view of the quasi-planar FinFET. Because the gate modulates current on both sides of the fin, the effective channel width W is considered to be twice the fin height.
current drive with limited short-channel effects down to 50-nm gate length. II. DEVICE FABRICATION The simplified FinFET structure illustrated in Fig. 1 is fabricated as follows: SOI wafers are thermally oxidized to produce 50-nm silicon films with a 50 nm hard-mask oxide. Phosphorus implants are used to achieve n-type channel doping in cm to cm . A double-resist process the range of similar to that described in [6] is used to define narrow fins and large-area patterns simultaneously. In this letter, 250-nm optical G-line resist is patterned first and hard baked at 170 C ; 200-nm SAL-601 is subsequently coated and patterned using e-beam exposure providing critical fin dimensions down to 30 nm. The two resist patterns are then transferred to the SOI with a single reactive ion etch (RIE). After the silicon fins are etched, 2.5-nm sacrificial oxide is grown and removed to improve the fin sidewall surface prior to gate oxidation without seriously undercutting the buried oxide. The gate stack includes a 50-m oxide hard mask on top on 1.8-nm SiO of 240-nm in-situ boron-doped Si Ge gate oxide. The Si Ge gate composition is chosen to provide the desired threshold voltage [3], [7]. Fig. 2(a) shows a top-view scanning electron microscope (SEM) of a 50-nm gate
0741–3106/01$10.00 © 2001 IEEE
488
IEEE ELECTRON DEVICE LETTERS, VOL. 22, NO. 10, OCTOBER 2001
Fig. 2. (a) Scanning electron microscope (SEM) top view of a 50-nm gate over a 40-nm fin. (b) Transmission electron microscope (TEM) cross–sectional view along the gate through the fin. The 2.5-nm sacrificial oxidation before gate oxidation results in minimal buried oxide undercutting. (c) High-resolution TEM view. Gate oxide uniformity is excellent, even around the corner of the fin.
over a 40-nm fin prior to spacer formation. The gate-to-drain misalignment tolerance for this experiment was 100 nm, but tighter tolerances can be achieved with improved e-beam stepping software. Transmission electron microscope (TEM) cross-sectional views of the fin are shown in Fig. 2(b) and (c). The triangular hard-mask shape and the trapezoidal fin are a result of using CHF during part of the Si RIE. The high-resolution TEM cross section shows a uniform 1.8-nm gate oxide and a smooth Si-SiO interface. After double-layer spacers of 37.5-nm nitride on 10-nm oxide are formed, arsenic and phosphorus ions are implanted to form the source and drain. A 600 C anneal is used to recrystallize any portion of the silicon fin amorphized by the heavy As implant. This is followed by a short 900 C activation anneal and a 450 C forming gas anneal. No silicide or metal was used in the devices reported here. III. RESULTS The effective channel width ( ) of a FinFET device is defined to be 2 (fin height) (number of fins). Most of the devices in this letter use a single fin, so is 100 nm. Larger devices are possible with multiple fins [4], [5]. Multiple-fin devices can exceed the area efficiency of traditional planar devices if the fin height is greater than half the pitch. The fin height, however, is limited due to aspect ratio and topography considerations. Measured current–voltage (I-V) characteristics for a 50-nm FinFET with 30-nm fin width are shown in Fig. 3. For V and V, A m. An alternative, more aggressive definition of as simply the fin height would effectively double the reported current to 950 A m. Also shown in Fig. 3(b) is the effect of swapping the source and drain connections. The difference in current results from the asymmetric
Fig. 3. (a) Subthreshold characteristics for a FinFET with L = 50 nm and W = 30 nm. (b) I V curves for the same device. V 1:48 V so I (V V = 1 ;V = 1 V ) 475 A/m, or 950 A=m if W is defined as the fin height. The dashed curve corresponds to V = 2:5 V with the source and drain connections swapped.
0
0
source/drain (S/D) resistance due to misalignment. Because of the large resistance in the smallest fins between the gate edge and the wide S/D area, the smallest devices do not provide the largest current; devices with larger fins and gates provide current up to 620 A m. Improved e-beam alignment or silicidation of the fin can alleviate such effects. cm Despite the n-type channel doping in the range of to cm , the is 1.2–1.7 V. This threshold voltage range is higher than the expected 0.5–0.7 V for a p-type Si Ge gate with a work function of approximately 4.8e V. Potential causes for this high include: poor gate oxide interface quality as a result of etch damage or boron penetration from the gate through the gate oxide. Plasma hydrogenation and additional forming gas anneals lowered the threshold by about 0.2 V, suggesting that there was etching damage, but not enough to explain in excess of 1.2 V. P-channel MOSFETs using a similar approximately 1.0 V more posprocess sequence also yield itive than expected, indicating that the body doping for both n and p-channel devices are highly p-type despite the n-type body
LINDERT et al.: SUB-60-nm QUASI-PLANAR FINFETS FABRICATED
Fig. 4. Drain induced barrier lowering (DIBL) as a function of L =W . DIBL is evaluated as the gate voltage shift between the V = 0:05 V and V = 1:0 V curves at I = 10 A. The gate length should be at least 1.4 times the width of the fin to control short-channel effects.
489
The first ever capacitance–voltage (C-V) data for FinFET devices are shown in Fig. 5. These devices have 200 fins and a total area ( ) of 100 m . The applied gate voltage is limited to 2.5V to avoid excessively high electric field in the oxide. From these curves the electrical oxide thickness is found to be 2.1 nm. This is 0.3 nm higher than the physical oxide thickness, which is accounted for by the inversion-layer QM effect [8]. Poly gate depletion does not occur because the NMOSFET has a p-type gate. The fact that a 200-fin device generates gate capacitance exactly as predicted is evidence that the yield for this quasi-planar FinFET process is high and the manufacturability is promising. IV. CONCLUSION A simplified FinFET process has been developed and results for n-channel devices with gate lengths down to 45 nm are presented. The data indicate that the FinFET is very scalable. Improved drive current for future devices can be realized by lowwith improved gate work function engineering and ering . Further improvements can also be made by with thinner using raised S/D [9], [10] or silicided S/D structures. REFERENCES
Fig. 5. Inversion capacitance for 100m devices with 70-nm and 55-nm fin widths. The electrical oxide thickness is extracted to be approximately 2.1 nm, 0.3 nm greater than the physical oxide thickness. Poly gate depletion does not occur because the NMOSFET has a p-type gate. Measured at 1MHz.
implants. Perhaps 18A gate oxides grown on vertical fins are more susceptible to boron penetration than expected. FinFET turnoff characteristics depend heavily on the fin in this width as shown in Fig. 4. The data suggest that without suffering case study can be scaled down to 1.4 from severe short-channel effects, even with n-type channel in this letter is approximately 30 doping. The minimum nm. This is an extremely aggressive nm, so for a relatively thick physical gate oxide thickness (1.8 nm). Such de-coupling of short channel effects to channel doping and oxide thickness is critical for scaling MOSFETs down to 10 nm.
[1] H.-S. P. Wong, D. J. Frank, and P. M. Solomon, “Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFETs at the 25 nm channel length generation,” in IEDM Tech. Dig., 1998, pp. 407–410. [2] L. Chang and C. Hu, “MOSFET scaling into the 10 nm regime,” in Nanoelectronics Workshop, 2000, pp. 351–355. [3] L. Chang, S. Tang, T.-J. King, J. Bokor, and C. Hu, “Gate length scaling and threshold voltage control of double-gate MOSFETs,” in IEDM Tech. Dig., 2000, pp. 719–722. [4] D. Hisamoto, W.-C. Lee, J. Kedzierski, E. Anderson, H. Takeuchi, K. Asano, T.-J. King, J. Bokor, and C. Hu, “A folded-channel MOSFET for deep-sub-tenth micron era,” in IEDM Tech. Dig., 1998, pp. 1032–1034. [5] X. Huang, W.-C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y.-K. Choi, K. Asano, V. Subramanian, T.-J. King, J. Bokor, and C. Hu, “Sub 50-nm FinFET: PMOS,” in IEDM Tech. Dig., 1999, pp. 67–70. [6] J. Kedzierski, E. Anderson, and J. Bokor, “Calixarene G-line double resist process with 15nm resolution and large area exposure capability,” J. Vac. Sci. Technol. B, vol. 18, no. 6, pp. 3428–3430, Nov. 2000. [7] Y. Taur, “An analytical solution to a double-gate MOSFET with undoped body,” IEEE Electron Device Lett., vol. 21, pp. 245–247, May 2000. [8] S. Hareland, S. Krishnamurthy, S. Jallepalli, Y. Choh-Fei, K. Hasnat, A. F. Tasch Jr, and C. M. Maziar, “A computationally efficient model for inversion layer quantization effects in deep submicron n-channel MOSFETs,” IEEE Trans. Electron Devices, vol. 43, pp. 90–96, Jan. 1996. [9] Y.-K. Choi, K. Asano, N. Lindert, V. Subramanian, T.-J. King, J. Bokor, and C. Hu, “Ultrathin-body SOI MOSFET for deep-sub-tenth micron era,” IEEE Electron Device Lett., pp. 254–255, May 2000. [10] Y.-K. Choi, Y.-C. Jeon, P. Ranade, H. Takeuchi, T.-J King, J. Bokor, and C. Hu, “30 nm ultra-thin-body SOI MOSFET with selectively deposited Ge raised S/D,” in DRC 2000, pp. 23–24.
