Implementation of Active Disturbance Rejection Control on FPGA

Implementation of Active Disturbance Rejection Control on FPGA Momir Stankovic, Stojadin Manojlovic, Slobodan Simic, Zoran Jovanovic

Abstract— Implementation of Active Disturbance Rejection Control (ADRC) on Field Programmable Gate Array (FPGA) was presented in this paper. Discrete ADRC for speed servo system with predictive and current extended state observer (ESO) was derived and compared by simulation. A hardware design of ADRC using high-level blocks and system-level hardware design tools, actually Xilinx’s System Generator™ is presented. The experimental results largely agree with simulation and maintain good system’s performance regardless different working conditions with external disturbance. Index Terms— active disturbance rejection control, speed servo system, FPGA.

I. INTRODUCTION Since Han has introduced Active Disturbance Rejection Control (ADRC) in 90’s, it has become an alternative to PID and modern control schemes which are based on precise model of system. In [1] concept of ADRC is described and four distinct measures which overcome the weaknesses of the PID control are proposed: 1) a transient trajectory generator; 2) tracking differentiator; 3) the nonlinear control laws; and 4) estimation and rejection of total disturbance. The basic idea of the ADRC is to treat unmodeled dynamics, parameter perturbations and external disturbances as one, total disturbance. Including the total disturbance as additional state, it can be estimated using extended state observer (ESO) and rejected in the real time. In this way the system is transformed into integral-chain form of the r-th order, where r is the relative order of the system. Such structure can effectively be controlled with appropriate state feedback algorithm. The ADRC can be effectively applied in various areas [2-4]. Discrete implementation and generalization of the ESO are investigated and compared in [5]. It is shown that the current discrete formulation is superior to the predictive one in reducing the delay associated with the sampling process. In recent years FPGA becomes very popular platform for hardware implementation. For purposes where there is a need

for faster control or control of more parallel processes the FPGAs now represent an alternative to general purpose programmable DSPs and microcontroller or microprocessor based platforms. Microprocessors, dedicated DSP hardware, memory, and speed input-output components i.e. a whole microcomputer system can be realized on a single chip. The available hardware resources and the speed that can be achieved are often much greater than the requirements of the typical problems that are before them [6,7]. In this paper the application of ADRC concept is briefly described on the second order system. Two types of discrete ADRC, with predictive and current ESO, for speed servo system are designed and compared trough simulation. Based on Simulink the System GenaratorTM model is generated by Xilinx’s toolbox components. The behavioral VHDL description of this design is placed and routed on FPGA chip by the ISETM 14.7 tool. Experimental and simulation results are compared and hardware resources occupancy and speed are analyzed. II. ACTIVE DISTURBANCE REJECTION CONTROL Without loss of generality, the second order SISO system will be used to describe the ADRC concept. The second order system dynamics is given by:

&y&(t ) = g ( y, y& , t ) + w(t ) + b(t )u (t ) ,

(1)

where u (t ) and y (t ) are the input and output of the system, respectively. The nonlinear function g (⋅) represents the internal dynamics of the system, and with w(t ) the external disturbances are modeled. Including perturbations of the system parameter b(t ) , it can be represented with:

b(t ) = b0 + ∆b(t ) ,

(2)

where b0 is the best approximation of the constant, and

∆b(t ) is its perturbed value. Now (1) can be reformulated: Momir Stankovic – Vojna akademija, Univerzitet odbarane u Beogradu, Pavla Jurišića 31, 11000 Beograd, Srbija (e-mail: [email protected]). Stojadin Manojlović – Vojna akademija, Univerzitet odbrane u Beogradu, Pavla Jurišića 31, 11000 Beograd, Srbija (e-mail: [email protected]). Slobodan Simic – Vojna akademija, Univerzitet odbrane u Beogradu, Pavla Jurišića 31, 11000 Beograd, (e-mail: [email protected]). Zoran Jovanovic – Elektronski fakultet, Univerzitet u Nišu, Aleksandra Medvedeva 14, 18000 Niš, Srbija (e-mail: [email protected]).

&y&(t ) = b0u (t ) + g ( y, y& , t ) + w(t ) + ∆b(t )u (t ) ,

(3)

or in more compact form:

&y&(t ) = b0u (t ) + f (t ) ,

(4)

introducing f (t ) = g ( y , y& , t ) + w(t ) + ∆b(t )u (t ) as total disturbance [1]. Choosing the states: x1 = y , x2 = y& , x3 = f the state space model of (4) has

u (t ) =

 x&1  0 1 0  x1   0   0  x&  = 0 0 1   x  + b  u + 0 f& = Ax + Bu + Ef&  2   2  0    x&3  0 0 0  x3   0  1  y = [1 0 0][ x1

x2

Y ( s) ωc2 . = R ( s ) ( s + ωc ) 2

x3 ] = Cx.

l2

ωobs = (3 ÷ 10)ωc .

The control loop structure of ADRC for the analyzed process is presented in the Fig. 1.

1/b0

-

u (t )

y (t )

Process

-

T

ESO

kd

λ ( s ) = ( s + ω obs ) ,

ωobs

-

kp

l3 ] could be selected so 3

and

(13)

(6)

the all observer poles are the same:

λ (s)

(12)

with bandwidth ωc . To work properly the observer dynamics must be fast enough, so its bandwidth has to be 3-10 times wider than the closed loop, i.e.[8]:

r (t )

where

and kd = 2ωc will lead to adjustable closed

(5)

It can be seen, that LESO is in the form of the Luenberger observer, while in the original case of ADRC, a nonlinear observer was employed [1]. In order to simplify the design,

[

(11)

loop dynamics:

The equations for the linear extended state observer (LESO), based on (5) are given in (6).

the observer gains L = l1

2

T

 x&ˆ1   xˆ1   l1    &xˆ =  x&ˆ  = A  xˆ  + Bu + l  ( y − xˆ ) 2 1  2  2 &   xˆ3   l3  ˆ x    3  yˆ LESO = xˆ

.

b0

where r (t ) is reference input. Selecting controller parameters as k p = ωc

form:

k p (r (t ) − xˆ1 (t )) − k d xˆ 2 (t ) − xˆ3 (t )

(7)

fˆ (t ) = xˆ3 (t )

y&ˆ (t ) = xˆ2 (t ) yˆ (t ) = xˆ1 (t )

is the characteristic polynomial of the LESO,

is its bandwidth. In that case observer gains

become:

L = 3ωobs

2 3ωobs

3  ωobs

Fig. 1. Control loop structure of ADRC for the second order process

It has to be noted, that in the proposed concept the relative order r and the approximate value of the system parameter b0

T

(8)

The total disturbance can be rejected using its estimate xˆ3 with [1]:

are the necessary a priori knowledge of the controlled system. Moreover, the closed loop system has only one adjustable parameter ωc . III. DISCRETE FORM OF ADRC

u (t ) =

u 0 (t ) − xˆ3 (t ) . b0

(9)

Substituting (9) into (4) the system transforms to the second order integral chain structure: &y&(t ) ≅ u0 (t ) , (10) where the control law u0 (t ) is to be selected. As LESO estimates output of the system and its derivation, a simple PD controller can be implemented, so the complete ADRC gets form:

Because the PD is linear form control law, for discrete ADRC only discrete form of LESO is need. Applying Euler, ZOH or FOH method with sampling period Ts discretized form of (6) can be created:

xˆ (k + 1) = Φ xˆ (k ) + Γu ( k ) + Lp ( y( k ) − yˆ (k )) yˆ (k ) = Hxˆ (k ) + Ju ( k )

(14)

The observer (14) is known as a predictive discrete estimator because the current estimation error e(k ) = y (k ) − yˆ (k ) is used to predict the next state

estimate xˆ ( k + 1) . In order to reduce computation time delay, which can cause the closed loop instability for low sample rates, the current discrete estimator is suggested [5]. If predictive estimator gain vector is defined as:

L p = ΦL c .

(15)

IV. SIMULATION RESULTS Speed servo system with ADRC is simulated in MATLAB®/Simulink. The parameters of the armature controlled DC motor and tacho are previously identified [9] and shown in Table 1. TABLE I PARAMETERS OF DC MOTOR AND TACHO

we get current discrete estimator form: xˆ ( k + 1) = Φ ( xˆ (k ) + L c ( y (k ) − H xˆ ( k )) + ( Γ − ΦL c J )u ( k ) (16)

Parameter Armature resistance Armature inductivity

where the new state

Moment of inertia

x (k ) = xˆ ( k ) + Lc ( y (k ) − H xˆ ( k )) = xˆ (k ) − Lc ( y (k ) − yˆ (k )) (17)

Coefficient of viscous friction Electromechanical constant

includes a current time step update [5]. The outputs of the observers are:

y p (k ) = xˆ (k ) y c (k ) = x (k ) = (I − Lc H)xˆ (k ) − Lc Ju(k ) + Lc y(k )

(18)

where subscripts p and c stands for predictive and current discrete estimator form. For given ωc according to (13) the continuous observer

poles are calculated. The relation between the discrete ( β ) and the continuous ( ωobs ) observer poles is:

β = e −ω

obsT s

.

(19)

Mechanical-electrical constant Constant of tacho

Ra La Je Fe kem kme ktg

Value 8.91 Ω 4.5 mH 2.93e-5 kg m2 11.7e-5 kg m2/rad/s 0.103 Nm/A 0.103 V/rad/s 0.0191 V/rad/s

The model of the servo system is described with differential equation:

&& y = −204.21 y& − 8.93 ⋅103 y + 7.89 ⋅104 u + w . (25) where u is armature voltage, y is DC rotor shaft angular rate and external disturbance is modeled with w . As discussed in Sections II and III the models of continuous and discrete ADRC with both, predictive and current LESO are formed. For observer is chosen ωobs = 5ωc and ωc = 120 rad / s .

Reference tracking performances of all structures is presented in Fig. 3, for different sample rates. Load disturbance of 0.3 Nm is included in time intervals 0.2-0.3 s and 0.5-0.6 s, as STEP function. Integral of absolute error as tracking quality performance is λ p ( z ) = zI - (Ф - Lp H) = ( z − β )3 (20) calculated for all cases and summarized in Table II. λc ( z ) = zI - (Ф - ФLc H) = ( z − β )3 (21) It can be seen that discrete ADRC with current LESO responds very similar to continuous one. The discrete ADRC with predictive ESO works properly for low period of for L p and L c we get: discretization (Ts< 1 ms). As the Ts increase, its performance degraded, and for Ts > 2.6 ms the closed loop system became Lp = 3(1 − β ) β / (2 Ts )(− β 2 + 9β − 15) 1/ Ts 2 (1 − β )3  (22) unstable. Lc = 1 − β 3 3 / (2Ts )(1 − β ) 2 (1 + β ) 1/ Ts 2 (1 − β )3  .(23) TABLE II When all observer poles are in the same location, solving the discrete characteristic equations

INTEGRAL ABSOLUTE ERROR

If the state space model (6) is discretized applying ZOH method, matrices in (14) have form:

Sample rates

Ts=2.6 ms

1 TS  Φ = 0 1 0 0 

b T / 2  T / 2    TS  , Γ =  b0TS  ,  0  1    Η = [1 0 0] , J = [ 0 ]. 2 0 S

(24)

Discrete ADRC (with predictive ESO) Discrete ADRC (with current ESO)

Ts=0.1 ms

6.617

Continual ADRC 2 S

Ts=1 ms

15.781

7.961

6.728

7.151

6.457

6.455

Ts=2.6ms

reference continual predictive current

r,y[rad/s]

100 50 0 0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.1

0.2

0.3

0.4 time [s]

0.5

0.6

0.7

Ts=1ms

r,y[rad/s]

100 50 0 0 Ts=0.1ms

r,y[rad/s]

100 50 0 0

Fig. 4. Experimental platform

Fig. 2. ADRC tracking reference for different Ts

It should be noted that there is an overshoot in responses, although the controller is designed to track step reference without any overshoot, see (12). The assumption that system is double integrator depends on the quality of total disturbance estimation and rejection. The real value of f and its estimation, for continues case is presented in Fig. 3. The quality of estimation depends on bandwidth of observer, especially in transient period. Due to the total disturbance is not rejected completely. 0

x 10

estimated

Fig. 5. Functional scheme of system

real

-4

f

u

5

-2

-6 -8 -10 -12

Ua

0.05

0.075

0.1 Time [s]

0.125

0.15

Fig. 3. Estimated vs real total disturbance

V. ADRC IMPLEMENTATION ON FPGA ADRC is implemented and verified on laboratory speed servo system by Spartan 3A FPGA XC700A chip. Photo of experimental platform, which consists of DC motor with tacho, power amplifier, Spartan 3A/3AN Starter Kit evaluation board, digital scope, personal computer and supply panel is shown in Fig. 4. Beside XC700A FPGA chip, evaluation board contains many peripherals. We used 2channel 12-bit width A/D converter, 2-channel 12-bit width D/A converter and RS232 module. Functional scheme of realized system is presented in Fig. 5.

The architecture of ADRC law (11) with current discrete LESO (17), was modeled using the VHDL and Xilinx’s System GenartorTM [7]. The behavioral VHDL description of this design is placed and routed on Spartan 3A, XC700A device by the ISETM 14.7 tool. System GenartorTM model and its subsystem is presented in Fig. 6 and 7. Arithmetic operations of addition and multiplication were realized with Int Clock period of 20 ns. Period of discretization for whole system was 4096 times higher, Ts=81.92μs. Design was pipelined in order to achieve synchronization in operation. It means that all adders and multipliers are followed by registers. Latency introduced on this way is of order Int Clock period, so it does not contribute to system delay defined by period of discretization. Signal taho is discretized output of tacho generator by A/D converter. Reference signal (ref), step function with amplitude of 100 rad/s, was determined by VHDL description. Discrete signal Ua was converted to its analog form and then 10 times amplified to produce the analog control signal u. The maximum value of control signal was limited on 33V, due to saturation of used amplifier. Data obtained from scope are stored on personal computer by RS232 interface and reproduced by MATLAB®.

y

TABLE III RESOURCES UTILIZATION FOR SPARTAN 3A XC700A FPGA DEVICE In

taho

↑ 4096

z-1 x 52.36

Up

M4

In

ref

a -1 z-1 z a-b x 3.861e-005 b

↑ 4096 Up Sp

a

a

z a-b b

-1

-1 z a-b

z x 1.44e+004

b

-1

M3

A3

z-1 x 0.1

z-1

Out

↓ 4096

Ua

Slices count (max 5888)

DSP mult. (max 20)

Speed (MHz) (max. 250MHz)

2145 (36%)

16 (80%)

52.9MHz

Down Sp

M5 z-6

A2

VI. EXPERIMENTAL VALIDATION

M1

A1

Del ay -1

M2

z x 240

x1 k-1

Step responses and control signals of simulation models designed by Simulink and System GeneratorTM are compared with experimental results and are shown in Fig. 8. In all cases bandwidths of closed loop system and observer were chosen as , ωc = 120rad / s and ωobs = 5 ωc ,

y u x3

k

x2

X3 x1 k-1

y u x3

k

respectively. For the purpose of fair comparison saturation of control signal on 33V and measurement noise with variance δ =0.001 V2 were added in simulation models.

x2

X2 x1 k-1

Sy stem Generator

y u x3

k

x2

X1

120 100

model of ADRC r,y [rad/s]

Fig. 6. System Genartor

TM

-1

z x (-1.665e+004) M1 -1

5 x2

z x (-1.375)

a

z a+b b A1

a -1 a z+ b b A4

M2 -1

2 y

z x 1.665e+004 M3 -1

3 u

z x (-1.438) M4

4 x3

a z-1 a+b b A2

60 40 20

-2

0

z-6

Del ay

z

-1

4096 ↓ 4096 ↑

2 -1

z a+b b

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

1 k-1

Down sp Up Sp a

0

40 30

u [V]

1 x1

Experimental Simulink SysGen Reference

80

20

k

A3

z-2 x 0.9999

10 0

time [s] Fig. 8. Experimental vs simulation results

M5

Fig. 7. System GenartorTM model of subsystem X3

The proposed controller designed by System GeneratorTM has the same structure as in basic Simulink. It is good for take of clarity, but is not optimal for hardware resources occupancy. Overview of resource utilization is shown in Table III. The logic and DSP resources occupancy: slices count of 36% and dedicated multipliers of 80% restrict the realization of only one controller per chip. Hardware design works well at maximal speed of 52.9 MHz (minimal clock period of 18.9 ns) as reported by ISE design tool.

We can note that experimental results largely agree with simulation. Minor deviation between Simulink and System Generator models are consequence of the quantization error in System generator blocks and experimental results are different from System Generator model response due to servo system model uncertainty. The influence of varying load on the motor shaft was tested using magnetic break. System starts with maximal load and after 0.4 second, load was removed completely. Experimental results for step response and control signal for the considered case was shown in Fig. 9. As it can be seen, despite the significant changes of working conditions the system was maintained good tracking performance. The value of control signal saturates due to amplifier limitation, which influence the system time response.

40

ua[V]

100 y

y [rad/s]

ua

20 50

disturbance. The fact that discretization period of system is several orders of magnitude times higher than Int Clock of chip, provides opportunity to optimize hardware design in order to reduce number of used dedicated multipliers. That enables implementation of more controllers on the same FPGA chip. which will be the objective of future resarch. REFERENCE

0

0

0.1

0.2

0.3

0.4 time [s]

0.5

0.6

0.7

0 0.8

Fig. 9. Experimental results with varying load

VII. CONCLUSION Based on little knowledge about system, ADRC represent new and elegant approach in solving control problems . Two discrete implementations of ADRC for speed servo system are studied and compared in this paper. It is shown that implementation with current discrete ESO is superior to the predictive discrete ESO. The system has been implemented on Spartan 3A FPGA device. A hardware design of ADRC using high-level blocks and system-level hardware design tools, actually Xilinx’s System Generator™ is presented. The availability of such varied libraries of functions brings great power in control design. It is no longer requires expert knowledge about FPGA design and that allowing designer to concentrate on the control problem. The experimental results show largely agree with simulation and maintain good system’s performance regardless on different working conditions, as external

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