(34). If the maximum ripple currents on the output inductors are equal to 0.2io,max at D=0.5, then the output inductances are expressed as: max,o o. 2. 1 i/TV5.2.
PEDS2009
Implementation of an Interleaved ZVS Forward Converter B. R. Lin, H. K. Chiang, J. J. Chen, J.-J. and C. Y. Cheng Dept. of Electrical Engineering National Yunlin University of Science and Technology, Yunlin 640, Taiwan on the output capacitor is reduced. Only two power switches are used in the proposed converter to achieve interleaved operation and ZVS feature. The circuit configuration, principle of operation and design considerations are presented. Finally, experiments based on a laboratory prototype are presented to verify the theoretical analysis.
Abstract—A parallel zero voltage switching (ZVS) forward converter with half-bridge topology is presented in this paper. Two converter modules are connected in parallel in the output side to share the load current. In the primary side, two converter modules use the same power switches so that the semiconductor devices are reduced in the proposed converter compared with the conventional interleaved half-bridge converter. The asymmetrical pulse-width modulation (APWM) is used to regulate the output voltage and realize the ZVS turn-on of switches at the transition interval. The voltage stress of switches is clamped at the input source voltage. The system analysis, operation principle and design consideration of the proposed converter are presented. Finally experimental results based on a laboratory prototype are provided to verify the effectiveness of the proposed converter.
I.
II.
INTRODUCTION
Interleaved forward converters have been widely used for high current and high power applications such as telecommunication and computer systems [1-2]. In interleaved converters by phase shifting of the control signals of several modules, the currents through the switches are just fractions of the input current. The input current ripple and the conduction losses are reduced so that the converter efficiency is improved [3-4]. However, the converters are still operated in the hard switching, resulting in large switching losses and the serious electromagnetic interference (EMI) problem. Resonant converters with zero voltage switching (ZVS) can enable power converters to operate at high switching frequency. However, high voltage stresses on the switches are the main drawback of these techniques if the high input voltage is required in the converters. Active clamp topologies [5-6] including an auxiliary switch and a clamped capacitor were proposed to limit the peak voltage of switches and achieve ZVS on switches. When the auxiliary switch was turned on, the voltage of the clamp capacitor is reflecting to the primary side of the transformer such that the primary current will reduce and reverse the direction. The energy stored in the leakage and magnetizing inductors will release to the output load. Therefore, no flux reset circuit is needed in the forward converters. The parallel-connected forward converters with ZVS technique have been presented in [7-8] for high output current applications. However, the main drawbacks of these schemes are complex control approach and too many power switches in the circuit. This paper presents an interleaved asymmetrical half-bridge converter which combines two converter modules with the same half-bridge leg to share the load current and reduce the input and output ripple currents. The APWM modulation is adopted to regulate the output voltage and realize the ZVS turn-on for power switches. Two converter modules are operated in the interleaved PWM scheme so that the output inductor ripple currents are partially cancelled each other. Therefore, the ripple voltage
854
CIRCUIT CONFIGURATION AND OPERATION PRINCIPLE
The configuration of the proposed converter is shown in Fig. 1. There are two ZVS half-bridge converter modules in Fig. 1. The converter module 1 includes circuit components of S1, S2, Cr1, Cr2, C1, Lr1, T1, D11, D12, L1 and Co. The converter module 2 includes circuit components of S1, S2, Cr1, Cr2, C2, Lr2, T2, D21, D22, L2 and Co. The driving signals of S1 and S2 are complementary each other with a small delay time. During the transition interval, the resonant inductors Lr1 and Lr2 and the output capacitors Cr1 and Cr2 are resonant to allow the ZVS turn-on of switches S1 and S2. The voltage stresses of switches are clamped at input source voltage Vin. When S1 is turned on, power is transferred from input source Vin to the load through S1, C1, Lr1, T1, D11 and L1. The output inductor current iL1 increases linearly. The transformer T2 is in the flux reset mode through Vin, S1, C2 and Lr2. The output inductor current iL2 in converter module 2 flows through L2, Co and D22. Thus, the inductor current iL2 decreases linearly. When S2 is turned on, the output inductor current iL1 decreases and iL2 increases linearly. Thus, the ripple current on the output capacitor Co is reduced.
Fig. 1 Circuit configuration of the proposed converter.
The following assumptions are made to simplify the system analysis. All semiconductors are assumed ideal and the output capacitance of Co is large enough to be a constant voltage. The capacitances of C1 and C2 are larger than the capacitances of Cr1 and Cr2. The magnetizing inductances Lm1 and Lm2 of transformers T1 and T2 are greater than the inductances of Lr1 and Lr2. The turn ratios of transformers T1 and T2 have the same value (n=n1=n2). There are eight operation modes in the proposed converter during one switching cycle. The key waveforms of the proposed converter are shown in Fig. 2. The equivalent circuits of each operation mode in one switching cycle are illustrated in Fig. 3.
PEDS2009
(d)
(e)
(f)
Fig. 2 Key waveforms of the proposed converter.
(g)
(a)
(h) Fig. 3 Eight equivalent circuits of the proposed converter during one switching period (a) mode 1 (b) mode 2 (c) mode 3 (d) mode 4 (e) mode 5 (f) mode 6 (g) mode 7 (h) mode 8. (b)
1) Mode 1 [t0≤t>Lr1 and Vin>vC1, the primary current iLr1 increases. For converter module 2, the transformer T2 is in the flux reset mode through Vin, S1, C2 and Lr2. The primary current iLr2 increases. The output inductor current iL2 flows through L2, Co and D22. Thus, the inductor current iL2 decreases linearly. Thus, the ripple currents on inductors L1 and L2 are cancelled each other so that the ripple current on the output capacitor Co is reduced. This mode ends at time t1 when S1 is turned off.
(c)
855
PEDS2009 2) Mode 2 [t1≤t
