Incorporation of a photonic layer at the metallization levels of a. CMOS circuit. JM. Fedeli a, M.Migettea, L.Di Cioccio a, L.El Melhaoui a, R. Orobtchouk b, ...
ThC2 (Invited) 14:30 – 15:00
Incorporation of a photonic layer at the metallization levels of a CMOS circuit. JM. Fedeli a, M.Migette a, L.Di Cioccio a, L.El Melhaoui a, R. Orobtchouk b, C. Seassal c, P. RojoRomeo c, F.Mandorlo c, D.Marris-Morini d, L. Vivien d a
CEA-DRT/LETI, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France INSA/LPM , Bât. Blaise Pascal, 7 avenue Jean Capelle 69621 Villeurbanne, France c LEOM, UMR CNRS 5512, Ecole Centrale de Lyon, Ecully, France d IEF, CNRS UMR 8622, Bât. 220, Université Paris-Sud XI, F-91405 Orsay, France
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ABSTRACT The integration of a photonic layer on a CMOS circuit can be done either by wafer bonding of an SOI photonic circuit or by low temperature fabrication of a photonic layer at the metallization levels.
INTRODUCTION Silicon photonics have generated an increasing interest in the recent year, mainly for optical telecommunications or for optical interconnects in microelectronic circuits. The rationale of silicon photonics is the reduction of the cost of photonic systems through the integration of photonic components and an IC on a common chip, or in the longer term, the enhancement of IC performance with the introduction of optics inside a high performance chip. To achieve such a high level of photonic function integration, the light has to be strongly confined in submicron waveguides with a large (Dn~2) refractive index material between the core and the cladding. In order to build a Photonic Integrated Circuit on CMOS (PICMOS), different incorporation schemes of a photonic layer can be proposed. The first followed by some companies [1] is a combined front-end process which mixes electronics and photonics process steps which is an interesting potentiality for integrated circuits. However, a monolithic integration of dissimilar functions leads to a complex fabrication technology where process steps for one type of component can affect the other and a new SOI electronics library has to be developed. Considering the size of the design, the photonics components could also consume too much silicon real estate and this could ultimately affect the overall cost. Introducing a photonic layer at the last metallization levels allows the use of any silicon technology with the same integration density. The drawback is the temperature limitation of 400°C at Back End of the Line (BEOL) and so hot processes as Ge epitaxy or silicon annealing are not longer allowed. Hot processes can be introduced indirectly by 3D integration; it relies on wafer bonding where a fully or partially processed photonic wafer is mounted on an almost finished CMOS wafer. The low temperature approach is to fabricate the optical layer with only back end technology at the metallization levels. As III-V technology produced efficient components such as lasers and modulators, we consider here the potential of mixing these devices with the advantages of silicon technology.
SOI PHOTONICS AND CMOS WAFER BONDING Using the wafer bonding technique, one can introduce a photonic layer at some level in the processing steps of CMOS. Since the first metal layers are too densely packed and thin, introduction at the upper metal layers must be considered. For example, after the fabrication of metal 4 in the MOS process, the planarized surface has been coated with a deposited oxide. On another substrate, a photonic part is fabricated with silicon waveguides and electro-optical components. On SOITEC optical SOI substrate, we have processed a silicon rib network with cavities filled with Ge. The height and width of the rib waveguides were 380 nm and 1µm, respectively and the etching depth was 70 nm , giving propagation loss lower than 0.4 dB/cm. Experimental demonstration of an optical division equivalent to optical distribution from one input to 1024 output points [2] was achieved with 0.7 dB excess loss per division. For photodetection, the guided light is directly coupled into the integrated Ge photodetectors. After rib fabrication, a cavity was etched in the waveguide with an oxide mask. Germanium was epitaxially grown in the cavity. The light is totally absorbed in a 5 µm long photodetector and so the capacitance is in the 10 fF range and PIN dark current is in the order of 5nA. Before etching openings in the oxide for electrical contact to the germanium photodetector, the optical wafer was carefully polished and bonded to a CMOS wafer before substrate removal (figure 1). In a second experiment, an SOI wafer perforated by a triangular photonic crystal (PC) lattice of circular holes was used. The samples were fabricated using 193 nm deep-UV lithography for both the waveguides and the PC [3]. The waveguides and the PC round areas were cladded with thick SiO2 and carefully polished before bonding. On figure 2, a view after Si substrate removal shows the PC area and the input and output waveguides. After cladding with oxide and planarisation of the optical wafer with CMP, perfect cleaning of both wafers facilitates their molecular bonding at room temperature. However, one of the flaws with this approach lies in the alignment between the electrical and the photonic parts which today can be as much 1-4244-0096-1/06/$20.00 ©2006 IEEE
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as ±2µm. Therefore, the design rules for the subsequent metal layers have to take this alignment margin into account. After bonding, grinding and chemical etching of the backside of the Si optical wafer a flat surface of thermal oxide remains on the top of this PICMOS circuit. Some subsequent process steps are needed to electrically connect the electrical and photonic parts which involve etching through the top layer to contact the electrical circuit below. This technique is often called 3D heterogeneous integration because the CMOS part is separated from the photonic part without any silicon surface waste at the transistor level. With this approach, any microelectronics technologies can be used for the electrical parts and III-V components can be embedded in the photonic layer.
Figure 1: Rib waveguides with splitters, corner mirrors, rectangular cavities filled with germanium on a CMOS at level M4
Figure 2: A Super prism with silicon photonic crystals and stripe waveguides on a CMOS at level M4
BEOL HETEROGENEOUS INTEGRATION As long as temperature is constrained so that it must not exceed 400°C, a photonic layer can be defined above the transistors and the dielectric/metallic levels. The obvious way to introduce such a photonic layer is to treat it as an additional metallic layer on top of most of the layers that have been used for the electrical interconnect.. For the active parts, such as the introduction of copper for electrical interconnect, new materials like low temperature III-V compounds can be introduced on the wafers in a dedicated part of the CMOS clean room. After a CMP planarisation operation, MQW layers on InP die are mounted on top of the waveguides. The InP substrate of these dies is then removed by chemical etching and further processing steps are performed which lead to sources and detectors connected to the metallic interconnects of the integrated circuit. Increasing the refractive index contrast between the cladding and the guiding medium leads to more compact devices. So hydrogenated amorphous silicon (a:Si-H) deposited by PECVD is a promising candidate. Silicon oxide and amorphous silicon films were deposited by a capacitively coupled plasma reactor, with a RF excitation frequency (13.56 MHz) at temperatures lower than 400°C. The power can be tuned from 30 to 1200W and the operating pressure can be varied from 0.2mtorr to few torr. TEOS was used as precursor for oxide deposition and silane/H2 mixture for the amorphous silicon. As with monocrystalline silicon on SOI, the high index difference allows the simultaneous use of refractive compact components (waveguides 0.2 x 0.5mm, loss less bends with radius of the order of 5mm and MMI 1 to 2 less than 6mm²) and photonic crystal components for wavelength functionality. By optimising the H2/Silane ratio in the deposition chamber, silicon films with losses as low as 0.2dB/cm @1.55µm after 350°C annealing were deposited on silicon wafers covered with 1µm TEOS. DUV 248nm lithography without hard mask and HBr silicon etching were used to define the waveguide and basic passive functions for optical links. A 1µm thick SiO2 TEOS oxide was deposited to provide an upper cladding. Measurements were performed at a spectral range between 1.25 to 1.65 µm. Results are compared to previous SOI waveguides data. The propagation losses decrease when the width of the waveguide increases and the losses are comparable to that of an SOI waveguide cladded with SiO2 (5 dB/cm at the wavelengths of 1300 and 1550 nm). Experimental results of the basic building blocks obtain on the amorphous silicon are in a good agreement with those of the SOI technology [4]. For the integration of InP components coupled to passive optical functions on top of a CMOS, our approach is to process the InP-based components in the same way as the CMOS transistors in order to reduce the cost of the introduction of III-V components. As the InP-based components occupy a very small surface on a large CMOS circuit, InP die to CMOS wafer bonding was studied. It consists of dicing an InP wafer with all the heteroepitaxial layers, bonding the die to the required places, removing the back of the InP die in order to only leave the active thin films attached to the CMOS wafer, thus enabling processing of InP components on a dedicated 200 or 300 mm fabrication line. To mount the die, molecular bonding was selected because good bonding quality can be achieved without any additional adhesive materials. In fact, the presence of the bonding material could inhibit efficient optical coupling.
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Furthermore, molecular bonding satisfies the requirements better in term of thermal conductivity and dissipation, transparency at the device working wavelengths and mechanical resistance. The dies were obtained by mechanical dicing of 360 µm thick InP substrate containing an epitaxial heterostructure and a thin silicon dioxide layer (figure 3). InP substrate and the sacrificial InGaAs layer can be chemically and selectively back-etched. So it can be considered as a localized epitaxy of InP heterostructure on CMOS via a SiO2 layer. After decontamination of the back side of the wafers, source processing steps were achieved in 200mm microelectronics clean room. DUV248nm lithography with SiO2 hard mask and ICP etching on AMAT CENTURA5200C defined the laser cavity (DBR or µdisk). Before metallization, the patterns were covered by thick SiO2 and the wafers were planarized by CMP (figure 4).
Figure 3: Source and PD InP dies bonded on an optical layer on a SOI waveguide substrate from IMEC
Figure 4: InP source µdisks after CMP
The coupling of such µdisks to silicon waveguides has been described in a previous paper [5]. The active heterostructure with MQW were designed to emit at 1.5 mm and have been grown by molecular beam epitaxy (MBE) on a 2 inch InP wafer. The final silica thickness between the passive silicon waveguides and the active layer is a key parameter, because it controls the coupling between the laser and waveguide’s modes. In this instance it was about 300 nm, which provided a good coupling efficiency and, at the same time, allowed the lasing of the device. When 5 mm microdisk lasers are coupled to 300 nm waveguides, the quality factor (Qt) drops from 14000 (no waveguide) to 10000. This implies a coupling efficiency > 40%. Their average threshold power is about 2.2 mW. When these lasers are coupled to 600 nm waveguides, Qt drops to 900, implying a coupling efficiency > 55%. The next key step was achieved with the report on electrically pumped lasing in a microdisk cavity in an InP-based membrane bonded on top of a silicon wafer [6]. The top metal contact was placed in the centre of the disk, whereas the bottom contact was made by means of a thin lateral contacting layer. In order to avoid large optical absorption in the p-type contact layers, a tunnel junction was used in combination with two n-type contacts. Lasing was observed in a pulsed regime with a current threshold of about 1.5mA, for microdisks with a diameter of 8mm.
AKNOWLEDGMENT This work is supported by the European community projects FP6-2002-IST-1-002131-PICMOS and FP6-RII3-CT2004-50623 MNTEurope and by the French RMNT programs "CAURICO".
REFERENCES nd
[1] G. Nunn “ CMOS Photonics” GFP 2005 2 International Conference on GroupIV Photonics [2] D. Marris, L. Vivien, D. Pascal, M. Rouvière, E. Cassan, A. Lupu, S. Laval, “Ultra low loss 1 to 1024 on-chip light distribution at 1.31 µm using silicon-on-insulator optical microwaveguides” Applied Physics Letters [3] A. Lupu and al “Experimental demonstration of the superprim effect in the SOI photonic technology” Optics 5690 Vol 12 n°23 15 November 2004 [4] R. Orobtchouk, S.Jeannot, T. Benyattou, J. M. Fedeli, P.Mur "Ultracompact optical link made in amorphous silicon waveguide", proceeding of Photonics Europe 2006 paper 6183-04 [5] H.Hattori et al., “Heterogeneous Integration of Microdisk Lasers on Silicon Strip Waveguides for Optical Interconnects”, to appear in Photonics Technology Letters [6] J. Van Campenhout et al. “An electrically driven membrane microdisk laser for the integration of photonic and electronic ICs” postdeadline paper, LEOS annual meeting, Sydney, 2005
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