Increasing Fault Simulation Performance Using Pre-synthesis Behavioral Model .... fault id equal to this fault. 2.3 Fault simulation ..... combinational circuit, has been tested for eight, ten, and ... circuit has been tested for sixteen, twenty-four, and.
Increasing Fault Simulation Performance Using Pre-synthesis Behavioral Model Zainalabedin Navabi, Mina Zolfy, Meisam Lavasani, Shahrzad Mirkhani Electrical and Computer Engineering Department Faculty of Engineering – Campus #2 – University of Tehran,14399, Tehran IRAN
Abstract: -In this paper, a fault simulation method that utilizes behavioral pre-synthesis and gate level post-synthesis components models will be presented. In this method, an injected stuck at fault in a module will propagate through gates until it reaches the boundary of the module. Propagation of the fault in modules other than the one that it is initiated in will be done in behavioral models. This method is implemented in VHDL by implementing gate level and behavioral level fault propagation in VHDL. Using existing benchmarks, results show fault simulation speed improvement of a factor of 4 over gate-level fault simulation. Key words: -Fault Simulation, VHDL, Behavioral Model, Hierarchical Fault Simulation.
1 Introduction As the complexity of digital components in integrated circuits increases, testing these components as an important part of the design becomes more difficult. Fault simulation is an essential part of most test methods. Since fault model for testing digital circuits is at the gatelevel, all of the existing algorithms use only this level of abstraction to simulate for faults. All the existing fault simulation methods, i.e., concurrent [1, 3], deductive [1, 4], differential [1, 5] and parallel [1, 6] fault simulation methods, are at the gate level in spite of design strategy that is now at the RT level. An important advantage of simulating at the behavioral over gate-level simulation is the simulation performance. In this paper, we discuss our fault simulation method that accelerates the simulation process by switching between gate-level and higher-level abstraction models. Using this method, we can do some parts of fault simulation at behavioral level without losing any detail at the gate-level abstraction An important characteristic of this method is that the more modular a design is, the more efficient fault simulation will be. As a result of increasing the size and complexity of designs, they need to be more and more modular. Modular design is a common technique used in large designs to manage their complexity. This modularity is useful in the implementation of our fault simulation method. Part of this modular design strategy is the use of synthesis tools and availability of behavioral and gate-level pre- and post-synthesis descriptions of modules. An integral part of our implementation is the use of behavioral and gate-level descriptions of modules utilizing modern RT level design trends.
We have implemented this fault simulation methodology in VHDL [2], because our method needs to work with both behavioral and gate level descriptions, and VHDL offers such a mixed level implementation environment. Also the high level capabilities and concurrent programming in VHDL proved useful in this implementation. For the gate level fault simulation we have used a fault simulation method that is based on concurrent fault simulation. In the behavioral parts of a design faults propagation used the same format used in the gate-level parts. In the next section, we will discuss our gate-level fault simulation environment for both combinational and sequential circuits. In the Section 3, we will describe our mixed-level fault simulation model. Section 4 will discuss mixed-level fault simulation process that will determine the sequence of events propagating the faults. Benchmarks and comparisons will be discussed in Section 5, and Section 6 presents conclusions.
2 Fault simulation model As a basic component of the mixed-level fault simulation, we have developed a gate-level fault simulation tool integrated in VHDL programming environment. This tool is based on the concurrent fault simulation algorithm and can be used in both sequential and combinational circuits. We refer to this gate level fault simulation method as Sequentially Propagated Concurrent Fault Simulation (SPC-FS) [14]. In the SPC-FS method that we are presenting, faulty values are received from gate inputs and accumulated in gate models. When a VHDL gate model receives all
faulty values it starts propagating its faulty values through its outputs. This Propagation occurs in zero real time, but it may take many simulation cycles (delta times). This time expansion within gates is determined by the number of faults received at input(s) of a gate. Gates not in the path of any of circuit faults will not be expanded in time, and therefore require only normal good value simulation time. Faults masked at one point in the circuit by a gate will not cause time expansion in the parts of the circuit driven by such gates.
2.1
Queue contents and organization
In the SPC-FS method we depend on individual gate models that can collect all faulty values that reach their inputs through input queues. Gate models process their faulty input values and generate output values. Input values are received in different time units and outputs are generated after all inputs are collected. Generated outputs are also propagated with different faulty values positioned in different time units. The above process uses a circuit line to communicate multiple faulty values to a gate. This time multiplexing of faulty values is shown in Fig. 1. b1-sa1
a=1 b1
b=0
b-sa1
b2
b2-sa1
c=1 b-sa1
b-sa1
b-sa1
b2-sa1
b-sa1
t1
t2
t3
b1-sa1
t4
b2-sa1
t5
time
t1 < t2 < t3 < t4 < t5
Figure 1: A representation for time multiplexing
In this figure there are several stuck at faults that eventually reach the output of the circuit by applying the input values abc=101 as a test vector. As shown, faults that reach the OR gate, reach it through fault queues at each of the gate inputs. Values in an input queue are distanced in time, and reach the destination gate at different time intervals. The OR gate in this figure, receives stuck-at faults at times t1 and t2 and starts performing OR logic operation on all faults received. Resulting faults will propagate through the output queue at times t3, t4 and t5. In the delta time dimension, a gate model receives all fault values from its input queues. The length of an input queue varies and depends on the number of faults reaching a circuit line. This requires fault queues to contain ‘begin’ and ‘end’ markers. We use good line values in place of the ‘begin’ marker. Queues in Fig. 1 represent such markers as shaded areas on the two sides of a queue.
Because of reconvergent fanouts, a fault may appear on more than one input queue. This necessitates a gate to wait for all input faults before propagating resulting faults to its output. Therefore we need an ‘end’ marker at the end of each queue. By seeing the ‘end’ marker of all input queues, a gate model will be able to start the output calculation process.
2.2 Data structure and fault simulation model for combinational circuits As we mentioned earlier implementation of SPC fault simulation is done in the VHDL simulation environment by developing fault simulation primitive gate models. These gate models use TaggedBit record type shown in Fig. 2 for the type of signals representing circuit interconnection lines. TYPE rit IS (‘x’, ‘0’, ‘1’); TYPE TaggedBit IS RECORD Value: rit; LayerTag: integer; END RECORD; Figure 2: Type declaration for lines in SPC-FS
Records in an input queue reaching gate inputs are of type shown in Fig. 2. The value field contains good value and faulty values reaching input. The Tag filed represents fault id corresponding to a faulty value or queue ‘begin’ or ‘end’ indicator. In the implementation of this fault simulation tool we have considered the 0 fault number (Tag) for begin marker (good value record) and we have used –1 fault number (Tag) for end marker. Good value of a line is repeated in the value field of both ‘begin’ and ‘end’ queue records. Within a gate model, a VHDL process statement scans gate inputs for ‘begin’ records. When beginning of a fault queue is detected, input records that follow, i.e., fault id’s and their corresponding faulty values, are read at delta time intervals and inserted in separate linked lists for every gate input. In the transmission phase, a gate output queue that is sent on a gate output line is filled with the following data in the order shown: 1. Begin marker that contains good value (‘begin’ record) 2. All fault id’s and faulty values propagating through the gates (fault records) 3. Fault id and faulty values that are injected on gate inputs and are its own faults 4. End marker that indicates the end of received fault record stream (end record) Item 2 of the above list is generated at the time of transmission of such output records. In this phase, all input link lists are processed to obtain a list of faults that will appear on the output of a gate. For this processing, input fault lists are searched and compared for finding faults that reach a gate through several inputs. The output faulty value of a fault is calculated by application
of gate logic function on the faulty values of the search results. However, for every input list in which the fault id is not found, the good value is used instead. A record with the faulty value and the corresponding fault id is placed on the output only if the faulty value differs from the output good value. … 1 … B
1 E
… …
0 7
1 E
0 7
… …
1 E
… …
0 9
0 3
1 B
0 E
1 9
… …
1 5
0 B
0 5
1 B
1 E
0 7
… …
0 5
0 E
1 5
… …
… 0 … B
1 B
(a)
(b)
Figure 3: Fault propagation
For example, fault 7 in Fig. 3-a that appears on both inputs of the AND gate will be placed on the gate output with 0 value (0 AND 0). In the same circuit fault 5 is transmitted through the output with value 0 (0 AND 1), because 1 is the good value of the upper input of the AND gate. In Fig. 3-b fault 9 does not appear on the output since its output according to faulty inputs (0 AND 1) is the same as the correct value of the gate output. a=1
b1-sa1 (11)
b1
b=0
b-sa1 (10)
b2 b2-sa1 (12)
c=1 Delta time 0 1 2 3 4 5 6 7 8 9 10 11 12 13
(a)
a
b
c
b1
b2
im1
im2
out
x ,-∞ ∞ 1,0 1,-1 … … … … … … ... … … … …
x ,-∞ ∞ 0,0 0,-1 … … … … … … … … … … …
x ,-∞ ∞ 1,0 1,-1 … … … … … … … … … … …
x ,-∞ ∞ … 0,0 1,10 0,-1 … … … … … … … … …
x ,-∞ ∞ … 0,0 1,10 0,-1 … … … … … … … … …
x ,-∞ ∞ … … … … 0,0 1,10 1,11 0,-1 … … … … …
x ,-∞ ∞ … … … … 0,0 1,10 1,12 0,-1 … … … … …
x ,-∞ ∞ … … … … … … … … 0,0 1,10 1,11 1,12 0,-1
(b) Figure 4: Creation and propagation of fault queues
Figure 4 shows the result of a fault simulation process for the circuit of Figure 1. As shown in this figure, list of events that propagate through each line in the circuit can illustrate the fault queue corresponding to that line. Three faults and their ids in this figure have been shown and their effects in the part of the circuit that is driven by faulty lines can be illustrated by the list of events. For example, fault b-sa1 affects the circuit output because there is a record in the output line list of events with a fault id equal to this fault.
2.3 Fault simulation model for sequential circuits The fault queue model, presented in previous sections, will be easily adapted for sequential circuits. This can be
done by altering the flip-flop components to fault simulation models. Also, there are a few problems that should be solved in circuits that have feedback paths. In addition to a fault simulation model for flip-flop components, we need some changes in our combinational primitive gates in order to support sequential fault simulation. In this section, first we will describe the fault simulation model of a simple D flip-flop and then we will describe the considerations we should have in combinational components. 2.3.1 Basic flip-flop fault simulation model It is obvious that at each clock event, every flip-flop must put its input fault queue on its output. Because each fault that has an effect in flip-flop input, will have an effect on its output at the next clock. In a D flip flop component input queue will propagate to output immediately after clock event. Therefore, fault effects propagate through this flip-flop from previous clock to current clock event. As the propagation of fault queues occurs in zero real time (but several delta times), a sequential circuit can operate with its original timing during the fault simulation. Therefore, there is no need to change the clock timing of a circuit. For initializing the simulation in the first clock we must send an empty queue (good value and end of queue) through the flip-flop output. For instance, in Fig. 5, G1 will never propagate its output queue until DFF sends a fault queue to its output, even if there is no fault queue on its D input. DFF
G1
B=1 C=0
G2
Q
D
G3
clk
Figure 5 – A sequential circuit with a feedback path
2.3.2 Altering combinational primitive gates Because of feedback in sequential circuits it is possible for a gate to receive its own fault. Therefore, it becomes necessary to use gate models that can handle this situation. As shown in Fig. 5, Q stuck-at-1 (Q-sa1) fault is propagating through G1 and G2 gates and after one clock cycle, this fault will be on DFF output and then G3 output, that is one of the G1’s inputs. In this case, it is illegal to pass Q-sa1 fault to G1’s output, because stuckat-x faults cannot be activated on a line with ‘x’ value. The primitive gate models for sequential circuits are changed to detect such faults.
3 Adding behavioral part to fault simulation model In this mixed-level method, the concepts of fault queues and fault records are used in a similar way to previously
described gate-level fault simulation method in Section 2. The difference is that in the mixed method, fault queues are propagated through behavioral models of modules as much as it is possible to gain performance. For any module, we will instantiate both behavioral and gate-level descriptions of that module. A wrapper will distribute tasks to behavioral and gate-level descriptions. Therefore, both descriptions will participate in the process of fault simulation, simultaneously. A typical circuit that has three 8-bit inputs and a single bit output is shown in Fig 6. This circuit consists of two modules, an adder and a comparator. As shown in this figure, both behavioral and gate level models of the comparator module are instantiated and work together. IF in1 > in2 THEN Out
