Interleaved Cuk Converter with improved Transient ...

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The Journal of Engineering

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Interleaved Cuk Converter with improved Transient Performance and Reduced Current Ripple Joseph K.D.1* , Asha Elizabeth Daniel2 , A. Unnikrishnan3 1

Department of Electrical Engg, Government Engg. College, Thrissur, Kerala - 680 009, India, School of Engineering, Cochin University of Science and Technology, Cochin, Kerala - 682 022, India, 3 Outstanding Scientist (Rtd), Naval Physical & Oceanographic Laboratory , Cochin, Kerala 682021, India , * [email protected] 2

Abstract: Boost DC-DC converters are widely used in non-conventional power conversions namely in solar and wind power generation systems. It is also used in switched mode power supplies. Since there is no filter inductor on output side, output current of boost converter is pulsed and it is not desirable. The quality of power required is very high when DC-DC converters are employed for transferring the requisite amount of power. In this context, the conventional cuk converter (CCC) having continuous current at both input and output sides is taken as the candidate for performance analysis. Accordingly an interleaved cuk converter (ICC) is proposed and designed to reduce the input current ripple and also to improve transient performances. Both CCC and the proposed ICC are simulated and validated experimentally. The proposed converter is having better efficiency attributable to cancellation of source current ripple, reduction of ripple content in both output voltage & current and improvement of transient performance.

1. Introduction The quality of power has become very important issue in power system operations when switched mode DC-DC converters are employed. Accordingly research investigations during last two decades are largely focussed in this area to improve power quality by the reduction of the ripple content of currents, enhancement of transient performance besides the improvement in voltage characteristics and efficiency. The ripple on input current of a power supply is not at all tolerable since it injects harmonics to parent source and is harmful to other connected equipments. Cuk converter is taken as the potential candidate for investigations here because cuk design is having better characteristics on ripple content of currents compared to all basic DC-DC converters. Reduction of current ripple on input side in boost converters is achieved by interleaving method [2] and reduction of switching loss by zero voltage switching [3] are already suggested. High gain of the converter output is obtained at a particular duty ratio [4], by diode-capacitor multiplier [5],by coupled inductor [6] and by variable inductor [7] methods. Boost converter with series connected transformers are also proposed to reduce input current ripple suitable for renewable power systems [8]-[9]. But the output current of these converters is pulsed. Reduction of switching losses of buck converter is using zero voltage switching PWM strategy is described [10] - [11]. Improvement of output current shape of a buck converter using four phase parallel structure [12] and parallel 1 IET Review Copy Only


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converter [13] are proposed. But here the input current is pulsed. Alternatively a soft switched interleaved flyback converter by current mode control [14] applied to remote power applications, buck-boost converter with built in interleaved boost operation [15], non-inverting converter for fuel cell applications [16] by eliminating a switch and diode, with interphase transformers [17] are described. But here both input and output currents are pulsed. Issues in reduction of ripple currents due to different magnitudes on parallel inductors of interleaved circuit [18], minimum value of ripple content on output voltage [19] of sepic converter with minimum values of inductance and capacitance are discussed. Simulation of high efficient interleaved cuk converter with duty ratio of switches less than 50% [20], boost converter with zero voltage switching [21], voltage multiplier [22], wide conversion ratio [24], interleaved sepic converter [23] with low switching losses are presented. Practical aspects like parasitic values are not considered in these papers and experimental verifications are required to substantiate above results. Industry demands high efficient power converters with low ripple and better transient performance. But all basic converters are having pulsed currents either on input or on output. Cuk converter with continuous input and output current is taken as the potential candidate for analysis. Even though the current is continuous but it still has ripples on input current which are not acceptable. It was found that ripple current cancellation, zero power switching, low-switching stress, high gain converter with high efficiency, low ripple on voltage and current are key research areas in converter analysis. In order to alleviate the above mentioned issues an Interleaved Cuk Converter (ICC) using Phase Shifted Pulse Width Modulation (PSPWM) scheme is proposed. The simulation and experimental validation of ICC demonstrated that enhancement of current ripple on input side, reduction of ripples on both voltage & current on output side, reduction of current stress of switches and superior transient performances, these lead to better efficiency. 2. Conventional Cuk Converter (CCC) - Compensator Design Generally a cuk converter as shown in figure (1) with sufficient value of inductors on both sides avoids pulsed current.

Fig. 1. The circuit diagram of Cuk converter The operation of the cuk converter is based on energy transfer by the capacitor C1 . The capacitor stores energy and transfers to output with constant voltage irrespective of line voltage and load 2 IET Review Copy Only

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current variations. The output equation of the cuk converter is Vo = −Vg (D/(1 − D))

(1)

Where Vo is output voltage, Vg is input voltage and D is duty ratio. This converter can be used for buck and boost operations. The compensator for cuk converter is designed by state space averaging method [26]. The general equation for small signal transfer function of cuk converter is Gp (S) =

vˆ(S) = C ∗ (SI − A)−1 ∗ (A1 − A2 )X ˆ d(S)

(2)

ˆ are small perturbations in the output voltage and duty ratio respectively bound to where vˆ(S), d(S) their steady state values Vo and D. And the state matrices A1 , A2 , C1 &C2 modelled using the state variables i1 , i2 , vc1 &vco and output variables ig &vo referred to figure(1) are given by  r1  − 0 0 0  L1    ro RL 1 1 RL 1  0 −[r2 − rc1 + ]( ) [− ]   RL + ro L2 L2 L2 (RL + ro )   [A1 ] =  1    0  0 0 −   C1   RL 1 0 0 − (RL + ro )Co (RL + ro )Co 1 r1 + rc1 ) 0 − −(  L1 L1  ro RL 1  0 −[r2 + ]( ) 0   RL + ro L2 [A2 ] =  1  0 0  C1   RL 0 0 (RL + ro )Co 

0 1 RL [− ] L2 R L + r o ) 0 −

1 (RL + ro )Co

          

 0 0 0  RL ro RL C1 = C2 =  0 0 ro + RL ro + RL The matrices A and C are obtained from equations (3) and (4)



1

A = A1 ∗ d + A2 ∗ (1 − d)

(3)

C = C1 ∗ d + C2 ∗ (1 − d)

(4)

The transfer function of the plant along with digital modulator after substituting parameter values as per the table (1) in equation (2) is Gm (s)Gp (S) =

87.7S 3 + 8.769 ∗ 109 S 2 − 6.356 ∗ 1013 S + 6.657 ∗ 1017 S 4 + 1.358 ∗ 104 s3 + 1.231 ∗ 109 S 2 + 3.073 ∗ 1012 S + 4.348 ∗ 1016 3 IET Review Copy Only

(5)


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The phase margin of the transfer function is 12.9o at a cross over frequency of 9.93 ∗ 104 rad/s is very low. A lag-lead compensator [1] is designed to improve the phase margin. The compensator transfer function with the signal and parasitic values is Gc (S) = 106 ∗ (

S 2 + 2 ∗ 18706.3S + 18706.32 ) S(S 2 + 2 ∗ 527282S + 5272822 )

(6)

The overall transfer function is T (s) = Gm (S) ∗ Gp (S) ∗ Gc (S)

(7)

Fig. 2. Bode plot of overall transfer function, phase margin = 69.5o The bode plot of the transfer function in shown in figure (2). The phase margin for the overall transfer function is 69.5o at a cross over frequency of 5.4 ∗ 104 rad/s and found that the system is stable in closed loop for input voltage and load current variations. 3. Interleaved Cuk Converter (ICC) The shape of output current can be pulsed in interleaved boost converter[2], but this converter improves current shape on input side. An ICC is developed with improved efficiency and superior transient performance to defeat the demerits of CCC and interleaved boost converter [2]. This proposed converter improves current shape by ripple cancellation technique, provides continuous current on both sides and reduces switching current stress. 3.1.

Interleaved Cuk Converter - Operation

An ICC topology consists of two switches S1 , S2 , two high frequency diodes D1 , D2 , four capacitors C1 , Co1 , C2 , Co2 , four inductors L1a , L1b , L2a , L2b and a load resistor of RL as shown in figure 4 IET Review Copy Only

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(3-a). The operation of the converter is analysed in four modes. The switches are turned ON one at a time for a duration of Ton /2 after a delay of Tof f /2 using PSPWM scheme. The maximum duty ratio of the switch is limited to 50%. Hence the current stress on switch of ICC is reduced to 50% in comparison with all known DC-DC converters.

Fig. 3. circuit diagram of interleaved cuk converter with different modes of operation.(a) basic circuit (b) S1 ON and S2 OFF (c) S1 and S2 OFF (d) S1 OFF and S2 ON 3.1.1. Mode 1 - S1 ON & S2 OFF (to − t1 ): The circuit diagram when switches S1 ON & S2 OFF is shown in the figure (3-b). During this period L1a charges and L2a discharges (figure (4)). The stored energy in L2a transfers to C2 and it charges. Also the capacitor C1 discharges through C1 , S1 , Co1 , L1b , Co2 , L2b and RL , hence transfers stored energy in the capacitor to the load. The load current is assumed constant and flows in negative direction. By assuming linear rise of inductor current, the ripple current is given by equations (8), (9) and (10) ∆IL1a = ((t1 − to )/L1a )(Vg − r1a iL1a )

(8)

∆IL2a = ((t1 − to )/L2a )(Vg − Vc2 − (r2a + rc2)iL2a )

(9)

Assuming L1a = L2a = La , r1a = r2a , iL1a = iL2a then ∆I1 = ∆IL1a − ∆IL2a = (Vc2 + rc2 ∗ iL2a )((t1 − to )/La )

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(10)


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3.1.2. Mode 2 - S1 OFF and S2 OFF (t1 − t2 ): The circuit diagram when both switches S1 & S2 are in OFF condition is shown in figure (3-c). During this period both inductors L1a & L2a are discharging and stored energy transfers to capacitors C1 & C2 respectively. Also C1 starts charging. At the same time inductors L1b & L2b are discharging as shown in figure (4), transfers its energy to load. By assuming linear fall of inductor current, the ripple current is given by equations (11),(12) and (13) ∆IL1a = ((t2 − t1 )/L1a )(Vg − Vc1 − (r1a + rC1 )iL1a )

(11)

∆IL2a = ((t2 − t1 )/L2a )(Vg − Vc2 − (r2a + rC2 )iL2a )

(12)

Assuming L1a = L2a , Vc1 = Vc2 , r1a = r2a , rC1 = rC2 then ∆I2 = ∆IL1a − ∆IL2a = 0

(13)

3.1.3. Mode 3 - S1 OFF & S2 ON (t2 − t3 ): The equivalent circuit when the switches S1 OFF and S2 ON is shown in the figure (3-c). During this period L2a charges and L1a discharges (refer Fig.4). The stored energy in L1a transfers to C1 and it continues to charge. Also the capacitor C2 discharges through C2 ,S2 , Co2 , L2b and RL . Hence transfers stored energy in the capacitor to the load. By assuming linear rise of inductor current, the ripple current is given by equations (14), (15) and (16) ∆IL1a = ((t3 − t2 )/L1a )(Vg − Vc1 − (r1a + rc1 ) ∗ iL1a ) (14) ∆IL2a = ((t3 − t2 )/L2a )(Vg − r2a ∗ iL2a )

(15)

Assuming L1a = L2a = La , r1a = r2a , iL1a = iL2a then ∆I3 = ∆IL1a − ∆IL2a = (−Vc1 − rc1 ∗ iL1a )((t3 − t2 )/La )

(16)

3.1.4. Mode 4 - S1 OFF and S2 OFF (t3 − t4 ): The operation is as same as that of mode 2. ∆I4 = ∆IL1a − ∆IL2a = 0. The waveforms of inductor currents and source current are shown in figure (4) along with PSPWM. In one half cycle when one switch is ON, corresponding inductor is charging and other inductor is discharging, hence current ripple cancellation takes place. The output equation of the converter can be derived as follows. During Mode -1, Capacitor C1 acts as primary means of storing and transferring energy from the input to the output. Under steady state conditions average inductor voltages VLa1 and VLb1 are over a period is zero. Hence VC1 = Vg + Vo1

(17)

Where VC1 and Vo1 are voltage across capacitors C1 and Co1 respectively. The volt-sec balance of switch S1 is given by Vg DTs /2 + (Vg − Vc1 )(1 − D)Ts /2 = 0 (18) Where Ts is switching period. Substituting equation (17) in equation (18), the output voltage equation by Co1 is Vg D Vo1 = − (19) (1 − D) 6 IET Review Copy Only

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Ton and Ton on time of switch S1 . According to polarities of diodes the output current Ts /2 is in the negative direction along with output voltage with respect to input, the converter works in quadrant III. Hence for an ICC both step up & step down process takes place with reference to equation (19). Also ripple cancellation takes place according to equations (10), (13) & (16) for the source current. Since the circuit (refer figure (3)), is parallel so the output, Vo2 = Vo1 . The compensator for ICC is designed by using state space model [26] (refer section-2) as same method as that of CCC. So the compensator transfer function in Z-domain is given by the equation (20). (3.441 ∗ 107 Z 3 + 1.032 ∗ 108 Z 2 + 1.032 ∗ 108 Z + 3.441 ∗ 107 ) (20) Gc (s) = (Z 3 + Z 2 − Z − 1) where D =

3.2.

Phase shifted Pulse Width Modulation (PSPWM)

A modified PWM generation scheme is shown in figure (4) is used to trigger switches rather than using alternate PWM scheme. A part of the output voltage is fedback to the z-domain compensator where the error is processed. DC output is compared with carrier signal and PWM is generated. The ON time and OFF time of PWM are divided to equal halves. First half of ON time is applied to first switch S1 . Second half of ON time applied to second switch S2 after a delay time of TOF F /2. It is continued to switch S1 after a delay of TOF F /2 and so on as shown in figure(4). Since the pulse width is reduced to half by PSPWM and interleaving feature, the current stress on switch is reduced to 50%. This will reduce the temperature rise of the switching devices and lead to reduction of cooling mechanism. 4. Results and Discussions The simulation and experimental validation have been conducted for CCC and ICC with reference to the table (1). The parasitic values of inductors and capacitors are inserted in simulation to get the results equivalent to real time experimental implementation. The output voltage obtained as Vo = −15V corresponding to an input voltage of Vg = 20V . Also the load current obtained as Io = −2A corresponding to a resistance of 7.5 ohm. The error signal is processed in compensator and it produces a DC signal which is compared in comparator with saw tooth carrier signal of the switching time and hence PSPWM is generated [20]. The switching frequency of PSPWM is kept to a nominal value of 25 kHz. The experimental circuit has been implemented using electronic circuit board in closed loop for CCC and proposed ICC. The converters are designed with an input voltage of 20V and output voltage of -15V at -2A. The input voltage is applied from a 30V, 5A, DC Power supply, inductors are prepared by winding coil on E55 ferrite core, and E23 ferrite core. IRF540 MOSFET and MUR420 high frequency diode are used in circuit. A current sensor LA55P is used and it is scaled as 1A = 1V. The output voltage is measured across 7.5 ohm resistive load, scaled down to a ratio of 1:11 and is applied to 8 bit AMS ADC circuit card pins of ALTIUM SPARTAN 3AN XC3S1400AN FPGA digital controller. The ADC output is compared with reference voltage and the error is processed in Z-domain XILINX model of compensator. The PWM pulse for CCC and PSPWM for ICC generated from FPGA controller and which are applied to MOSFETs of converters through a level shifter board. The output voltage, input voltage, output current, input current, line and load transients, PSPWM pulses are measured using TEKTRONIX 100MHz Digital Storage Oscilloscope. 7 IET Review Copy Only


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Fig. 4. Ripple reduction using PSPWM Table 1 CCC and ICC - values for design

Parameter Values

Vg

Vo

L1 , L1a , L2a L2 , L1b , L2b

C1 , C2 , Co Co1 , Co2

RL

fs

20 V

-15 V

0.75 mH

10 uF

7.5 ohm

25 kHz

0.1 mH


22uF

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Both converters are designed with an input voltage of 20V and output of -15V, -2A. The closed loop non ideal simulation is carried out using designed compensator in Z- domain and brief results are shown below. 4.1.

Steady State Characteristics

With the input of 20V and set value of output as -15V, the duty cycle evaluated as D = 0.43 (refer equation (19)). The Simulation and Experimental results of output voltage is shown in table (2). In simulation results, the ripple content of output voltage has reduced from 1.2% to 0.1% for proposed ICC. Also in Experimental results, the ripple content of output voltage has reduced from 7% to 2.7% for proposed ICC. The difference in results of simulation and experiment is due to the difference parasitic values of passive elements. Simulation and experimental results of CCC of input and output current is shown in figure(5). The Table 2 Simulation and experimental results - Output Voltage at switching frequency fs = 25kHz Parameter Input Voltage Vg Output Voltage Vo Simulation Results Output voltage ripple Vo(rip) Experimental Results Output voltage ripple Vo(rip)

CCC 20 V -15V

Proposed ICC 20V -15V

0.18V (1.2% )

0.015 V (0.01% )

1.04V (7% )

400 mV (2.7% )

average value of input current is Ig = 1.9A and that of output current is Io = −2A. The input current has a ripple of 27.3% on simulation as in figure(5-a). Also the experimental results verified it and the ripple content is 27% as in figure(5-b). Simulation and experimental results of ICC of input and output current is shown in figure(6). In figure(6-a) both inductor currents have an average valueIL1a = IL2a = 0.875A. But the source current has an average value of Ig = 1.75A. The inductor current waveforms have ripple of 0.45A which is same as that of CCC ripple. But by modifying it to interleaved, the source current ripple has reduced further from 27% (in CCC) to 7.1% (in proposed ICC). Also in the experimental results the ripple content is 4.4% as in figure(6-c). The actual parasitic resistance values of inductor in experiment is less than the values inserted in simulation hence the ripple content is less in experimental results. The output current has a ripple of 0.1% on simulation as in figure (6-b) . Also in experimental results the ripple value of output current is 4.7% as in figure (6-c). From experimental results it can be concluded that the input current ripple has reduced from 27% (in CCC) to 4.4% (in proposed ICC). 4.2.

Transient Characteristics

Load transient waveforms of CCC and ICC are shown in figure (7). In CCC as shown in (simulation) figure (7-a) the load current (Io ) changed from -1A to -2A at 0.015 second and Vo to settle to -15V in 7mS. Also Io shifted back to -1A at 0.03 second and settling time is 7 mS. The overshoot is 10V. But ICC as shown in (simulation) figure (7-b) settling time is smaller than that CCC for the same change of output current. The overshoot has reduced from 10V to 4V. 9 IET Review Copy Only


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Fig. 8. Efficiency curve for CCC and ICC Table 4 Comparison of CCC and ICC of Experimental results at Vg = 20V, Vo = −15V, Io = −2A, Ig = 1.8A, fs = 25kHz Parameter Source current ripple Ig(rip) Output Voltage ripple Vo(rip) Load transient - settling time Line transient - settling time Overshoot Efficiency

CCC 450 mA (27%) 1.04 V( 7%) 10 mS 40 mS small oscillations 81%

Proposed ICC 100 mA (4.4%) 400mV (2.7%) 3 mS 2 mS No oscillations 87%

reduction of the output voltage ripple to 2.7%. Though the efficiency really matters when ripple reduction takes place, but the efficiency is not sacrificed and kept above 87% in the case of ICC. The settling time and overshoot for line and load transient performances for the ICC are much better than that of CCC. Reduction of switching stress is achieved during the buck operation since duty cycle is below 50% and boost operation is possible when duty cycle is above 50%. The experimental validation of the two circuits conclude that ICC is having significantly better performance both during transient and steady state operations. The better performance has been achieved by reducing settling time, reducing overshoot and ripple content on input and output waveforms and these lead to higher efficiency. 7. Acknowledgment Technical Education Quality Improvement Programme (TEQIP) Phase II, Government Engineering College, Thrissur, Kerala, India support this work by providing fund under Research Seed Money Project scheme. 8. References 8.1.

Websites

[1] ’Type III compensator design for power converters - Power Electronics Technology’, http://powerelectronics.com /images/ Type3CompensatorDesign.pdf, accessed 30 March 2016 13 IET Review Copy Only


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8.2.

Journal articles

[2] Yu Gu, Donglai Zhang:‘Interleaved Boost Converter with Ripple Cancellation’, IEEE Trans. on Power Elect., Aug. 2013,28, (8), pp. 3860-3869. [3] Chien-Ming Wang1, Chang-Hua Lin2, Chien-Min Lu1, Jyun-Che Li1: ’Design and realisation of a zero-voltage transition pulse width modulation interleaved boost power factor correction converter’, IET Power Electron., 2015, 8, (8), pp. 1542-1551 [4] Julio Cesar Rosas-Caro, Fernando Mancilla-David, Jonathan Carlos Mayo-Maldonado,Juan Miguel Gonzalez-Lopez, Hilda Lizeth Torres-Espinosa, Jesus Elias Valdez-Resendiz: ‘A Transformer-less High-Gain Boost Converter With Input Current Ripple Cancellation at a Selectable Duty Cycle’, IEEE Trans. Ind. Electronics, Oct. 2013’, 60, (10), pp. 4492-4499. [5] Luo-wei Zhou, Bin-xin Zhu, Quan-ming Luo, Si Chen: ’Interleaved non-isolated high step-up DC/DC converter based on the diodecapacitor multiplier’, IET Power Electron., 2014, 7, (2), pp. 390-397 [6] Tohid Nouri, Seyed Hossein Hosseini, Ebrahim Babaei, Jaber Ebrahimi: ’Interleaved high step-up DCDC converter based on three-winding high-frequency coupled inductor and voltage multiplier cell’, IET Power Electron., 2015, 8,(2), pp. 175-184 [7] Quan-ming Luo, Huan Yan, Si Chen, Luo-wei Zhou: ’Interleaved high step-up zero-voltageswitching boost converter with variable inductor control’, IET Power Electron., 2014, 7,(12), pp. 3083-3089 [8] Longlong Zhang, Dehong Xu, Guoqiao Shen,Min Chen, Adrain Ioinovici: ’A High Step-Up DC to DC Converter Under Alternating Phase Shift Control for Fuel Cell Power System’, IEEE Trans. Power Electron., Mar. 2015, 30,(3), pp.1694-1703. [9] Kuo-Ching Tseng, Chi-Chih Huang,: ’High Step-Up High-Efficiency Interleaved Converter with Voltage Multiplier Module for Renewable Energy System’, IEEE Trans. Ind. Electron., Mar. 2014, 61, (3), pp.1311-1319. [10] Morteza Esteki, Ehsan Adib, Hosein Farzanehfard, Sayed Abbas Arshadi: ’Auxiliary circuit for zero-voltage-transition interleaved pulse-width modulation buck converter’, IET Power Electron., 2016, 9, (3), pp. 568-575 [11] Fahimeh Marvi, Ehsan Adib, Hosein Farzanehfard: ’Zero voltage switching interleaved coupled inductor synchronous buck converter operating at boundary condition’, IET Power Electron., 2016, 9, (1), pp. 126-131 [12] Morteza Esteki, Behzad Poorali, Ehsan Adib, Hosein Farzanehfard: ’High step-down interleaved buck converter with low voltage stress’, IET Power Electron., 2015, 8, (12), pp. 2352-2360. [13] Parvathyshankar Deivasundari1, Govindarajan Uma2, Christy Vincent2, Krishnamurthy Murali3 :’Non-linear intermittent instabilities and their control in an interleaved DC/DC converter’, IET Power Electron., 2014, 7, (5), pp. 1235-1245


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[14] Anuradha Thangavelu1, Vairakannu Senthilkumar2, Deivasundari Parvathyshankar3 :’Zero voltage switching-pulse width modulation technique-based interleaved flyback converter for remote power solutions’, IET Power Electron., 2016, 9, (7), pp. 1381-1390 [15] Hongfei Wu, Tiantian Mu, Hongjuan Ge, Yan Xing :’Full-Range Soft-Switching-Isolated Buck-Boost Converters With Integrated Interleaved Boost Converter and Phase-Shifted Control’, IEEE Trans. Power Electron., Feb. 2016, 31, (2), pp.987- 999 IEEE Trans. Power Electron., Apr. 2014, 29, (4), pp. 1840 -1849 [16] H.K. Liao1, T.-J. Liang1, L.-S. Yang2, J.F. Chen1:’Non-inverting buckboost converter with interleaved technique for fuel-cell system’, IET Power Electron., 2012, 5, (8), pp. 1379-1388 [17] Ding Wu, Gerardo Calderon-Lopez, Andrew John Forsyth: ’Discontinuous conduction/current mode analysis of dual interleaved buck and boost converters with interphase transformer’,IET Power Electron., 2016, 9, (1), pp. 31- 41 [18] Pablo D. Antoszczuk, Rogelio Garcia Retegui, Nicolas Wassinger, Sebastian Maestri, Marcos Funes, Mario Benedetti: ’Characterization of Steady-State Current Ripple in Interleaved Power Converters Under Inductance Mismatches’, IEEE Trans. Power Electron, April 2014,29,(4),pp.1840-1849 [19] Ebrahim Babaei, Member, Mir Esmaeel Seyed Mahmoodieh: ’Calculation of Output Voltage Ripple and Design Considerations of SEPIC Converter’, IEEE Trans. Ind. Electro, Mar. 2014, 61, (3), pp. 1213-1222. 8.3.

Conference Paper

[20] K.D.Joseph, Asha Elizabeth Daniel, A. Unnikrishnan:’Reduced Ripple Interleaved Cuk Converter with Phase Shifted PWM’, IEEExplore, Kota, Kinabalu, Malaysia, ASCC, May 2015, pp. 1-6 [21] Bor-Ren Lin, Jian-Yo Jhong: ’Implementation of an Interleaved ZVS/ZCS DC/DC Converter’, ”IEEE Proceedings,IEEE Region 10, TENCON 2011, pp.853-857. [22] Ryuga Hosoki,Hirotaka Koizumi: ’High-Step-Up Dc-Dc Converter Using Voltage Multiplier Cell with Ripple Free Input Current’, IECON2013, pp.834-839. [23] Bor-Ren Lin, Po-Li Chen, Jyun-Ji Che: ’Interleaved Sepic Converter with Low Switching Loss’, IEEE Proceedings, IEEE Region 10, TENCON 2010, pp.1817-1822 [24] R. Gules, L. L. Pfitscher, L. C. Franco: ’An interleaved boost DC - DC converter with large conversion ratio’, IEEE Proc.ISIE2003, pp. 411-416. 8.4.

Book, book chapter and manual

[25] Ned Mohan, Tore M Undeland, William P Robbins: ’Switching dc Power Supplies’, in Singapore Media Enhanced (Ed.): ’Power Electronics : Converters,Applications and Design’ (John Wiley & sons Inc. , 2003, 3rd edn), pp.331-336



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[26] Robert W.Erickson, Dragan Maksimovic: ’Dynamics and Control - AC Equivalent Circuit Modelling’, in USA (Ed.): ’Fundamentals of Power Electronics’ (Kluwer Academic, 2001, 2nd edn). pp.213-225
