2013 International Conference on Connected Vehicles and Expo (ICCVE)
Interleaved High-Gain Boost Converter With Low Input-Current Ripple For Fuel Cell Electric Vehicle Applications Jesus E. Valdez-Resendiz, Abraham Claudio-Sanchez, Gerardo V. Guerrero-Ramirez, Carlos Aguilar-Castillo, Alejandro Tapia-Hernandez, Josefa Gordillo-Estrada Departamento de Ingeniería Electrónica CENIDET Morelos, México
[email protected]
converter is not used when the required boost ratio is higher than four.
Abstract—This work proposes a boost dc-dc converter topology that offers excellent characteristics for fuel cell power conditioning. The proposed converter features high voltage gain without utilizing extreme values of duty cycle or transformers, input current ripple reduction by interleaved inductors, low count of components and reduced weight and size.
Several high voltage gain circuits have been proposed in the literature [4]–[7], the main disadvantages of this converters are; the high number of components, the complexity and the large input current ripple. The expected low input current ripple in a fuel cell stack power processing circuit is a main challenge in fuel cell power conditioning topic. Any ripple on the converter input current caused by switching operation, must be reduced as much as possible in order to improve the efficiency of the fuel cell stack since, due to the limited response speed of the fuel flow control system, periodical load oscillations cannot be followed, resulting in a mismatch between the real and the optimal fuel flow, in these conditions a fraction of the fuel crosses the cell stack without producing energy, lowering the stack efficiency.[8], [9]
These characteristics make the converter ideal for fuel cell electric vehicles, where a high dc bus for traction system and reduced input current ripple for increasing the fuel economy are required. Simulation-based results, theoretical analysis and experimental validation are presented in this work. Keywords—dc/dc converters, fuel cell vehicles, power conversion, current ripple reduction.
I.
INTRODUCTION.
In last years, fuel cell electric vehicles have been widely investigated. Features such as: high energy density, high efficiency, low temperature operation and zero emissions make fuel cell a good choice for electric vehicle power systems[1], [2].
Another problem of large input current ripple is the electromagnetic interference (EMI), this is a serious issue that can cause communication faults or noises in the commutation signals, being necessary the use of bulky filters.
In vehicular applications, fuel cell stack power conditioners are highly recommended due to: (i) the fuel cell stack have a wide variation output voltage caused by the power demand variation, (ii) the typical voltage per cell in a fuel cell stack, is around 0.6 V, thus it is hard to reach the DC bus voltage for a high voltage motor (200V-400V), (iii) in hybrid power systems (fuel cell, battery and/or ultracapacitor) the active control of the power flow is necessary.
The standard solution is use big inductances that lead to a small current ripple, but inductors with big inductances are bulky, large in size, and expensive. Furthermore, a large inductor also slows down transient response of the converter and it is well know that large inductances have a big leakage resistance, which, as noted above, limits the boost ratio of the converter [3], [4], [10], [11].
Typically a step up converter is used as a fuel cell stack conditioner; it plays a key role in the applications where a low voltage fuel cell based power generator is committed to supply high voltage DC bus.
This paper proposes a DC–DC interleaved PWM converter topology based on the MBC [3], and the classic boost converter. The main advantages of the proposed topology are: (i) high voltage gain without extreme duty cycle, (ii) low input current ripple, (iii) the reduction of input current ripple makes the power rating of the converter increases, (iv) voltage balancing in output capacitors. The
In theory, a traditional boost converter can achieve an infinite voltage gain when duty cycle gets close to 100%, but in real life, the boost ratio is limited by the leakage resistance of the inductor-charging loop [3], [4] Because of this, a boost
978-1-4799-2491-2/13/$31.00 ©2013 IEEE
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DOI 10.1109/ICCVE.2013.171
converter’s principle is proven by simulation and validated by experimental setup. II.
PROPOSED TOPOLOGY
In Fig.1 the proposed topology is presented, it can see that the components are; two transistors, four diodes, two inductors and three capacitors. One can appreciate that the circuit consist of a multilevel boost converter (MBC)[3], interleaved with a traditional boost converter. That arrangement provides two important features for fuel cell conditioners, like: (i) input current ripple reduction, due to the interleaved inductors, (ii) high output voltage gain, due to the diode-capacitor voltage multiplier of the MBC.
(a)
(b) Fig. 2. Equivalent circuit diagrams of the proposed converter.
Fig. 1. Circuit schematic of the proposed topology.
The converter operation will be described assuming the small ripple approximation and the continuous conduction mode. The converter has two equivalent circuits, resulting from the switching of S1 and S2, these circuits are shown in Fig. 2. During the switches-on state, the inductors L1 and L2 are connected to Vi, Fig. 2(a). If the voltage across C1 is smaller than the voltage across C3, then C3 transfer energy to C1 through D2. D3 and D4 are reverse biased blocking the voltage across C3; similarly D1 is reverse biased blocking the voltage across C2. The output voltage is giving by the sum of C2 and C3 voltages.
Fig. 3. Current waveforms through the input inductors, and switching sequence.
While S1 is conducting, the current through L1 rises with a slope of Vi/L1 on the other hand, when S1 is open L1 discharges at a rate of (Vi-VC3)/L1. Similarly while S2 is conducting, the current through L2 rises with a slope of Vi/L2 and when S2 is open L2 discharges at a rate of (ViVC3)/L2. Currents depicted in Fig.3 are shown for a converter that work at a duty cycle of D=0.5.
When the switches S1 and S2 turn off, the currents through the inductors L1 and L2 force the diodes D3 and D4 to be closed, then C3 is charged with the sum of both currents, Fig. 2(b). D2 is reverse biased blocking the voltage across C1. If the voltage across C2 is smaller than the voltage across C1, then C1 transfer energy to C2 through D1. Again, the output voltage is giving by the sum of C2 and C3 voltages.
III.
ANALISYS AND COMPONENTS SELECTION.
One of the advantages of the proposed interleaving converter topology is the high voltage gain compared with the traditional interleaved boost converter, as it can be seen from Fig. 1 the output voltage is giving by the sum of the VC2 and VC3, which makes that extreme duty cycle don’t be required.
Fig. 3 shows, typical waveforms for the currents through L1 and L2 and the switching sequence for S1 and S2. For input current ripple reduction, both transistors switch with the same frequency and duty cycle but shifted 180°.
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A. Voltage gain. The converter will be analyzed during steady state conditions therefore the small ripple approximation will be assumed (capital letters indicate steady state values). Considering the duty cycle d as the time when the switch S1 is closed over the total switching period Ts, the average voltages across the input inductors are given as: ܮଵ
݀ܫଵ ൌ ݀ሺݒ ሻ ሺͳ െ ݀ሻ ή ሺݒ െ ݒଷ ሻ ݀ݐ (1)
ܮଶ
݀ܫଶ ൌ ݀ሺݒ ሻ ሺͳ െ ݀ሻ ή ሺݒ െ ݒଷ ሻ ݀ݐ
Fig. 4. Voltage gain vs. duty cycle.
(2) To calculate the input current ripple, a duty cycle D=0.5 will be used, then D= (1-D), and expression (6) can be modified as follows: ܸ ܸ ሺͳ െ ܦሻ ο݅ଶ ൌ ሺͳ െ ܦሻܶ௦ ൌ ή ܮଶ ܮଶ ݂௦ (7) The input current ripple, denoted by ¨ii, is the difference between the current ripple of the inductors defined by equations (5) and (7), thus
By using expressions (1) or (2) the voltage across C3 may be expressed as: ܸଷ ൌ
ͳ ήܸ ͳെ ܦ
(3) It is important to note that C3 transfer energy to C1 during the time when the switch S1 is on, see Fig. 2(a) and then they get practically the same average voltage [4]. Later during the time when the switch S1 is off C1 transfer energy to C2 and then they get practically the same average voltage, thereby, voltage in C2 is practically the same that the voltage in C3.
ο݅ ൌ
ܸ ܦሺͳ െ ܦሻ ቆ െ ቇ ݂௦ ܮଵ ܮଶ
(8) From (8) it’s clear that, if we want zero input current ripple (¨ii), L1 and L2 must be equal, besides we can use (8) for analyzing the input current ripple through the full operation range. ܸ ܦሺͳ െ ܦሻ ܸ ሺʹ ܦെ ͳሻ ο݅ ൌ ቆ െ ቇൌ ݂௦ ܮଵ ݂௦ ܮଵ ܮଵ (9) Expression (9) shows a linear dependence of current ripple on the value of the duty cycle. This fact can be appreciated in Fig 5. It is important to note that this current ripple is given in amperes (not in percentage).
As said before the load is connected to the voltage that results of adding VC1+VC3, hence voltage gain of the converter can be written as: ܸ ൌ ܸଶ ܸଷ ͳ ήܸ ܸଶ ൌ ܸଷ ൌ ͳെ ܦ ʹ ܸ ൌ ܸ ͳ െ ܦ (4) The plot in Fig. 4 shows the voltage gain as a function of the duty cycle is shown. It is clear that the gain of the proposed converter is twice the gain in a traditional boost converter. B. Input current ripple. From Fig. 3, it is clear that the current ripple of each one of the inductors is given by: ο݅ଵ ൌ ο݅ଶ
ܸ ܸ ܦ ܶܦ௦ ൌ ή ܮଵ ܮଵ ܨ௦
ܸ ܸ ܦ ൌ ܶܦ௦ ൌ ή ܮଶ ܮଶ ݂௦
(5)
(6)
Fig. 5. Input current-ripple vs. duty cycle.
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In Fig. 7 the output voltage waveform is shown, it has an average voltage of 195.5 V that is very close to the expected 200v for 50% duty cycle.
Finally and consistent with (3)), the average current through the inductors can be defined as: ܫଵ ܫଶ ൌ
IV.
ܸଶ ܸଷ ͳ ൌ ܫ ሺͳ െ ܦሻܴ ሺͳ െ ܦሻ
SIMULATION AND EXPERIMENTAL RESULTS
A. Simulation. The proposed converter was simulated in the saber sketch platform. Real parameters were taken into account. A complete list of parameters is provided in Table I. TABLE I.
SIMULATION PARAMETERS
Parameter
Value
Fig. 7. Simulated waveform: output voltage .
Input voltage
50 V
Duty cycle
50%
Output voltage
200 V
L1
160μH
Fig. 8 shows the capacitors voltage with relative good voltage balance. Despite of the capacitor low value (8μF), the voltage ripple is very low, this is another benefit of have low input current ripple. The efficiency of the simulated converter is 94%.
L2
160μH
C1, C2, C3
8μF
Mosfets
VDS 200V,ID 130A, RDS 8m
Diodes
250V, 40A, VF 0.86V
Fs
50 kHz
Load
125
(a)
In Fig. 6 Current waveforms are presented. can be see that the inductor currents are shifted 180°, the inductor value was calculated for large inductor current ripple, but due to the ripple cancelation, the input current has almost zero ripple
(b) Fig. 8. Simulated waveforms: (a) C2 voltage, (b) C3 voltage .
From the simulation plots, it can see that the input current ripple is almost zero. A closer examination of the results also suggests the simulation data are consistent with the analytical results developed earlier in this paper. Fig. 6. Simulated waveforms: inductors current and imput current .
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In Fig. 11(b) the current through S2 can be seen, from Fig. 2 it is clear that when S2 closed their current is equal to IL2.
B. Experimental results. An experimental prototype was constructed to validate analytical and simulation results, the prototype shown in Fig. 9 has a 500W power rating and was constructed with the same parameters as were used in the simulation.
Some values measured during the experimental test are presented in Table II. TABLE II.
MEASURED VALUES
Parameter
Value
Input voltage
50 V
Input power
310 W
Output voltage
190 V
Output power
285 W
Efficiency
92%
Fig. 9. Experimental prototype .
Fig.10 shows illustrative waveforms for the converter operating at D = 50%, despite the small current imbalance in the phases induced by the difference values of inductance, parasitic resistances, duty cycle and other in each phase, the input current (Ii) is almost ripple-free.
(a)
Fig. 10. Experimental waveforms of IL1, IL2 and Ii.
In Fig. 11 the mosfet current waveforms are presented, Fig. 11(a) shows the current through S1, it can see that there is a current peak due to the energy transference between C1 and C3 when both are paralleled; in this case the switching period is large enough so that the capacitor C1 reaches the voltage of the capacitor C3, when this occur the charging current becomes zero and the S1 current is only IL1.
(b) Fig. 11. Experimental waveforms: (a) S1 current, (b) S2 current.
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V.
CONCLUSIONS.
This paper proposes a DC–DC interleaved PWM converter topology with advantages such as: (i) high voltage gain without extreme duty cycle, (ii) low input current ripple by interleaved inductors, (iii) voltage balancing in output capacitors. (iv) low count of components and reduced weight and size. Those features are highly desirable in fuel cell electric vehicle applications. Simulated-based results are provided along with a theoretical analysis. Finally an experimental prototype was constructed and tested to validate the features of the converter.
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