Inverters With Strained Si Nanowire Complementary ... - IEEE Xplore

6 downloads 0 Views 836KB Size Report
May 20, 2013 -

IEEE ELECTRON DEVICE LETTERS, VOL. 34, NO. 6, JUNE 2013

813

Inverters With Strained Si Nanowire Complementary Tunnel Field-Effect Transistors Lars Knoll, Qing-Tai Zhao, Member, IEEE, Alexander Nichau, Stefan Trellenkamp, Simon Richter, Anna Schäfer, David Esseni, Luca Selmi, Konstantin K. Bourdelle, and Siegfried Mantl, Member, IEEE Abstract— Inverters based on uniaxially tensile strained Si (sSi) nanowire (NW) tunneling field-effect transistors (TFETs) are fabricated. Tilted dopant implantation using the gate as a shadow mask allows self-aligned formation of p-i-n TFETs. The steep junctions formed by dopant segregation at low temperatures improve the band-to-band tunneling, resulting in higher oncurrents of n- and p-TFETs of > 10 µA/µm at VDS = 0.5 V. The subthreshold slope for n-channel TFETs reaches a minimum value of 30 mV/dec, and is < 60 mV/dec over one order of magnitude of drain current. The first sSi NW complementary TFET inverters show sharp transitions and fairly high static gain even at very low VDD = 0.2 V. The first transient response analysis of the inverters shows clear output voltage overshoots and a fall time of 2 ns at VDD = 1.0 V. Index Terms— Inverter, strained Si (sSi) nanowire, subthreshold slope, tunnel-FET.

I. I NTRODUCTION AND-to-band tunneling field-effect transistors (TFETs) are very attractive for ultralow power applications because of their potential for overcoming the 60 mV/dec limit of the inverse subthreshold slope (SS) in conventional MOSFETs at 300 K [1], [2]. For achieving high tunneling currents, new materials and novel device structures have to be implemented. Semiconductors with lower bandgap E g , as well as high-k dielectrics, are needed. III–V [3], SiGe [4], [5], and Ge [4], [6] provide higher tunneling probabilities because of their small E g . In addition, tensile strained Si (sSi) that has a smaller E g than Si improves the tunneling currents [5], [7]. In addition, the uniaxial strain in Si nanowires (NWs) along the direction lifts the sub-band degeneracy of the valence and conduction bands, leading to a carrier repopulation in the subbands and hence to a reduction of the effective mass m ∗ of electrons and holes [8]. NW structures with multigates are preferred for TFETs as they provide improved electrostatics, and thus higher tunneling currents [7], [9], [10]. Another critical technology step is the formation of optimized tunneling junctions to achieve a steep dopant profile. The conventional tunneling junctions in

B

Manuscript received March 18, 2013; revised April 8, 2013; accepted April 13, 2013. Date of current version May 20, 2013. This work was supported by the European project STEEPER. The review of this letter was arranged by Editor M. Östling. L. Knoll, Q.-T. Zhao, A. Nichau, S. Trellenkamp, S. Richter, A. Schäfer, and S. Mantl are with the Peter Grünberg Institute, Jülich Aachen Research Alliance -FIT, Forschungszentrum Jülich, Jülich 52425, Germany (e-mail: [email protected]). D. Esseni and L. Selmi are with the Dipartimento di Ingegneria Elettrica Gestionale e Meccanica, University of Udine, Udine 33100, Italy. K. K. Bourdelle is with SOITEC, Parc Technologique des Fontaines, Bernin 38190, France. Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/LED.2013.2258652

Si-TFETs are normally realized by implantation and rapid thermal annealing. However, pronounced diffusion of dopants during annealing broadens the junctions and decreases the tunneling currents drastically, typically for p+ − i junctions formed by B+ implantation. Therefore, the best sub60 mV/dec characteristics are obtained for p-TFETs, as n + −i junctions are much steeper because of less diffusion of arsenic [7], [9]–[11]. Even so, the reported tunneling currents are still very small [7], [9], [10]. Optimized silicidation and a lowtemperature anneal show improvement of currents in p-TFET [11], but the on-currents of n-TFETs are very small [11]. Because of these limitations, complementary TFETs (C-TFETs) with comparable performance of both p- and n-TFETs and hence inverters are not reported with Si technology yet. In this letter, we experimentally demonstrate a novel and simple method to make tunneling junctions by dopant segregation (DS) in sSi NW TFETs. With this technique we fabricate C-TFETs with higher on-currents and better SS. We present for the first time inverters with sSi NW C-TFETs. II. D EVICE FABRICATION Strained Si on insulator (sSOI) wafers with a biaxial strain of ε = 0.8% are used as a substrate. After patterning the sSOI layer into NW arrays, the elastic relaxation across the NWs yields a uniaxial tensile strain along the wires [7], [12]. The gate-stack is formed with 3-nm HfO2 layer and a 20-nm-thick TiN metal gate. Each TFET consists of an array of 100 parallel NWs with a gate length of 200 nm. Epitaxial NiSi2 contacts at source/drain (S/D) are formed by silicidation of a very thin Ni layer (< 3 nm) on sSi at 700 °C [13]. As a novel step, the S/D-doped junctions are formed without additional implantation masks. The gate-stack is used as a shadow mask for the tilted (45/135°) As+ and B+ ion implants into the silicide (IIS), as shown in Fig. 1(a) for an inverter layout. This allows the formation of perfectly selfaligned n+ and p+ pockets at the edges of NiSi2 S/D after low-temperature annealing (450 °C) by DS [Fig. 1(b)]. With a two-finger gate structure an inverter consisting of physically identical n- and p-TFETs where the biasing determines the p- and n-operation modes can be easily formed [Fig. 1(a)]. The implantations are carried out at energies of 1 keV for B+ and at 5 keV for As+ , both with a dose of 2 × 1015 /cm2 . Fig. 1(c) shows a scanning electron microscopy (SEM) image of a section of the sSi NW array TFET. The cross-section transmission electron microscopy (XTEM) image of Fig. 1(d) shows a trapezoidal shape of the sSi NW with a thickness of only 7 nm and a base width of 45 nm, and an equivalent oxide thickness of 2.2 nm. An XTEM image [Fig. 1(e)] prepared by focused ion beam cutting along the NW demonstrates the uniformity and perfect gate alignment of the silicide without

0741-3106/$31.00 © 2013 IEEE

814

IEEE ELECTRON DEVICE LETTERS, VOL. 34, NO. 6, JUNE 2013

Fig. 1. (a) Schematic of sSi NW TFET inverter fabricated using tilted B+ and As+ ion implantations into epitaxial NiSi2 S/D contacts. Highly doped n+ and p+ pockets at the silicide edges are created with IIS after a low-temperature anneal, forming (b) an n-TFET on the left and a p-TFET on the right in (a). (c) SEM image of the NW array TFET. (d) XTEM image of single sSi NW with gate-stack. (e) XTEM cross-section along the NW, indicating a perfectly aligned NiSi2 contact to the channel.

encroachment into the sSi channel after completed processing. The ultrathin epitaxial NiSi2 also offers high uniformity along the gate edges as we demonstrate for a planar structure [14]. III. TFET C HARACTERIZATION Fig. 2(a) shows the output characteristics of the sSi NW C-TFETs, where the drain currents are normalized with a gate width of 50 nm for each NW. Comparatively, high on-currents of ION = 10.3 μA/μm (VGS = −1.2 V, VDS = −0.5 V) for the p-TFET and ION = 18.3 μA/μm (VGS = 1.6 V, VDS = 0.5 V) for the n-TFET are obtained, distinctly higher than for most reported Si TFETs [7], [9], [10], [15], [16]. This also holds for our recent sSi NW TFETs in which S/D junctions are formed by ion implantation into the NW and spike annealing [7]. Obviously the great improvement stems from the IIS junctions. Direct tunneling of carriers through the Schottky barrier at high VGS could also be a source for high I D [16]; however, the tunneling currents through the Schottky barrier are much smaller than band-to-band tunneling currents according to simulations [17]. It is also remarkable to mention that the n-TFET shows a linear I –V on-set and good saturation at VDS > 0.5 V, indicating highly doped tunnel junctions [18]. Fig. 2(b) shows the transfer curves of the corresponding C-TFETs measured at 300 K. As expected for homojunction TFETs, ambipolar characteristics are observed. The n-TFET shows a much steeper SS than the p-TFET, reaching a minimum SS ∼ 30 mV/dec with an SS < 60 mV/dec range more than one order of magnitude of I D , as shown in Fig. 2(c). The increase of SS with I D is typical for TFETs. The gate leakage currents IG for the NW n-TFET are much smaller than I D as shown in Fig. 2(b), demonstrating that the very small SS is not caused by the gate leakage current. The p-TFET shows a minimum SS of 90 mV/dec with a slight kink in the I D –VGS curves, indicating trap assisted tunneling (TAT). The quality of the tunneling junction formed by IIS depends on the diffusion, activation, and segregation of dopants, as well as defects remaining in the tunneling region. In As+ implanted junctions defects obviously remain after annealing at 450 °C because of the heavy ion mass, leading to TAT with high tunneling currents but poorer SS [11], [19]. Obviously the B+ implanted tunneling junctions are of

Fig. 2. (a) I D –VDS characteristics of NW array C-TFETs showing high on-currents. (b) Corresponding I D –VGS characteristics of sSi NW array C-TFETs, providing a minimum SS of 30 mV/dec for the n-FET (c), and of 90 mV/dec for the p-TFETs at 300 K. (c) ID-range with SS < 60 mV/dec extends over one order of magnitude of I D . (d) Low-temperature (T ) measurements demonstrate a BTBT dominated transport mechanism with an almost constant SS in the investigated temperature range.

significantly better quality. Fig. 2(d) shows the transfer characteristics measured at different temperatures. The average SS in an I D ranging from 1 × 10−5 to 1 × 10−2 μA/μm shown in the inset remains almost the same, which further substantiates tunneling dominated transport. A comparison with the InGaAs homojunction TFETs reported by Intel [3] reveals similar SS and IDS at very low VDS = 0.3 V for the NW n-TFET of this experiment. Remarkably, the Ion /Ioff ratio of the sSi NW TFETs is significantly larger, presumably because of the larger bandgap. Compared with our previous results for planar TFETs [19], NW n-TFETs show much smaller SS and higher Ion because of the improved electrostatics. IV. I NVERTER C HARACTERIZATION The applied C-TFET fabrication process and the improved performance for sSi NW n- and p-TFETs, allow the realization of inverters, as shown in Fig. 1(a). The corresponding voltage transfer characteristics (VTC) of the first TFET inverter are shown in Fig. 3(a) at different VDD . A sharp transition with wide noise margin is observed even at a VDD as low as 0.2 V. The corresponding inverter gains VOUT /VIN at various VDD are shown in Fig. 3(b). A high gain of 57 is obtained at VDD = 1.2 V. Most remarkable, even at VDD = 0.2 V a gain of ≈ 3 is still achieved. The nominal output voltage VOUT shows degradation indicated by VOUT < VDD at small input voltage VIN and VOUT > 0 V at high VIN . This degradation is caused by the ambipolar behavior of the C-TFETs. We calculate the VTC of the inverter by setting equal currents for both the n- and p-TFETs from the measured I D –VDD data. Fig. 3(c) shows, as expected, that the calculated VTC matches perfectly the measured VTC, for example, at VDD = 1.0 V. The degradation of the high nominal output voltage (VOUT < VDD at VIN < 0.5 V) is found to be mainly because of the strong ambipolarity of the n-TFET, whereas the low nominal

KNOLL et al.: INVERTERS WITH STRAINED Si NANOWIRE COMPLEMENTARY TUNNEL FIELD-EFFECT TRANSISTORS

Fig. 3. (a) VTC and (b) voltage gain for NW TFET inverters, functioning at VDD = 0.2 V. (c) Experimental and calculated VTC for NW TFET at VDD = 1 V. The calculation confirms that the nominal value of the high VOUT recovers to VDD = 1 V and the low VOUT approaches to 0 V as the ambipolarities of both the n- and p-type transistors are removed. (d) Transient response of NW C-TFET inverter at VDD = 1.0 V, showing clear voltage overshoots.

VOUT > 0 is caused by the ambipolarity of the p-TFET. To confirm the analysis, we calculate the VTC with suppressed ambipolarity of both, the n- and p-TFETs, by flatting the measured IDS –VGS characteristics at the minimum I D in the off-states. The high nominal VOUT recovers to VOUT = VDD = 1.0 V, and VOUT = 0 at high VIN . The slow decrease of VOUT to 0 V in the calculated curve with suppressed ambipolarities is caused by the higher measured minimum currents of p-TFET at larger VDD . Fig. 3(d) shows the measured transient response characteristics for the NW C-TFETbased inverter at VDD = 1.0 V. The rise and fall times for the input signal are 130 ps. The inverter shows a fall time of ∼ 2 ns and a rise time of ∼ 3 ns (10% and 90% VOUT ) at VDD = 1.0 V The propagation delay t p is ∼ 1.9 ns that are estimated using t p = (tpr + tpf )/2, with tpr and tpf being the times for VOUT to rise and fall by 50%. Clear voltage overshoot is observed because of the large Miller capacitance of the TFET structure [20], [21]. V. C ONCLUSION In this letter, we fabricated sSi NW C-TFETs and inverters with a novel and easy process by fabricating the tunneling junctions using tilted IIS. The low-temperature process allowed the formation of self-aligned, steep doping profiles right at the edge of the silicided source. Both n- and p-TFETs showed high ION currents. A minimum SS of 30 mV/dec at 300 K was achieved for n-TFETs. First inverters showed sharp transitions even at VDD = 0.2 V. The transient analysis resulted in a rise time of 2 ns at VDD = 1.0 V and showed clear output voltage overshoots. R EFERENCES [1] A. M. Ionescu and H. Riel, “Tunnel field-effect transistors as energyefficient electronic switches,” Nature, vol. 479, no. 7373, pp. 329–337, 2011. [2] A. C. Seabaugh and Q. Zhang, “Low-voltage tunnel transistors for beyond CMOS Logic,” Proc. IEEE, vol. 98, no. 12, pp. 2095–2110, Dec. 2010.

815

[3] G. Dewey, B. Chu-Kung, J. Boardman, J. M. Fastenau, J. Kavalieros, R. Kotlyar, W. K. Liu, D. Lubyshev, M. Metz, N. Mukherjee, P. Oakey, H. W. Then, and R. Chau, “Fabrication, characterization, and physics of III-V heterojunction tunneling field effect transistors H-TFET for steep sub-threshold swing,” in Proc. IEEE Int. Electron Devices Meeting, Dec. 2011, pp. 33.6.1–33.6.4. [4] F. Mayer, C. Le Royer, J.-F. Damlencourt, K. Romanjek, F. Andrieu, C. Tabone, B. Previtali, and S. Deleonibus, “Impact of SOI, Si1-xGexOI and GeOI substrates on CMOS compatible tunnel FET performance,” in Proc. IEEE Int. Electron Devices Meeting, Dec. 2008, pp. 1–5. [5] Q. T. Zhao, J.-M. Hartmann, and S. Mantl, “An improved Si tunnel field effect transistor with a buried strained Si1−3 Gex source,” IEEE Electron Device Lett., vol. 32, no. 11, pp. 1480–1482, Nov. 2011. [6] D. Kazazis, P. Jannaty, A. Zaslavsky, C. Le Royer, C. Tabone, L. Clavelier, and S. Cristoloveanu, “Tunneling field-effect transistor with epitaxial junction in thin germanium-on-insulator,” Appl. Phys. Lett., vol. 94, no. 26, pp. 263508-1–263508-3, Jul. 2009. [7] S. Richter, C. Sandow, A. Nichau, S. Trellenkamp, M. Schmidt, R. Luptak, K. K. Bourdelle, Q. T. Zhao, and S. Mantl, “-Gated silicon and strained silicon nanowire array tunneling FETs,” IEEE Electron Device Lett., vol. 33, no. 11, pp. 1535–1537, Nov. 2012. [8] D. Esseni, P. Palestri, and L. Selmi, “Nanoscale MOS transistors: Semiclassical transport and applications,” Cambridge, U.K.: Cambridge Univ. Press, 2011. [9] K. E. Moselund, M. T. Bjork, H. Schmid, H. Ghoneim, S. Karg, E. Lörtscher, W. Riess, and H. Riel, “Silicon nanowire tunnel FETs: Low-temperature operation and influence of high-k gate dielectric,” IEEE Trans. Electron Devices, vol. 58, no. 9, pp. 2911–2916, Sep. 2011. [10] R. Gandhi, Z. Chen, N. Singh, K. Banerjee, and S. Lee, “CMOScompatible vertical-silicon-nanowire gate-all-around p-Type tunneling FETs with ≤ 50-mV/decade subthreshold swing,” IEEE Electron Device Lett., vol. 32, no. 11, pp. 437–439, Nov. 2011. [11] D. Leonelli, A. Vandooren, R. Rooyackers, A. S. Verhulst, S. De Gendt, M. M. Heyns, and G. Groeseneken, “Silicide engineering to boost Si tunnel transistor drive current,” Jpn. J. Appl. Phys., vol. 50, no. 4, pp. 04DC05-1–04DC05-4, 2011. [12] S. F. Feste, J. Knoch, S. Habicht, D. Buca, Q. T. Zhao, and S. Mantl, “Silicon nanowire FETs with uniaxial tensile strain,” Solid-State Electron., vol. 53, no. 12, pp. 1257–1262, Dec. 2009. [13] L. Knoll, Q. T. Zhao, S. Habicht, C. Urban, B. Ghyselen, and S. Mantl, “Ultrathin Ni silicides with low contact resistance on strained and unstrained silicon,” IEEE Electron Device Lett., vol. 31, no. 4, pp. 350–352, Apr. 2010. [14] L. Knoll, Q. T. Zhao, S. Trellenkamp, K. K. Bourdelle, and S. Mantl, “20 nm gate length Schottky MOSFETs with ultra-thin NiSi/epitaxial NiSi2 source/drain,” Solid-State Electron., vol. 71, pp. 88–92, May 2012. [15] K. Jeon, W.-P. Loh, P. Patel, C. Y. Kang, J. Oh, A. Bowonder, C. Park, C. S. Park, C. Smith, P. Majhi, H. H. Tseng, R. Jammy, T. J. King Liu, and C. Hu, “Si tunnel transistors with a novel silicided source and 46mV/dec swing,” in Proc. Symp. VLSI Techol., Jun. 2010, pp. 121–122. [16] Q. Huang, Z. Zhan, R. Huang, X. Mao, L. Zhang, Y. Qiu, and Y. Wang, “Self-depleted T-gate Schottky barrier tunneling FET with low average subthreshold slope and high ION/IOFF by gate configuration and barrier modulation,” in Proc. Int. Electron Devices Meeting, Dec. 2011, pp. 382–385. [17] L. Knoll, A. Nichau, A. Schaefer, K. K. Bourdelle, Q. T. Zhao, and S. Mant, “Gate-all-around Si nanowire array tunnelling FETs with high on-current of 75 mA/mm @ VDD = 1.1 V,” in Proc. ULIS, 2013, pp. 1–14. [18] L. De Michielis, L. Lattanzio, and A. M. Ionescu, “Understanding the superlinear onset of tunnel-FET output characteristic,” IEEE Electron Device Lett., vol. 33, no. 11, pp. 1523–1525, Nov. 2012. [19] L. Knoll, Q. T. Zhao, S. Trellenkamp, A. Schäfer, K. K. Bourdelle, and S. Mantl, “Si tunneling transistors with high on-currents and slopes of 50 mV/dec using segregation doped NiSi2 tunnel junctions,” in Proc. Eur. Solid-State Device Res. Conf., Sep. 2012, pp. 153–156. [20] J. Zhuge, A. Verhulst, W. Vandenberghe, E. Dehaene, R. Huang, Y. Wang, and G. Groeseneken, “Digital-circuit analysis of short-gate tunnel FETs for low-voltage applications,” Semicond. Sci. Technol., vol. 26, no. 8, p. 085001, 2011. [21] S. Mookerjea, R. Krishnan, S. Datta, and V. Narayanan, “Effective capacitance and drive current for tunnel FET TFET CV/I estimation,” IEEE Trans. Electron Devices, vol. 56, no. 9, pp. 2092–2098, Sep. 2009.

Suggest Documents