Apr 5, 2002 - 26. ISSCC-2010. Got its own session at ISSCC â 7 out of 8 papers! (Columbia U.) (NEC). (Atheros). (U. Twente). (P. Milano). (Infineon). (IMEC).
EBCCSP & NoMe TDC-2016:
It is Time to use Time (for Digital RF Clock Generation) R. Bogdan Staszewski Professor, IEEE Fellow University College Dublin Dublin, Ireland 2016-06-15
UCD - Staszewski
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1995: Analog-Intensive PRML Read Channel Sampled-Data Analog Signal Processing
Continuous-Time Analog Signal Processing Preamp
AGC
FIR
CTF
Equalizer
Signal Response A
PR4 Targets
Viterbi Detector
1bit
Adapt Coefficients
0.8um BiCMOS
Required Signal Boost Fs/2
freq
Timing Recovery
• The hottest topic in analog IC design 2016-06-15
UCD - Staszewski
[1997 JSSC Kiriaki] 2
Hard-Disk Drive Read Channel • HDD following Moore’s law just as semiconductors Over 5 decades
• H. Thapar, CICC-1999, “Hard Disk Drive Read Channels: Technology and Trends” 2016-06-15
UCD - Staszewski
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1997: Digitally Intensive PRML Read Channel 0.18um CMOS
Magnetic storage and read/write head
• Mostly digital frequency-domain equalization • 750MS/s Digital
Unequalized samples
Preamp
PGA
CTF
ADC
6
CLK Write Precomp
AGC
Timing Recovery (PLL)
Write Datapath
FIR Filter
Equalized samples 8
Viterbi 1 detector
c(n)
Coefs
Error/ Gradient
Timing gradient Gain gradient
2016-06-15
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1999: Digital RF • Hottest new area in IC mixed-signal design was now RF • Brain drain from read channel? • Wireless was booming • GSM standardized in Europe • Bluetooth
• The read channel for HDD was another form of a communication channel • Temporal: Write at time A, read back at time B
• GSM carrier frequency was 900MHz • Compare to 750MS/s Time A Point A
Time B 2016-06-15
UCD - Staszewski
Point B 5
1999: Eureka #1 TI read channel: 750MS/s digital processing 0.18um CMOS
RF transceiver, 0.25um CMOS
?
[2007 DCAS Staszewski]
[2001 ISSCC Opt’Eynde]
• Can RF transceiver be digitized at 900MHz clock? • Possibly yes, but excessive power 2016-06-15
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1999: Digitally Controlled Oscillator • Doing it “all-digital-logic” was out of question • RF oscillator still LC-tank based • But why not digital control?
• Implemented in 130nm CMOS • Finest varactor size: 1 atto-farad! • 1 electron
• SD varactor dithering (Eureka #2) • Feedback loop around DCO could now be fully digital LC tank
-R C
(a) 2016-06-15
L
Digital control
Analog control
LC tank
C0
C1
C2
C3
CN-1
-R L
(b) UCD - Staszewski
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1999: Eureka #2 1/s
DCO MSB s
RF out
Interface logic
Integer value capacitance
reference cycle
C2
LSB s
Digital SD modulator
time
C1
Fractional average value
High-speed clock (~225 MHz)
8
RF clock (~1.8 GHz)
Tuning word (tracking)
f
• High-speed dithering of DCO varactors • Oversampling using its own clock 2016-06-15
UCD - Staszewski
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All-Digital Phase-locked Loop Charge-pump IP
Xtal osc. FREF PFD
Analog chargepump PLL
VCO
VTune
CKV
R1
IN
C2
C1
÷N
Xtal osc. FREF
2016-06-15
Up Down
FCW
TDC-based ADPLL
Loop filter
Σ
Reference phase
TDC
+ -
FCW
ΣΔ Mod.
DCO
Phase error Digital OTW LF ΔΣ
Variable phase
UCD - Staszewski
CKV
Variable clock 9
2000: Time-to-Digital Converter (TDC) • Quantized phase detector with resolution of 5-20 ps • DCO clock passes through the inverter chain • Delayed outputs are sampled by FREF • Simple TDC can outperform a good PFD – Eureka #3 D(48)
DCO FREF Q(1)
Q(48)
P-Thermometer-Code Detector
FREF
TDC_RISE
normalizer 2016-06-15
DCO D(1) D(2) D(3) D(4) D(5) D(6) D(7) D(8)
Q(1:10)
TDC_RISE UCD - Staszewski
0011110000 6 10
Effect of TDC Resolution on Phase Noise In-band phase noise [dBc/Hz]
-90
Fref = 50MHz, Fosc = 2.5GHz -100 -110
FCW
S
Phase error Loop
FREF
-120
DCO
Filter
TDC -130
Sf(w)
Dtinv
Best crystal oscillator ($100s) -140 -150 0
5
10
15
20
Inverter delay == TDC resolution [ps] 2016-06-15
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Time Resolution Gets only Better • Inverter delay enjoys 0.7x scaling per node (2 years) • Area scaling of 0.5x is even better 100
ITRS
10 2005
2007
2009
2011
2013
70% / 2yr
2015
2017
CMOS propagation time ITRS roadmap (year 2005 = 100)
• Inverter-based TDC is used as phase detector in RF PLL’s – [Staszewski’02], [Staszewski’06], [Tonietto’06], [Hsu’08], [Wu’08], [Lee’08] 2016-06-15
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Time-to-Digital Converter Circuitry 1
D Q
Σ
Integer part Reference phase Variable phase -
FREF resampler
CKV FREF
CKV
t
+
Phase error ΦE[k]
TDC
DCO
Glitch removal
DLF
Cell 50
Dummy cells
CKV
Fractional part
1/KTDC Edge aligner Dummy cells
Cell 1
FREF
[2014 CICC Wu]
Decoder TDC_rise
2016-06-15
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TDC_fall 13
TDC Core Layout • • • •
Precise layout for best resolution and linearity Minimal interconnect parasitics Measured Δtres= 12.2 ps with both INL and DNL < 1LSB FREF edge prediction is used to gate the TDC input clock for power saving: < 1 mA
[2014 CICC Wu] 2016-06-15
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TDC Normalization (Calibration) • Expected output between 0~1 (i.e., 0 ~ 2^WF
-Ɛ =
2^WF
Tv/Δtinv
Δtr
• Accurate calibration of the inverter delay
1 Tv = N
Navg
ΣT [k]
avg k=1
2016-06-15
v
UCD - Staszewski
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Programmable Loop Filter 1st IIR
4th IIR
-log2l
Phase error ΦE
-log2a0 -log2(a/a0) 0 1
IIR1_en
QD
αΦE
QD
ckr syn_reset Switchable IIR filter
GS event -log2rk
• Bandwidth affects phase error, settling, jitter. • Hitless gear shift • Proportional, integral path and IIR all configurable 2016-06-15
Loop filter output
0 1 -log2rk/rK-1 GS event
UCD - Staszewski
DQ ckr [2014 CICC Wu]
16
2016-06-15
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• Not much work on monolithic TDC before year 2000 • Except for University of Oulu, Finland
• Mostly for time-of-flight: nuclear science, astronomy 2016-06-15
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ADPLL: TDC-Centric View
• Digitally synchronous fixed-point arithmetic for Phase error PHE[k] = RR[k] - (RV[k] + Ɛ[k]) • Oversampling FREF by CKV and using the resulting CKR for phase error generation • Alignment between RV[k] and Ɛ[k] 2016-06-15
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All-Digital PLL and Transmitter • Building blocks: • TDC (RF-ADC) • DCO (RF-DAC) • DPA (RF-DAC)
Discrete-time operation Maximally digital No bias current sources Fairly coarse resolution
RF variable clock
S1/Ron
FREF
C0
C1
CN-1
-R
L
Time-to-digital converter (TDC) All-digital phase-locked loop (ADPLL)
Digitally-controlled oscillator (DCO)
Frequency command word (FCW) 2016-06-15
UCD - Staszewski
Amplitude control word
Digital logic
LC tank
Matching network
• • • •
Digital power amplifier (DPA) 20
2001: ADPLL in 130nm CMOS • The first TDC was simply synthesized and APR’ed
Inductor: 270x270 um • 10,000s of digital gates per inductor
2016-06-15
UCD - Staszewski
[2005 TVLSI Staszewski]
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Timeline of Digital RF at TI 1995 Analog 1999 Read Channel Digital 2000 for HDD RF idea TDC 1997 1999 Digital DCO Read Channel
2002 PhD thesis
2004 GSM SoC
2003 2001 ADPLL Bluetooth SoC
2008 EDGE SoC
• Eureka #1: Digitization of RF carrier • Eureka #2: DCO – avoidance of any analog tuning • Eureka #3: TDC – string of inverters of 5-20ps • Eureka #4: ADPLL - digital logic loop around DCO and TDC with only one RF passive 2016-06-15
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2016-06-15
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Improving RF-DAC Resolution Through Timing [Park, Perrott, Staszewski, TCAS1-2011, “An Amplitude Resolution Improvement of an RFDAC Employing Pulsewidth Modulation”]
• RFDAC: 10-b -> 13-b • Perrott: “It is time to use time”
2016-06-15
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ISSCC-2007
2016-06-15
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ISSCC-2010
Got its own session at ISSCC – 7 out of 8 papers! (Columbia U.)
(NEC) (Atheros) (U. Twente) (P. Milano) (Infineon) (IMEC) 2016-06-15
UCD - Staszewski
(Pohang U.)
26
Time-Domain RF and Analog Signaling
2016-06-15
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Electrical Signals Vmax v(t)
v(t1) v(t2)
VS t Vmin
• Electrical signal typically encodes the information as a voltage level v(t) versus time t. • Sometimes it could be a current level i(t) or charge level q(t). 2016-06-15
UCD - Staszewski
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Analog Signals v(t)
v(t)
continuous-amplitude continuous-time
continuous-amplitude discrete-time
v[2] v(t1) v[7] 0
t1
t
k
0 1 3 4 5 6 7
• Analog signal amplitude is continuous • Analog signal time can be continuous or discretized • Discretization in time involves sampling • Many sampling methods: impulse, zero-order hold, sampled integration, etc. 2016-06-15
UCD - Staszewski
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Digital Signals discrete-amplitude discrete-time
v(t)
v(t)
continuous-amplitude continuous-time
continuous-amplitude discrete-time
v[2]
d[k]
v(t1) v[7] 0
t1
t
0 1 3 4 5 6 7
k
k
0 1 3 4 5 6 7 8
• Digital signals quantize v(t) into two levels (logic HIGH and LOW) and use an array of them (i.e., word) • Synchronous digital circuits use clocks, hence d[k] is a digital bit or word value at a discrete-time index k.
2016-06-15
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Information Carrier of an Electrical Signal • These signal representations are well known and commonly used • Continuous-amplitude and continuous-time (a.k.a., traditional analog) • Continuous-amplitude and discrete-time (a.k.a., sampled analog) • Discrete-amplitude and continuous-time (a.k.a., digital)
• The information is contained in a voltage amplitude level • Is this all? Can a signal be represented in other forms? • What about time?
2016-06-15
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Time-Domain Signaling Vmax v(t)
HIGH
v(t1)
VS
v(t2)
t[k3] t[k1] t[k2]
t[k4]
t Vmin
LOW
• Question: Can time (i.e., timestamp) be the information carrier t[k]? • This time-domain signal processing approach has barely been exploited… • Why? 2016-06-15
UCD - Staszewski
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Time-Domain Signaling v(t)
binary-amplitude continuous-time
continuous-amplitude discrete-time
v[2]
k
v(t) v[6] 0 1 2 3 4 5 6
k
1 2 3 4 5 6
• Time-domain operation is a discrete signal • Instead of the amplitude, it is the timestamp that carries the information
2016-06-15
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Progress of CMOS Technology tr=500ps
800nm
5V 4V 3V
Scaling: faster edges but lower voltage
350nm
2V 40nm
1V 0V
time
• Voltage-domain resolution gets worse • VDD goes down • Vth stays the same
• Time-domain resolution gets better • Edges are now super-sharp with 20ps risetime
• Exploit the time-domain for RF and analog functions 2016-06-15
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Sharp Edges Needed v(t) voltage noise, threshold uncertainty
LOW
HIGH 1
timing noise (jitter)
2
t
• Transition edge that carries the information needs to be sharp, otherwise the voltage noise and threshold uncertainty and will worsen the timing noise 2016-06-15
UCD - Staszewski
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It is Time to Use Time... • Now the mainstream CMOS technology is extremely fast
V(t)
Trajectory tracking
• Good news for the time-domain!
• However, the voltage supply levels are very small: Difficult to resolve voltage-domain signals DV
Fast transition
• “Don't care” for the time-domain!
t
Dt
• Seems like the mainstream CMOS technology is now ready! • It is time to use time! • However, obstacles: – New theory of the time-domain signal processing and circuit architectures is not well developed – Reluctance to change in scientific and industrial communities 2016-06-15
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Time-Domain vs. Digital • Despite some similarities, the time-domain operation is different from the digital operation • In digital, the voltage level is important but the transition time is not • As long as the setup time between the next clock edge is satisfied, of course
• In time-domain, the transition time is of significance, not the actual voltage level • However, the time-domain analog signal processing is often combined with the digital signal processing • “Digital RF”
2016-06-15
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• Large volume production • All-digital PLL (ADPLL) • All-digital ADPLLbased TX • Digitally-intensive discrete-time RX
10mm2 (3mm2 RF/analog)
Digital Baseband and Application Processor
130-nm 10mm2 Bluetooth SoC (TI) Channel
Digital Logic
TX data
SD
Amplitude Regulation DCO
TDC
RF Out TX/RX DPA Combine r LO clock
TX RX
RX data
Digital Logic
A/D
Power Management (PM)
Discrete time
LNTA Current sampler
RF In
RF Built-in Self Test (RFBIST)
• Heavy digital assistance • RF built-in self test (BIST) 2016-06-15
UCD - Staszewski
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DRP Historical Perspective: Timeline • 1999: DRP idea conceived • 2000: Digitally-controlled oscillator testchip • 2001 TX testchip: Full Bluetooth transmitter • 2002: Commercial single-chip Bluetooth radio • 2003: Single-chip GSM transceiver • 2004: Commercial single-chip GSM radio
2016-06-15
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Single-chip GSM Transceiver • 90 nm CMOS • Preproduction version of the single-chip GSM radio • Two pairs of TX & RX – Investigation of noise coupling for WCDMA
• Transceiver: ~7 mm2 • January 2004: 1st cellular phone call
2016-06-15
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Single-chip GSM Transceiver • First ever fully-integrated fully-compliant GSM transceiver IC in a deep submicron CMOS • Jan 2004: Successful cellular phone call over the GSM public network in Nice, France
Transceiver IC 2016-06-15
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First GSM Single-Chip Radio • “Single-chip GSM ready at the end of 2004” • Tom Engibous’, former CEO, commitment to TI shareholders in 2002
Intel, TI clash on baseband integration strategies By Rick Merritt, EE Times Apr 5, 2002 (12:39 PM) URL: http://www.eetimes.com/story/OEG20020405S0063 SAN MATEO, Calif. — A Goliath vs. Goliath battle is shaping up for the 390 millionunit cellular phone arena, and among the weapons of choice is CMOS integration. Supported by design and process technology prowess, Intel Corp. and Texas Instruments Inc. said they intend to brandish baseband devices that sport integrated nonvolatile memory and analog RF functions, a move that could reshape the competitive landscape for wireless. Texas Instruments, which commands the lion's share of the $2.4 billion cellular baseband market, said it will integrate analog RF with digital baseband chips at the 90-nanometer node in an attempt to create new mass markets for cellular telephones. Hoping to steal some of TI's thunder is Intel, a neophyte in wireless that is scouting 2016-06-15
UCD - Staszewski
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Digital RF Processor (DRPTM) Xtal Dither
• All-digital PLL • All-digital AM • Digitallyintensive discrete-time RX 2016-06-15
Front-end Module
SD
FREF
Internal DRP Processor
Digital Baseband Processor
SRAM
• System-on-chip (SoC) • Digitallyintensive implementation of RF circuits • Transforms RF functionality into:
Amplitude modulation
DCXO
· 2-watt PA · T/R switch · RX SAW filters
DPA SD Digital logic
Processor clock
Digital logic
Power Management (PM)
Battery Management UCD - Staszewski
A/D
DCO TDC
LO clock
TX
Dividers
Discrete time CH
iRF Current sampler
RX LNA +TA
RF in
RF Built-in Self Test (RF-BIST)
VBAT [Staszewski ISSCC 2005] 43
First GSM Single-Chip Radio Charger Connector
Audio Connector GSM/GPRS SoC
DRP
Digital
PA
20mm2 (3.8mm2 RF/analog) Flash 16Mb
Display Connector
RF Memory
Analog
December 2004 – fully functional March 2005 – 1st phone call August 2005 – 1st phone call on a commercial network 4Q 2006 – in volume production 2016-06-15
UCD - Staszewski
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DRP SoC Phones (4)
Nokia 1200
Nokia 1208
Display of phone selections in Northern Thailand
DRP phones are the least expensive! ($30 unsubsidized) 2016-06-15
UCD - Staszewski
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Written a Book on It • R. B. Staszewski and P. T. Balsara, “All-Digital Frequency Synthesizer in Deep-Submicron CMOS,” New Jersey: John Wiley & Sons, 2006 • Largely based on my 2002 PhD thesis • Used as textbook in “Digital RF” class at TU Delft (ET4371 - 4 credit hours)
2016-06-15
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Japanese Translation • Oct 2010: Paperback • Translated by Prof. Kobayashi
2016-06-15
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2013: Millimeter-Wave ADPLL Frequency command word Frequency reference
Reference phase ~60GHz + Phase DCO error LF ΔΣ TDC Σ Variable phase Variable clock a few GHz ÷N
Σ
RF out BUF RF & mm-wave Mixed-signal Digital (syth.)
[W. Wu, ISSCC-2013] 2016-06-15
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2016-06-15
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Nano-Satellite Communications • New paradigm in commercial satellites – E.g., 10x10x10 cm3 – Low-cost, fast design cycle
• Reuse of inexpensive cellular phone technology
Digital logic
Digital logic
PM
TDC
DCO
DPA
TX-N
SD
SD
PM
AM
TDC
DCO
DPA
TX-2
SD
SD
DCO SD
SD
PM
AM
TDC
TX-1
DPA
AM
Digital logic FREF
3-wire serial port interface (SPI)
Oscillator
• Array of antennas & transmitters – Beamforming, reliability
• Exploit high power efficiency of “timedomain RF” • Nanoscale CMOS is actually preferred for cosmic radiation
Controller
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Internet of Things (IoT) • Currently: Internet-of-people (IoP) • 30 billion autonomous wirelessly connected internet devices by 2020 • Low power: Harvesting energy from the environment
2016-06-15
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Frequency reference
RF-PLL RF transceiver
Non-RF-PLL
Analog baseband
Digital baseband
Energy management (EM) Light Heat Vibration RF
Energy harvester
Energy storage
Sensor
ADC
Actuator
DAC
Application processor
Antenna
Current Research at UC Dublin: IoT SoC
Voltage conversion
(optional)
• IoT SoC demo in nanoscale CMOS
2016-06-15
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