J. Sommarek, J. Vankka, J. Ketola, J. Lindeberg and K. Halonen ...

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Digital Modulator with Bandpass Delta-Sigma Modulator ... digital domain and then mixed to the second IF and to the radio frequency (RF) using analogue ...
J. Sommarek, J. Vankka, J. Ketola, J. Lindeberg and K. Halonen, Digital Modulator with Bandpass Delta-Sigma Modulator, Analog Integrated Circuits and Signal Processing, Vol. 43, No. 1, pp. 81-86, April 2005. © 2005 by authors and © 2005 Springer Science+Business Media Reprinted with kind permission of Springer Science+Business Media.

Digital Modulator with Bandpass Delta-Sigma Modulator Johan Sommarek, Jouko Vankka, Jaakko Ketola, Jonne Lindeberg and Kari Halonen

Electronic Circuit Design Laboratory, Helsinki University of Technology, P.0.Box 3000, FIN-02015, TKK, Finland, [email protected]

Abstract A digital quadrature modulator with a bandpass ∆Σ-modulator is presented that interpolates orthogonal input carriers by 16 and performs a digital quadrature modulation at carrier frequencies fs /4, −fs /4, (fs is the sampling frequency). After quadrature modulation, the signal is converted into an analogue IF signal using a bandpass ∆Σ modulator and a 1-bit D/A converter. The die area of the chip is 5.2mm2 (0.13µm CMOS technology). The total power consumption is 139mW at 1.5V with a clock frequency of 700MHz (D/A converter full-scale output current 11.5mA). Keywords: current steering differential pair, digital quadrature modulator, bandpass ∆Σ-modulator, 1-bit D/A-converter, multirate system

1. Introduction In traditional transmitters, a complex baseband signal is usually modulated to the first intermediate frequency (IF) in the digital domain and then mixed to the second IF and to the radio frequency (RF) using analogue mixers. We present a digital quadrature modulator that modulates the signal from the first IF to the second IF in the digital domain, thus only one analogue mixer is needed as illustrated in Fig. 1. The digital quadrature modulator is fed by two digital complex modulators, shown in Fig. 2, which modulate the baseband in-phase (I) and quadrature (Q) channels into orthogonal carriers (X, Y ) at the first IF frequency. One example of such a complex modulator suitable for this purpose is presented in [1]. These complex modulators can be operated at a much lower sampling frequency than the quadrature modulator. The complex modulators take care of the fine tuning of the transmitted carrier frequency with a sub-Hz resolution, whereas the digital quadrature modulator is used for the coarse tuning. It is beneficial to implement the fine tuning at lower sampling frequencies and the coarse tuning at the higher frequencies, because of the smaller amount of hardware associated with the coarse tuning implementation. The quadrature modulator interpolates orthogonal input carriers by 16 and performs a digital quadrature modulation moving the carriers around frequencies fs /4 and −fs /4, where fs is the output sampling frequency. The key advantages in performing the quadrature modulation in the digital domain are the high precision achieved and the perfect I/Q-channel matching. The major limiting factor of digital IF modulator performance in base station applications is the D/A converter, because the development of D/A converters does not keep up with the capabilities of digital signal processing with faster technologies [2]. In this design, the multi-bit D/A converter in [2] is replaced by the bandpass delta-sigma (∆Σ) modulator and 1-bit D/A converter. In addition, the sampling frequency fs is increased to 700MHz. As the 1-bit delta sigma (∆Σ) D/A converter has only two levels, any misplacement of the levels results only in gain error or offset. Neither of those are of great importance in many applications. The 1-bit ∆Σ-D/A converter is an all digital circuit, which has numerous advantages over analogue signal processing, such as flexibility, noise immunity, reliability and potential improvements in

performance and power consumption because of the scaling of the technology. In addition, the design, synthesis, layout and testing of digital systems can be highly automated. The DDS with 1-bit ∆Σ-D/A converter is attractive in digital transmitters, where it allows the output transistors to be operated in a power-efficient switching mode, and thus may result in an efficient power amplifier [3, 4, 5, 6].

2. Digital Quadrature Modulator Figure 3 shows the block diagram of the designed digital quadrature modulator. In order to produce a multi-carrier signal, the in-phase and quadrature-phase parts of the carriers from two complex modulators are summed in the quadrature modulator. After summing the carriers, the sampling rate is quadrupled using two half-band interpolation filters shown in Fig. 3. The passband of the first half-band filter restricts the maximum carrier frequency of the feeding complex modulators in Fig. 2 to be about two-fifths of the input sampling rate of the quadrature modulator. The last filter has an interpolation ratio of 4 and thus it is composed of four polyphase filters. After the quadrature modulation, the signal is converted into an analogue IF signal using a bandpass ∆Σ modulator and a 1-bit D/A converter. 2.1. Multiplier-free Quadrature Modulation The conventional quadrature modulator requires two multipliers and an adder [7]. When performing a quadrature modulation to the frequency fs /4, the output consists of interleaved X and Y samples, such that every other X and Y sample is negated (··· X(n), Y (n), −X(n), −Y (n) ···). This is achieved by arranging the outputs of the polyphase filters of the last interpolation filter appropriately using a 4:1 multiplexer and by negating the third and the fourth polyphase filter outputs as shown in Fig. 3 [8, 9]. These negations can be included in the coefficients of the third and fourth polyphase filters. The modulation to the frequency - fs /4 instead of fs /4 can be performed by negating the entire Y -branch (··· X(n), −Y (n), −X(n), Y (n) ··· ). The selection can be done independently for each of the orthogonal input carriers using the control signals CTR1 and CTR2 shown in Fig. 3. This functionality enables almost a doubled bandwidth. The quadrature modulation may be considered to represent a frequency up-shift of the passband of the interpolation filters to - fs /4 or fs /4. The combination of the filters provides more than 74dB image rejection (passband ripple of 0.004dB). 2.2. Bandpass ∆Σ modulator A block diagram of a digital fourth order bandpass ∆Σ modulator used in this design is shown in Fig. 4. Scaling factors have been added to the signal path to prevent overflows. The noise transfer function of the ∆Σ modulator produces a notch in the quantisation noise at the frequency of interest, i.e. fs /4. The sampling frequency of 700MHz is demanding for the successive adders in Fig. 4. Moreover, due to the feedback loops, it is not possible to pipeline the structure in a conventional manner. The inherent delay elements (D) of the ∆Σ modulator have been utilised to ensure the right timing of the feedback loops when pipelining the design [10]. The ∆Σ modulator pipelined using this technique is illustrated in Fig. 5. The critical path of the structure in Fig. 5 consists of only one inverter and two full adders (FAs), instead of an inverter and 13 full adders needed in a conventional structure.

3. 1-bit D/A converter Since the output of the 1 bit D/A converter is an analogue signal, it is susceptible to clock jitter, waveform fall/rise asymmetry and noise coupling. In the fully differential system used here, the D/A converter output rise and fall are inherently symmetric, so a simple non-return-to-zero output suffices [11]. The 1-bit D/A converter is a simple current steered differential pair with a current source as shown in Fig. 6. The latch and driver shown in Fig. 6 adjust the crossing

point of the control voltages and limit their amplitude at the gates of the current switches, so that that these transistors are never simultaneously off. This minimises the glitch energy at the output. The crossing point is set by the cross-coupled inverters, which generate differential output with different rise and fall times. A driver is inserted between the latch and the current switch to adjust further the crossing point of the differential outputs and to make the transitions smoother. The reduced voltage swing is achieved by increasing the negative power supply (Vbias ) of the driver output so that the feedthrough to the output is minimised. Disturbances connected to the external bias current (Ibias ) are filtered out on-chip with a simple one-pole low-pass filter. The 1-bit D/A converter in Fig. 6 does not need cascode current sources to enhance linearity as multi-bit D/A converters do. So it is suitable for low supply voltage operation.

4. Implementation The digital part of the quadrature modulator was synthesised from a VHDL description using a standard 0.13µm CMOS cell library. Multirate systems are efficiently implemented using a polyphase structure in which sampling rate conversion and filtering operations are combined. The last filter stage shown in Fig. 3 was implemented using pipelined carry-save architecture due to the high speed requirements. The taps of the folded transposed direct form FIR filters were realised with canonic signed digit (CSD) coefficients. The static timing check and pre-layout timing simulations were performed for the netlist and the chip layout was completed using place and route tools. Finally, based on the parasitic information extracted from the layout, the post-layout delays were back-annotated to ensure satisfactory chip timing. In order to reduce the ground bounce in the digital part and to minimise the coupling of the switching noise from the digital logic to the D/A converter output, on-chip decoupling capacitors (total capacitance of 260pF) are used.

5. Measurement results The digital part of the quadrature modulator was synthesised from a VHDL description using a standard 0.13µm CMOS cell library. Figure 7 shows the GSM signal at the 1-bit digital output. Figure 8 shows the GSM signal at the 1-bit D/A converter output, where the sampling and output frequencies are 700MHz and 175MHz, respectively. In Fig. 8 the GSM signal measured at the 1-bit D/A converter output fulfils the GSM spectrum mask requirements [12]. The spectral degradation at the analogue output (Fig. 8), is due to the clock jitter and non-ideal differential output. Figure 9 shows the WCDMA signal at the 1-bit D/A converter output, where the adjacent channel leakage power ratios (ACLR1,2 ) are 50.26dB and 40.27dB. Due to the ACLR specifications of 45/50dB [13], a bandpass filter is required to remove the remaining quantisation noise from the second adjacent channel.

6. Conclusions The first analogue IF mixer stage of a transmitter can be replaced with this digital quadrature modulator. The modulator interpolates orthogonal input carriers by 16 and performs digital quadrature modulation at carrier frequencies fs /4, −fs /4, (fs is the sampling frequency). After the quadrature modulation the signal is converted into an analogue IF signal using a bandpass ∆Σ modulator and a 1-bit D/A converter. The die area of the chip is 5.2mm2 (0.13µm CMOS technology). The typical power consumption of the chip is 139mW with a 1.5V supply voltage, when 700MHz clock frequency and 11.5mA D/A converter full-scale output current are used. The IC is in a 144-pin BGA package.

7. References [1] J. Vankka, J. Ketola, J. Sommarek, O. Väänänen, M. Kosunen and K. Halonen, “A GSM/EDGE/WCDMA Modulator with on-chip D/A Converter for Base Stations”, IEEE Trans. on Circuits and Systems Part II, Vol. 49, No 10, pp. 645-655, Oct. 2002. [2] J. Vankka, J. Sommarek, J. Ketola, I. Teikari, M. Kosunen and K. Halonen, "A Digital Quadrature Modulator with on-chip D/A Converter," IEEE J. Solid-State Circuits, Vol. 38, No. 10, pp. 1635-1642, Oct. 2003. [3] S. R. Norsworthy, R. Schreier, and G. C. Temes, “Delta-Sigma Data Converters, Theory, Design, and Simulation,” New York: IEEE Press, 1997. [4] A. Jayaraman et al., "Linear High Efficiency Microwave Power Amplifiers Using Bandpass Delta-Sigma Modulators,” IEEE Microwave and Guided Wave Letters, Vol. 8, No.3, pp. 1211-123, March 1998. [5] J. Keyzer et al., “Digital Generation of RF Signals for Wireless communications with Band-pass Delta-Sigma Modulation” IEEE Microwave Symp. Digest, Vol. 3, pp. 2127-2130, 2001. [6] M. Iwamoto et al., "Bandpass Delta-Sigma Class-S Amplifier,” Electronic Letters, Vol. 36, No. 12, pp. 1010-1012, June 2000. [7] J. Vankka, and K. Halonen, “Direct Digital Synthesizers: Theory, Design and Applications,” Kluwer Academic Publishers, 2001. [8] S. Darlington, “On Digital Single-Sideband Modulators,” IEEE Trans. Circuit Theory, Vol. 17, No.3, pp. 409-414, Aug. 1970. [9] B. C. Wong and H. Samueli, “A 200-MHz All-Digital QAM Modulator and Demodulator in 1.2µm CMOS for Digital Radio Applications,” IEEE J. Solid-State Circuits, Vol. 26, No. 12, pp. 1970-1979, Dec. 1991. [10] K. Falakshahi, C.-K. K. Yang, and B. A. Wooley, “A 14-bit 10-Msamples/s D/A Converter Using Multibit Σ∆ Modulation,” IEEE J. Solid-State Circuits, Vol. 34, No. 5, pp. 607-615, May 1999. [11] J. F. Jensen et al., “A 3.2-GHz Second-Order Delta-Sigma Modulator Implemented in InP HBT Technology,” IEEE J. Solid State Circuits, Vol. 30, No. 10, pp. 1119-1127, Oct. 1995. [12] GSM Recommendation 05.05: “Radio Transmission and Reception,” Dec. 1999. [13] 3rd Generation Partnership Project; Technical Specification Group Radio Access Networks; UTRA (BS) FDD; Radio transmission and Reception, 3G TS 25.104, V3.3.0, June 2000.

D IG IT A L M O D U L A T O R S

1 6

B P F

D A C

D A C B P F 1

L P F

B P F 2

P A

L O 2

L O 1

Fig. 1. The digital quadrature modulator replacing the first analogue IF mixer stage. I 1

Q I

1

2

Q

X

C o m p le x M o d u la to r

C o m p le x M o d u la to r 2

Y

1 1

Y

X

Q u a d ra tu re M o d u la to r 2

O

2

Fig. 2. Two complex modulators in series with the quadrature modulator. X 1

X

X 1 6 2

Y 1

N E G

Y

C T R 1 2

N E G

Y 1 6

C T R 2

fs/1 6

1 s t H a lfb a n d F ilte r (4 3 ta p s ) 1 s t H a lfb a n d F ilte r (4 3 ta p s )

1 6

1 6

fs/8

2 n d H a lfb a n d F ilte r (2 3 ta p s ) 2 n d H a lfb a n d F ilte r (2 3 ta p s )

h

1 6

4 k

8 ta p s h

4 k + 1

7 ta p s h

1 6 fs/4

4 k + 2

7 ta p s h

4 k + 3

7 ta p s

N E G

4 :1 M U X

f

1 2

å D M O D U L A T O R

s

f

N E G

fs/4 fs/2

Fig. 3. Digital quadrature modulator.

s

1

1 -B IT D /A C O N V E R T E R

f s

C h ip

F IL T E R

1 2 1

z 4 1

1

-2

-2

z 2 1

4

4

Fig. 4. 4th order bandpass ∆Σ-modulator.

D

D D

D

D

D

F A

D

F A

D

D

F A

D

F A

D D

D D

D

D

D

D

D

D

D

D D D

D

F A

D

D

F A

D D

D

F A D

D

F A

D

D

D

F A

D

D

F A

D

D D

F A

D

D

F A

D

D D

D

D

D

D

D

D

F A

D

D

F A

D

D

D

D

F A

D

D

F A

D

D D

D D

D

D D

D

D

D D

F A

D

D

F A

D

D D D

'1 '

F A D

D

D

D

D

D

D

F A D

D

D

D

D

D

D

'1 '

Fig. 5. Pipelined structure of 12-bit 4th order bandpass modulator.

L a tc h

V in

V D D

V D D

D riv e r

V D D V D D

V D D R

lo a d

V o u t

c lk

V o u t I

V

b ia s

V

R lo a d

b ia s

b ia s

Fig. 6. Schematic of the 1-bit D/A converter. P O W E R S P E C T R U M

-1 0 -2 0

M A G N IT U D E (d B )

-3 0 -4 0 -5 0 -6 0 -7 0 -8 0 -9 0 -1 0 0 -1 1 0 -1 2 0

1 7 3 .5

1 7 4

1 7 4 .5

1 7 5

1 7 5 .5

F R E Q U E N C Y (M H z )

1 7 6

1 7 6 .5

Fig. 7. Power spectrum of GSM signal at 1-bit digital output.

D e l t a

- 1 0

1

[ T 1 ]

R B W

3 0

k H z

R e f

L v l

0 . 0 0

d B

V B W

3 0

k H z

- 1 0

d B m

0 . 0 0 0 0 0 0 0 0

H z

S W T

L I M I T

C H E C K

:

5 0 0

R F

m s

A t t

0

U n i t

d B d B m

P A S S E D A

- 2 0

- 3 0

- 4 0 1 V I E W

1 A V

- 5 0

- 6 0

- 7 0

- 8 0

- 9 0 1

G S M _ S P E C

- 1 0 0

- 1 1 0

C e n t e r

D a t e :

1 7 5

M H z

3 6 0

3 0 . J U L . 2 0 0 3

k H z /

S p a n

3 . 6

M H z

1 5 : 1 2 : 1 6

Fig. 8. Spectrum of GSM signal at 1-bit D/A converter output.

R B W

3 0

k H z

R e f

L v l

- 4 1 . 0 1

d B m

V B W

3 0

k H z

- 1 0

d B m

1 7 5 . 3 5 0 7 0 1 4 0

M H z

S W T

5 0 0

M a r k e r

- 1 0

1

[ T 1 ]

m s [ T 1 ]

1

- 4 0

0

d B d B m

- 4 1 . 0 1

d B m

1 7 5 . 3 5 0 7 0 1 4 0

M H z

P W R

- 2 1 . 6 6

d B m

A C P

U p

A C P

C H

- 3 0

A t t

U n i t

1

- 2 0

R F

- 5 1 . 3 2

d B

L o w

- 5 0 . 2 6

d B

A L T 1

U p

- 4 1 . 5 4

d B

A L T 1

L o w

- 4 0 . 2 7

d B

1 V I E W

A

1 A V

- 5 0

- 6 0

- 7 0

- 8 0 c l 2

- 9 0

C 0

c l 2 c l 1

C 0

c l 1 c u 1

- 1 0 0

c u 1 c u 2

- 1 1 0 D a t e :

C e n t e r

1 7 5

M H z

3 0 . J U L . 2 0 0 3

5

M H z /

c u 2

S p a n

5 0

M H z

1 5 : 3 8 : 1 1

Fig. 9. Spectrum of WCDMA signal at 1-bit D/A converter output.