Junction Profile Engineering with a Novel Multiple Laser Spike Annealing Scheme for 45-nm Node High Performance and Low Leakage CMOS Technology T. Yamamoto, T. Kubo*, T. Sukegawa*, E. Takii*, Y. Shimamune, N. Tamura, T. Sakoda M. Nakamura, H. Ohta, T. Miyashita, H. Kurata, S. Satoh, M. Kase* and T. Sugii Fujitsu Laboratories Ltd. and *Fujitsu Ltd., 50 Fuchigami, Akiruno, Tokyo 197-0833, Japan e-mail:
[email protected], phone:+81-42-532-1253, fax:+81-42-532-2513
Abstract We developed novel junction profile engineering that uses a newly developed multiple laser spike annealing scheme and applied it to 45-nm node high performance and low leakage CMOS technology. This novel junction profile engineering is effective for the performance improvement of CMOS devices with embedded SiGe in the PMOS regions. Reduction of the source-drain parasitic resistance and the junction leakage current were achieved, thus improving the Ion of 33-nm CMOS devices (8.2% / 12.8% with an Ioff= 9 [nA/tm] for PMOS / NMOS). We also demonstrate that the fluorine co-implant plays a large role in reducing the PMOS source-drain extension (SDE) resistance. Introduction For scaling of high-performance CMOS technology to the 45-nm node and beyond, the power consumption issue becomes increasingly severe. Hence, supporting the multiVth library including the high-Vth transistors with low offstate leakage currents (
