Low-cost fabrication of nanoimprint templates with ...

Microelectronic Engineering 170 (2017) 34–38

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Low-cost fabrication of nanoimprint templates with tunable feature sizes at a constant pitch Shuhao Si ⁎, Lars Dittrich, Martin Hoffmann Technische Universität Ilmenau, IMN MacroNano®, Micromechanical Systems Group, Ilmenau, Germany

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Article history: Received 15 September 2016 Received in revised form 18 November 2016 Accepted 22 December 2016 Available online 24 December 2016 Keywords: Soft UV nanoimprint lithography NIL Nanofabrication Template Cryogenic dry etching Tunable feature sizes Low cost RIE ICP

a b s t r a c t Nanoimprint lithography (NIL) templates are in general costly, especially for large area and small feature sizes. With a simple shrinking technique using a serial of well-known technologies, it has been feasibly realized to produce high-quality soft NIL templates with widely tunable feature sizes at a constant pitch from a single master at very low-cost and in a short processing cycle. The master featuring at sub-micron range has been replicated to new silicon NIL templates with feature sizes at, but not limited to, sub-200 nm. soft UV-NIL combined with a dry etch process, were employed to fabricate an intermediate template of nanocone patterns that is further used for an imprint on the final substrate. The feature size of the SiO2 etch mask on the final substrate can be adjusted by varying the duration of mask formation etching. The final patterning of the template is realized by cryogenic etching based on SF6/O2 chemistry. Silicon NIL templates featuring nanopillar patterns with diameters of 150 nm, 200 nm and 250 nm, respectively, have been fabricated on wafer level from the same master with 450 nm feature size. The presented process flow avoids the time-consuming and cost-intensive electron beam writings and gives more flexibility in the fabrication of nanopatterns. The fabrication cycle for such NIL working templates with tunable feature sizes is maintained short and at a low cost. Moreover, the technique allows the fabrication of wafer level products at a constant pitch, which is of importance as well for the stacked large-area imprintings with varying feature sizes. © 2016 Elsevier B.V. All rights reserved.

1. Motivation and overview Nanoimprint lithography (NIL) has changed people's perception: a rather “mechanical” technique is employed for nanoscale patterning, and it caused a paradigm shift in nanolithography [1]. Utilizing a soft stamp following a lithographic scheme, the soft UV-NIL development has evolved from chip level [2] via wafer level patterning up to 300 mm substrates [3], to even ultra large patterning for meters by rolling schemes [4]. When employing soft UV-NIL, it is generally necessary to start with a master, either for replications of working soft stamps or for duplications of the template in the form of Nickel and such. The master is commonly fabricated by electron beam lithography (EBL) which is, however, costly, time-consuming and can hardly offer reasonable throughput at sufficiently high resolution [5]. Therefore, the working stamps are usually replicas from the master, nowadays in general as soft stamps replicated in PDMS or other suitable polymers. A fast and low-cost approach to fabricate wafer-level silicon templates with tunable feature sizes for positive patterns is presented in this paper. A master featuring periodic circular pillar patterns fabricated by EBL serves as a starting point for the reproduction with tunable ⁎ Corresponding author. E-mail address: [email protected] (S. Si).

http://dx.doi.org/10.1016/j.mee.2016.12.023 0167-9317/© 2016 Elsevier B.V. All rights reserved.

feature sizes. A two-step replication process is designed where the master is replicated into a cone-like patterned intermediate template and the intermediate template is employed for numerous replications of NIL template with tunable pillar diameters. The fabrication procedure incorporates only soft UV-NIL and subsequent dry etch processes. The processes involve no further electron beam writing for patterning, which therefore leads to a low cost and fast acquisition of NIL templates. The feature size (and shape) of the new set of templates can be effortlessly adjusted during the respective etch process, which was one of the key motivations of this work. Moreover, the process is designed also based on the fact that, for certain applications, it is critical to imprint varying feature sizes at identical pitch on the same substrate at different stages of fabrications. In 1D surfaces, such as applications of graded index photonic crystals or anodic aluminum oxide membranes, the radius of the patterns is in graded or stepped manner whereas the pitch size is maintained [6,7]. In multistack alignment, the pitches of the multiple layers are commonly kept constant while within each layer the feature size can vary if necessarily designed [8]. Therefore, the template series generated from one and the same master is of great importance to avoid variations in pitch or device alignment. The theoretical methodology of the fabrications is demonstrated in next section and the corresponding experimental results will follow.

S. Si et al. / Microelectronic Engineering 170 (2017) 34–38

2. Methodology A schematic process flow of the template fabrication is depicted in Table 1. A master is fabricated by EBL and its surface is coated with an anti-sticking layer (Step A). A soft stamp made of UV-curable PDMS is replicated from the master (Step B) and used for the first imprinting (Step C). An intermediate silicon template featuring cone patterns is etched (Step D) and applied for further soft stamp replications (Step E). A silicon substrate featuring a hard mask layer is imprinted using the soft stamp, thus transferring the cone patterns in the UV-NIL resist (Step F). The feature size of the final template is determined by the diameters of the etch mask, respectively. By exposing the substrate to variable etch durations, the hard mask is opened according to the slope of the cone pattern (Steps G-1/G-2/G-3 for comparison). Taking the resulting non-vertical profile of the hard mask into account, cryogenic silicon etching based on SF6/O2 chemistry is employed to etch the silicon substrate. It offers a fast etching of silicon with smooth and vertical sidewalls at high selectivity with respect to the mask. Afterwards the mask is completely removed (Steps H-1/H-2/H-3). The detailed process parameters and materials used are explained in the subsequent section. 3. Results and discussion A nanopillar array of 5 cm × 5 cm centered on a 150 mm silicon wafer is used as the master. The nanopillars have a diameter of 450 nm at a pitch of 1000 nm and a height of 700 nm. Scanning electron microscope (SEM) images of the master are displayed in Fig. 1a (cf. Step A). A monolayer of Perfluorodecyltrichlorosilane (FDTS) was deposited onto the surface of the master due to its excellent anti-sticking properties in vapor phase at 165 °C within 2 h. The soft UV-NIL system (GD-N03, GDnano Ltd.) employs a center-to-edge stamp bowing scheme [5, 12] for imprinting on the 100 mm silicon wafer with a low back pressure below 0.5 kPa. A bi-layer soft stamp is established for imprinting. The stamp consists of a 2 mm thick PDMS carrier and a 500 μm feature layer made of UV-PDMS (Shin-Etsu). The UV-PDMS features a 0.02% shrinkage enabling a high replication fidelity of the master patterns [13]. The PDMS carrier was produced at a mixing ratio of 10:1 (base:curing agent) by weight and cured separately in advance. The UV-PDMS, which is originally served as two component product, was mixed at a ratio of 1:1 (base:curing agent) and dispensed on the FDTS-treated master. The UV-PDMS was co-cured on the PDMS carrier by UV exposure at 365 nm at a dose of at least 2000 mJ cm− 2 and post-cured for 3 h at room temperature before peeling off from the master to reach the required physical properties (Fig. 1b). The resist used for the first imprinting of intermediate template is AMONIL MMS4 (AMO GmbH). It is non-sensitive to oxygen and PDMS-compatible, thus meeting the requirement of nanoimprint lithography in ambient atmosphere. The resist was spin-coated at 4000 rpm for 1 min, resulting in a height of approximate 700 nm and a residual layer thickness of less than 50 nm. The imprinted wafer is shown in Fig. 2a. The residual layer is descummed by means of reactive ion etching (RIE) utilizing a gas combination of CHF3 and Ar afterwards (cf. Step C). Employing the patterned resist as mask, the silicon substrate is undercut into cone-like structures by plasma etching in SF6 and O2. The etched patterns are shown in Fig. 2b (cf. Step D). The PDMS/UV-PDMS bi-layer soft stamp was then replicated from the intermediate silicon template which has been coated with FDTS as well. The dimension, i.e. the volume, of the cone patterns decreases compared to the pillar patterns. Therefore, the coating thickness of the resist is preferably reduced in order to achieve a possibly thin residual layer after the imprinting. The AMONIL was diluted by Isopropoxyethanol at a ratio of 1:1 by weight owing to its lower evaporation rate in comparison to that of ethanol. The silicon substrates as for the final NIL templates are thermally oxidized for 50 nm SiO2 layer as hard etch mask. On one hand, resist faces high risks of cracking at cryogenic temperature which is

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Table 1 Schematic process flow of the template fabrication with tunable feature sizes for nanopillar patterns.

Application–oriented processes, e.g. direct thermal imprinting, working polymer

Master

Step

3D–view

Intermediate template

Top view

Working template

Side view

Soft stamp replications and metal stamp electroplating, etc. Description

A

NIL master fabricated by EBL. Surface treatment with FDTS (anti–sticking layer).

B

Soft stamp replication from the master. Stamp consisting of PDMS carrier and UV–PDMS feature layer.

C

First imprinting and descumming of the residual resist layer.

D

Dry etching of nanocone pattern on the intermediate template.

E

PDMS/UV–PDMS soft stamp replicated from the intermediate template.

F

Second imprinting on the silicon subtrate featuring a hard silicon dioxide mask on top.

G–1

Residual resist descumming and hard mask etching (short duration).

H–1

Cryogenic silicon etching for the final NILworking template (mask removed). Short mask etch duration = large pillar diameter.

G–2

Residual resist descumming and hard mask etching (medium duration).

H–2

Cryogenic silicon etching for the final NIL working template (mask removed). Medium mask etch duration = medium pillar diameter.

G–3

Residual resist descumming and hard mask etching (long duration).

H–3

Cryogenic silicon etching for the final NIL working template (mask removed). Long mask etch duration = small pillar diameter.

Master

Intermediate template

Template

Resist

Mask

Soft stamp

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Fig. 1. (a) SEM image of the master and (b) an example of the bi-layer PDMS/UV-PDMS soft stamp.

Fig. 2. (a) Imprinting on 100 mm intermediate substrate; (b) SEM image of nanocone pattern etched intermediate template; (c) SEM image of imprinted final substrate.

required for the final patterning. On the other hand, the oxygen content in the etching plasma leads to uncontrolled erosion of the AMONIL mask [9]. Therefore, an intermediate SiO2 hard mask is preferably used to keep the fidelity of patterned surfaces. The substrate is coated with the diluted AMONIL at 4000 rpm for imprinting. The residual layer thickness is below 20 nm after the imprinting, and the SEM image is shown in Fig. 2c (cf. Step F). A gas combination of CHF3 and Ar which is suitable to etch both AMONIL and SiO2 is used to descum the residual layer and open the hard mask at the same time. Due to the resulting slope of the cone patterns in the resist, the diameter of the mask can be reduced to different sizes by adapting the etch durations (cf. Steps G-1/G-2/G-3). As shown in Fig. 3, the diameter of the SiO2 mask was narrowed to 250 nm, 200 nm and 150 nm (measured at the bottom of the mask), respectively, without removing the residual resist on top. The slopes of the cone patterns in the resist result in non-vertical sidewalls of the SiO2 mask. The etch selectivity between silicon and SiO2 is generally constrained below 35 in continuous fluorine-based etching chemistry at room temperature and high inductively coupled power up to 1400 W [10]. As a result, the SiO2 mask would be etched away especially at the edges during the silicon etching. It would cause uncontrollable feature size shrinkage and non-vertical sidewalls of the etched silicon.

Much higher selectivity of silicon vs. SiO2 can be achieved in a cryogenic etch process using SF6/O2 chemistry. The electrode is cooled down to − 120 °C utilizing liquid nitrogen. The low temperature greatly inhibits radicals chemically reacting with the SiO2 mask. Moreover, the higher condensation of etch by-products consisting of silicon oxide/ fluoride (SiOxFy) facilitates the protection of the sidewalls from attacking. An ICP (Oxford PlasmaPro 100 Cobra) has been used throughout the etching of the final templates. The flow rates of SF6 and O2 are kept at 38 sccm and 12 sccm, respectively. The wafer is placed on the electrode prior to etch for 5 min to level the temperature to −120 °C. The bottom electrode is set to 5 W at 13.56 MHz resulting in a DC bias voltage between 15 V to 18 V. The ICP power is set to 500 W, and the chamber pressure is kept at 6 mTorr. Helium backing is activated for enhanced thermal contact. The SEM images of etched wafers for NIL templates are shown in Fig. 4. The residuals of resist as well as mask were removed completely by hydrofluoric acid. The wafer is etched for 15 s at such conditions resulting in a structure depth of approximately 300 nm. The erosion of the SiO2 mask caused by free fluorine radicals decreases dramatically at −120 °C due to its high temperature sensitivity. The selectivity between silicon and SiO2 can be raised to over 750:1 when the DC bias voltage is limited to

Fig. 3. Etching of the SiO2 mask to the feature sizes of (a) 250 nm; (b) 200 nm; (c) 150 nm, without removing the residuals of resist.


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Fig. 4. SEM images of the tilted views (1 & 2), cross-section view (3) and the top view (4) of the etched NIL templates with feature sizes of (a) 250 nm, (b) 200 nm and (c) 150 nm.

below 20 V [11] which corresponds to the presented etch results. The diameters of the etched pillars were directly measured by the SEM software and turned out to be approximate 250 nm, 200 nm and 150 nm, respectively. The feature size was maintained from the mask whereas no shrinkage was observed during the etch process. Smooth sidewalls have been obtained, and the surface of the template was kept clean since there is no polymer condensation in the SF6/O2 cryogenic chemistry using the mentioned etch conditions. The angle between the etched pillar sidewalls and the bottom substrate reaches nearly 90°. Thus, no complications are expected for future working soft stamp replications such as cavity filling and detaching.

4. Conclusion A technology for a fabrication of NIL templates with a wide range of tunable feature sizes and at an identical pitch from a single master is presented. It involves a serial of well-known technologies, such as soft UV-NIL and dry etching processes, to allow its realization with high reproducibility, at very low cost, and in a short processing cycle. An intermediate nanocone template was produced based on an EBL written master using soft UV-NIL and a subsequent SF6/O2 reactive ion etch process. The nanocone pattern was transferred into the resist on the final substrate, and the mask was used to tune the feature size owing to the sloping sidewalls of the nanocone pattern. Cryogenic silicon etching using SF6/O2 chemistry was employed for the NIL template patterning. The appropriate combination of SF6 and O2 as well as low pressure and temperature facilitate the silicon etch with vertical and smooth sidewalls without uncontrolled feature size changes compared to the mask. The generation of such new NIL templates requires a single master. It avoids the costly EBL and involves multiple large area soft UV-NIL and short dry etching processes in the realization of the final patterning. The feature size can be tuned simply by changing the duration of the

mask etch process, and final etching of the template completes within seconds. Therefore, the processing cycle is kept simple and the costs are maintained low which contributes to greater potential for large area nanopatterning.

Acknowledgement The processing of NIL-related technologies such as soft stamp investigation and plasma etching techniques has been supported by the Institute of Micro- and Nanotechnologies MacroNano®. Special thanks to Mrs. Birgitt Hartmann, Mrs. Jutta Uziel and Mrs. Manuela Breiter for technological supports. Further appreciations are given to the 5microns GmbH for providing support on the NIL system and process as well as for providing consumables and materials. References [1] S.Y. Chou, Foreword, Appl. Phys. A 121 (2015) 317–318. [2] M. Bender, U. Plachetka, J. Ran, A. Fuchs, B. Vratzov, H. Kurz, T. Glinsner, F. Lindner, High resolution lithography with PDMS molds, J. Vac. Sci. Technol. B 22 (6) (2004). [3] X. Thrun, K. Choi, M. Freitag, M. Gutsch, C. Hohle, J. Paul, M. Rudolph, K. Steidel, 15 days electron beam exposure for manufacturing of large area silicon based NIL master, Microelectron. Eng. 110 (2013) 119–122. [4] Soken Chemical & Engineering, Stampkind product brochure, https://www.sokence.co.jp/en/product/nano_imprint. [5] H. Schift, Nanoimprint lithography: an old story in modern times? A review, J. Vac. Sci. Technol. B 26 (2) (2008) 458–480. [6] Q. Zhu, L. Jin, Y. Fu, Graded index photonic crystals: a review, Ann. Phys. (Berlin) 527 (3–4) (2015) 205–218. [7] L.Y. Wen, Z.J. Wang, Y. Mi, R. Xu, S.H. Yu, Y. Lei, Designing heterogeneous 1D nanostructure arrays based on AAO templates for energy applications, Small 11 (2015) 3408–3428. [8] M. Mühlberger, I. Bergmair, W. Schwinger, M. Gmainer, R. Schöftner, T. Glinsner, C. Hasenfuß, K. Hingerl, M. Vogler, H. Schmidt, E.B. Kley, A Moiré method for high accuracy alignment in nanoimprint lithography, Microelectron. Eng. 84 (2007) 925–927. [9] AMONIL Product Fact Sheet, https://www.amo.de/wp-content/uploads/2015/03/ FactSheet_AMONIL.pdf (accessed on 13.Sep., 2016).

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