Paul McCloskeya, Ray Foleyb, Virginia Morrisa, Nicolás Corderoa, Alan
Mathewsona, Cian Ó Mathúnaa ... Motivation. Next generation power supplies
must be.
Low Parasitic Packaging of Power Modules for High Frequency Operation Paul McCloskeya, Ray Foleyb, Virginia Morrisa, Nicolás Corderoa, Alan Mathewsona, Cian Ó Mathúnaa
µ0Ms(T)
aTyndall bDepartment
National Institute,Lee Maltings, Prospect Row, Cork. of Electrical Engineering, University College Cork, College Road, Cork..
Motivation
Next generation power supplies must be
SMPS switching at higher frequencies
Smaller
Reduces size of passive components required
More efficient
Helps miniaturisation
Cheaper
Parasitic inductance has much greater impact on performance
Manufacturable as “system in a package”
Hence packaging needs to be better
Integrated Power Trains - State of the Art NXP PIP212-12M
Renesas R2J20601NP
Fairchild FDMF8704V
ON Semi NIS3001A
Vout
0.8V to 6V
1.0V to 5V
0.8 to 3.2V
0.7V to 5.1V
Vin Iout max Operating Frequency Package size (Power Train) Included
3.3V to 16V 35A Up to 1MHz. 8mm x 8mm x 0.85mm 2 Mosfetts,1 Schottky, 1 driver L, C, Controller
Up to 16V 35A >1MHz possible 8.1mm x 8.1mm x 0.8mm 2 Mosfetts,1 Schottky, 1 driver L, C, Controller
7 to 20V 32A Up to 1MHz. 8mm x 8mm x 0.8mm 2 Mosfetts,1 Schottky, 1 driver L, C, Controller
7V to 14V 31A Up to 1MHz 10.5 mm x 10.5mm x 2.0mm 2 Mosfetts,1 Schottky, 1 driver L, C, Controller
Model
Required
NXP PIP212-12M
Renesas SiP
CASE 500 PinPAK On Semi
Wafer Level Module Packaging Cu interconnect Thick photo-resist Embedded die
Fabrication Steps
Advantages
Embedded FET
Cu interconnect 207 µm
Novel thick photoresist developed
Deposit release layer
Batch processing
Create pads and bottom side interconnect
Uses modified commercial materials
Thick plated copper interconnect
Patterning of thick layers achievable
Mount die required for module
Good feature size capability
Repeatable release process
Embed die in thick photoresist
Repeatable release process
Fabricate top side interconnect Fabricate top cover Release from temporary substrate
Reduced shrinkage
Horizontal Interconnect
Vertical Vias Max Via Length
Min Via Ø
Min Via Spacing
Min Width
Min Spacing
500 µm
200 µm
200 µm
50 µm
50 µm
Process optimisation Closed 300 micron via and partly closed large structure
Close up of 300 micron via
Electrical Modelling
Power Loss; Iout=16A L=7.7nH f=307kHz
,
1.5MHz
and
3MHz
4.50E+00
3.00E+00 2.50E+00 2.00E+00 1.50E+00
Theoretical
1.00E+00
Measured
Discrete Components Parasitic L = 7.7 nH 85
Driver SiP41101
Wire Loss
Inductor Loss
Pon
f=307kHz
Lower MOSFET Si7336ADP
Commercial Integrated, Freq=1.55MHz
High side FET wirebonds
80 Efficiency/%
Poff
Gate Drive Upper
Current/A
f=3MHz
Gate Drive Lower
Inductor
30
Ringing Turn Off
25
Loss
20
Turn On
15
Body Diode Conduction
10
Upp MOS Cond Loss
5
Low MOS Cond Loss
5.00E-01 0.00E+00
0
Analytic Model developed to predict converter efficiency Calculates losses at each part of the converter waveform Inputs • FET performance parameters • Rds Î MOS Conduction loss • Qrr, Coss Î Reverse recovery & ringing turn-on loss • Cgd, Cds Î Ringing turn-off loss • Vf, tdeadtime Î Body diode Conduction losses • Qg-q, Vdrv-q Î Gate drive losses Packaging •Parasitic L Î Pon and Poff loss
3.50E+00
Rev Recovery& Ringing
Buck Converter with parasitic inductance; Ld1, Ld2, Ls1, Ls2
70 65 60 55 50 45 40 35 30
Upper MOSFET Controller ISL6561CR Si4682
4.00E+00 Power Loss/W
Efficiency/%
Discrete Components, Freq=1.923MHz
75 70 65 60
Measured
55 50
Modelled
Inductor
45 40 0
10
20 Current/A
30
40
Commercial Integrated Power Train
Controller ISL6561CR
Low side FET
Driver
Commercial Power Train Loop inductance = 1.4 nH
Optimised Design
2% HF efficiency improvement vs. commercial 50% reduction in size
Modelled Efficiency, Freq=1.55MHz
85 80
Efficiency/%
Build Up Power Train (Optimised layout) Loop Inductance = 0.6 nH
75 70
Commercial Build Up
65 60 55 50 45 40 0
www.tyndall.ie
10
20
Current/A
30
40
