MD4.2 (Invited) 16.00 – 16.30
Low power silicon photonic transceivers Xuezhe Zheng, John E. Cunningham, Ron Ho1, Jon Lexau1, Guoliang Li, Ying Luo, Hiren Thacker, Jin Yao, Frankie Liu1, Dinesh Patil1 , Philip Amberg1, Nathaniel Pinckney1, Po Dong2, Dazeng Feng2, Mehdi Asghari2, Attila Mekis3, Thierry Pinguet3, Kannan Raj, and Ashok V. Krishnamoorthy
1
Sun Labs, Oracle, San Diego CA 92121 Sun Labs, Oracle, Menlo Park, CA 94025 2 Kotura Inc., Monterey Park, CA 91754 3 Luxtera Inc., Carlsbad, CA 92011
[email protected]
Abstract: We present ultra low power silicon photonic transceivers, including a 320fJ/bit reverse biased ring modulator integrated with CMOS driver, and a 690fJ/bit record-low power receiver with sensitivity of -18.9dBm at 5Gbps for bit-error-rate of 10-12. Scaling of high performance, many-core, computing systems calls for disruptive solutions to provide ultra energy efficient and high bandwidth density interconnects at very low cost. Silicon photonics is viewed as a promising solution owing to its potential advantages of low latency, high bandwidth, high density, and low power consumption. For photonic solution to prevail in intra/inter-chip applications, the communication link power consumption, including all the electronic circuits, has to be aggressively scaled down from currently ~10 pJ/bit to ~100 fJ/bit in the near future, which demands for not only innovative optical devices and system architectures [1], but also novel circuit designs and integration techniques. Key components to enable low power dense silicon photonic interconnects are high speed, energy efficient transceivers. In recent years, substantial progress has been made in developing high-speed waveguide silicon modulators and photo detectors [2-5] , but lagged behind in development of low power driver circuits and low parasitic integrations. To advance the technology for practical applications, we developed novel microsolder bump based hybrid integration technique[1] to enable best-of-the-breed performance for both the photonic devices and the VLSI circuits. A reverse biased ring modulator was designed and optimized for low drive voltage, low capacitance and high speed[6]. We maximized the effective index change by optimizing both the ring waveguide, and pn junction design. The waveguide was designed to have a width of 0.5 μm, a height of 0.25μm and a slab height of 50 nm to enable very tight mode confinement. An asymmetric pn junction with a 5x1017 cm−3 p doping concentration, a 1x1018 cm−3 n doping concentration, and a junction offset of 50 nm to maximize the mode overlap with the depletion region for maximized index change. As a result, we obtained a compact ring modulator with high modulation bandwidth sufficient for 15Gbps modulation, very small capacitance of ~15fF, low voltage swing of 2V, high extinction ratio (~7dB) and low optical loss (~2dB at on-state). Ge-PIN waveguide diodes were designed for high speed and high responsivity[7] . They were fabricated with Luxtera’s Ge-enabled optoelectronic process integrated in Freescale's HIP7_SOI 130 nm CMOS. High responsivity of >0.7 A/W at 1550 nm, low dark current of 3 μA at 25°C and 0.5 V reverse bias, low capacitance of less than 20 fF, and -3 dB bandwidth exceeding 10 GHz were achieved. Based on the electrical characteristics of the ring modulator and Ge photo detector, we designed low power driver and receiver circuits[8]. A simple cascode circuit was used to drive the capacitive depletion ring modulator, where each transistor only sees voltage less than 1V while the whole circuit issues an effective swing of up to 2V across the device. We used a low power receiver design with a 3stage TIA, followed by a sense amplifier. The 3-stage TIA gives a total gain of about 10k, giving a 100 mV output voltage for a 10 μA input signal. A simple and power-efficient clocked sense amplifier then subsequently amplifies the TIA output to a full-swing CMOS signal. Special low-overhead bias refresh scheme was developed to set proper decision threshold for the receiver without requiring DC balanced data. The driver and receiver chip was fabricated using TSMC 90nm CMOS process. Low parasitic integration was achieved using micro solder bonding technique. Both VLSI and photonic chips were first processed to add under-bump-metallization (UBM) to the bonding pads using
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electroless plating. Low profile and small footprint microsolder bumps were then added to the pads on the modulator chip with a few microns of vertical compliance. The two post-processed chips were then flipchip bonded together by thermo-compression. The microsolder connections were measured to have
