P105: Failure Analysis of operational amplifier due to ESD Stress in Complementary Bipolar Process F. Liu, L. Liu, L. He, Y. Wang Sichuan Institute of Solid-state Circuits, China; University of Electronic Science and Technology of China, China P106: An Analytical Solution to the Grain Boundary Barrier Height in Undoped Polysilicon Thin-Film Transistors Z. Gong, M. Wang Soochow University, China P107: Failure Analysis of Gate-all-around Nanowire Field Effect Transistor under TLP Test G.Y Zhang, A.H Dong, N. Liu, R. Tian, X. Yang, Z. Liu, K. Lee, H.-C. Lin, J. J. Liou, Y. Wang University of Electronics Science and Technology of China, China; National Chiao Tung University, Taiwan; University of Central Florida, USA; Science and Technology on Analog Integrated Circuit Laboratory, China P108: Improving the Accuracy of Module Based Thermal Modeling H. Wang, M. Zhang, C. Zhang, H. Tang, X. Wang University of Electronic Science and Technology of China, China; Xi’an Jiaotong University, China P109: Early Effect Exposing Performance of 28nm HK/MG pMOSFETs under PDA or DPN Nitridation Treatment M.C. Wang, P.K. Chen, W.D. Lee, Y.H. Yu, S.J. Wang, F. Hsu, O. Cheng, L.S. Huang Minghsin University of Science and Technology, Taiwan; Lee-Ming Institute of Technology, Taiwan; National Taipei University of Technology, Taiwan; United Microelectronics Corporation, Taiwan P110: Development of Low Temperature Amorphous Tin-doped Indium Oxide Thin-Film Transistors Technology Y. Liu, L. Wang, S. Zhang Peking University Shenzhen Graduate School, China P111: A New Model of Low-Frequency Noise in Polycrystalline Silicon Thin-Film Transistors M. Wang, M. Wang Soochow University, China P112: Analysis of 2-TFTs AMOLED Pixel Circuit Based on an On-Current Model of Poly-Si TFTs J. Zhou, M. Wang, D. Zhang, M. Tang Soochow University, China
Early Effect Exposing Performance of 28nm HK/MG pMOSFETs under PDA or DPN Nitridation Treatment Mu-Chun Wang1, Po-Kai Chen1, Win-Der Lee2, Yi-Hong Yu1, Shea-Jue Wang3,a, Fang Hsu1,b,Osbert Cheng4, LS Huang5 1
Dept. of Electronic Engineering, Minghsin University of Science and Technology, Hsinchu, Taiwan 2 Department of Electrical Engineering, Lee-Ming Institute of Technology, Taipei, Taiwan 3 Dept. of Materials and Resources Engineering, National Taipei University of Technology, Taipei, Taiwan 4 ATD Device Division, United Microelectronics Corporation, Hsinchu, Taiwan 5 Reliability Dept./ATD Device Division, United Microelectronics Corporation, Hsinchu, Taiwan *Corresponding emails: a
[email protected]; b
[email protected] Abstract—Incorporating a high-k dielectric and metal gate engineering at deep-nano node process is a trend to promote the drive current of MOSFET devices. Nevertheless lots of challenges crowdedly reveal either process technologies or device model establishment. To reduce the gate leakage and enhance the device reliability, the nitridation process after high-k deposition will be utilized, but causing the difficulty in device model construction. One of the issues is Early effect which is not intersected at one point. The vertical field in gate node hugely contributes its influence in the entire electrical field in device operation. Keywords—DPN; PDA ; Early voltage; high-k; metal gate.
I. INTRODUCTION Device models bridging process technologies and IC design propose a predominant role in the performance of IC products. With the need in commercial electronic marketing, the feature size of MOSFETs in shrinkage view is a sustaining trend even though the semiconductor technology enters the nano-node level. Because of this trend, the density of devices in IC and the IC processing speed are raised up obviously. Additionally, narrowing down the channel length L or reducing the thickness of gate dielectric T d to increase the drive saturation current is a feasible way. One of the cardinal factors to reform the drive current is to use the high-k material [1] as gate dielectric, especially based on hafnium or zirconium oxide to replace the conventional gate silicon oxide or oxy-nitride. II. DEVICE FABRICATION A simple process flow is introduced below. After wafer cleaning, an interfacial layer (IL) and a thin film of high-k gate dielectric with HfOx/ZrOy/HfOx (HZH) were deposited. A nitridation with post deposition annealing (PDA) [2] using NH3 gas and 700oC annealing or low-pressure decoupled plasma nitridation (DPN) [3] process adopting nitrogen gas and 700oC annealing is to repair the oxygen vacancy in high-k layer. Continuously, a barrier metal and dummy poly-gate were deposited in sequence. Using lithography technology is to define the desired patterns. Adopting ion implantation skill is to form lightly-doped drain and source/drain zones. Self-align silicide process and contact-etch-stop-layer (CESL) process were followed. After that, the dummy poly-gate was removed and the deposition of work function (WF) adjustment for n-channel or p-channel MOSFET devices labeled NWFM and PWFM, respectively. Furthermore, Al barrier metal was deposited before gate trench filling with Al low-resistance metal. In the end, proceeding gate trench planarization via
metal polish, contact loop and backend-of-line (BEOL) process were followed. The schematic device profile is shown in Fig. 1 and the simple process flow is represented in Fig. 2. III. RESULTS AND DISCUSSION In this study, the chief test devices for p-channel MOSFETs (pMOSFETs) include W/L=1/1, 1/0.2 and 1/0.03 (μm/μm). According to the formula of drive current in saturation mode [4] with short-channel effect [5,6], it is given as
I DS
W C ox (VGS VT ) 2 (1 VDS ) 2L
(1)
where : channel mobility, Cox: gate capacitance, VT: threshold voltage, : channel length modulation factor = 1/VA: VA: early voltage. When the device channel is until quarter-micron node, this Early effect is gradually distinct. Additionally, as the gate thickness is decreased more, the influence of vertical field contributing to this effect is also strengthened. Therefore the last term (1+VDS) must be modified as (1+VDS + (VGS-VT)) or more complicated revise term, where is a factor related to gate bias. In Fig. 3-5, we observe the Early voltage is not constant no matter what the channel length is. The extracted |VA| values are listed at Table 1 and 2 for PDA and DPN treatment, respectively. Considering the order, the curves of |VA| vs. (VGS-VT) with DPN treatment show more regular distribution than those with PDA treatment. It means the device model construction with DPN process is easier to be achieved confidently due to the ordinary trajectory, as shown in Fig. 6. IV. CONCLUSIONS Device model establishment in nano-node era is indeed more difficult. Due to high-k dielectric is beneficial to enhance the drive current at the nano-node process. This deposition is necessary recently. Adopting a PDA or DPN nitridation treatment is a good choice to minimize the oxygen vacancy in high-k layer. However, different nitridation processes usually demonstrate the various behaviors of drive current related to gate bias. Thus the model construction is obviously tougher than before. The distribution of Early voltage is not simple, just influenced by horizontal filed, but partially impacted by vertical field. This viewpoint is very important in the future to build up a more accurate model to
Fig. 4 Early effect as W/L= 1μ m /0.2μm with (a) PDA and (b)DPN processes.
IC designers. [1] [2] [3] [4]
C.H. Tsai , et al., IEEE VLSI-TSA, pp.1-2, Apr. 2012. M.S. Akbar, et al., APL, vol.82, no.11, pp. 1757 – 1759, 2003. R.L. Radin, et al., IEEE ISCAS, pp.1720-1723, May 2008. B. G. Streetman, et al.: Solid State Electronic Devices, 6th Ed., Prentice Hall, 2006. [5] Q. Xie , et al., IEEE TED, vol.59, no.6, pp.1569-1579, June 2012. [6] S. Ohmi , et al., IEEE ISSM , pp.1,4, 15-17, Oct. 2007.
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(a) (b) Fig. 5 Early effect as W/L= 1m /0.03m with (a) PDA and (b) DPN processes Table 1. Early voltage (V) extracted under PDA treatment.
Fig. 1 Cross-sectional profile of a HK/MG pMOSFET
Table 2. Early voltage (V) extracted under DPN treatment.
Fig. 2 Simple process flow for 28nm gate-last MOSFET devices.
(a) (b) Fig. 3 Early effect as W/L= 1m /1m with (a) PDA and (b) DPN processes.
Fig.6 Distribution of Early voltage vs. VGS-VT with PDA and DPN nitridation treatment.
(a)
(b)
