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Department of Information Technology, Bengal Engineering & Science University, Shibpur, Howrah-711103, India. Email: [email protected], ...
2013 International Conference on Electrical Information and Communication Technology (EICT)

Modeling of Crosstalk Induced Effects in Nanoscale Copper Interconnects Manodipan Sahoo and Hafizur Rahaman Department of Information Technology, Bengal Engineering & Science University, Shibpur, Howrah-711103, India Email: [email protected], rahaman [email protected] Abstract—Due to continued scaling of feature sizes, signal integrity and performance of today’s copper based nanoscale interconnects are severely impacted. In this work, an ABCD parameter based model is presented for fast and accurate estimation of crosstalk delay and noise for identically coupled copper based nano-interconnect systems. Using the proposed analytical model, the crosstalk delay and noise are estimated in copper based nanointerconnects for intermediate and global interconnects at the future Integrated circuit technology nodes of 21 nm and 15 nm respectively. The proposed model has been compared with SPICE and it is found that both the crosstalk delay and noise model are almost 100% accurate as SPICE and in an average ∼22 times and ∼40 times faster than SPICE respectively. Keywords—signal integrity , nanoscale , ABCD parameter , crosstalk , delay , noise , nano-interconnects , SPICE.

FDTD (Finite Difference Time Domain) method [12]. In this work, we have used the concept of ABCD parameter matrix to accurately model the crosstalk delay and noise of three identically coupled copper interconnects for intermediate and global interconnects at the integrated circuit technology nodes of 21 nm and 15 nm [3], [8]-[13]. The rest of the paper is organised as follows. Section II briefly describes the equivalent RLC parameters of copper based nano-interconnects. The proposed delay and crosstalk analysis model is explained in section III. Section IV describes the crosstalk analysis results using our proposed model for various technology nodes and levels of interconnects. The work concludes in section V. II.

E QUIVALENT ELECTRICAL PARAMETERS OF COPPER INTERCONNECTS

I. I NTRODUCTION With the continued scaling of feature sizes, the clock frequency increases, separation between adjacent interconnects decreases, signal edge rates become faster and interconnects become longer. Aggressive interconnect scaling also leads to significant coupling capacitance among adjacent interconnects. Moreover, because of the higher operational frequencies and lower resistivity copper interconnects, inductive impedance of the on-chip wires become comparable to or larger than the resistive impedance. Due to these reasons, on chip capacitive and inductive effects have become a major concern for signal integrity and performance of today’s copper (Cu) based nanointerconnects [1]. So, conventional approaches of lumped or distributed RC model of interconnects are not adequate for delay and crosstalk prediction especially in intermediate and global wires in the nanometer regime [2]. In [3], the investigation on a single distributed RLC line has been done without any consideration of coupling capacitances. Delay and crosstalk have been modeled in [4] for loosely coupled interconnects. Time domain expressions for output of capacitively coupled interconnects have been developed using the transmission line theory in [5], [6]. However, the delay and crosstalk noise expressions ignore the effect of capacitive loading at the receiver end. In [7], the lumped parameter approximation was considered for crosstalk delay and noise estimation, which did not correctly model the intermediate and global interconnects of the nanometer regime. In [8]-[10], two coupled interconnects are considered for the analytical estimation of crosstalk delay and noise using classical ABCD parameter based approach. ABCD matrix based method is also reported to be advantagious to SPICE simulations [11] and This work is partially supported by the DIT, Government of West Bengal, India under VLSI Design Project.

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A typical copper interconnect system is shown in Fig. 1. In Fig. 1, 𝐿 is interconnect length, 𝑟 is per unit length (p.u.l) resistance, 𝑙 is p.u.l self inductance, 𝐶𝑔 is p.u.l electrostatic ground capacitance and 𝐶𝑐 is p.u.l electrostatic coupling capacitance. The driver is implemented using inverting buffers and load is capacitive, denoted by 𝐶𝐿 . The buffers can be modeled as an equivalent RC circuit with a high degree of accuracy [3]. The parameters of the driving buffer are 𝑅𝑠 and 𝐶𝑜𝑢𝑡 . 𝑅𝑠 and 𝐶𝑜𝑢𝑡 are the equivalent switching resistance and the equivalent diffusion capacitance of a minimum sized inverter buffer. RC parameters of the driver and load inverting buffer are estimated using the device parameters from ITRS2011 roadmap [14]. The estimated parameters are shown in Table I. The technology parameters for various levels of copper interconnects are obtained from ITRS-2011 roadmap [14] and shown in Table II. The analytical equations from [15] are used to calculate the distributed RLC parameters (i.e., 𝑟, 𝑙, 𝐶𝑔 and 𝐶𝑐 ) of copper interconnects. TABLE I. RC PARAMETERS OF THE MINIMUM SIZED BUFFER FOR VARIOUS TECHNOLOGY NODES  Technology node  Parameters   𝑅𝑠 (in KΩ) 𝐶𝑜𝑢𝑡 (in fF)

III.

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15 nm

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47.4 0.03

P ROPOSED M ODEL FOR ANALYSIS OF CROSSTALK EFFECTS

In this work, a computationally efficient model for crosstalk analysis in identically coupled interconnect systems is presented. The model is applied for analyzing crosstalk effects in copper based nano-interconnect systems and compared with

Infinitesimal section of a distributed line

TABLE II. INTERCONNECT PARAMETERS (ITRS-2011) Year DRAM 1/2 pitch (nm) (contacted) MPU/ASIC Metal1 1/2 pitch (nm) (contacted) MPU Physical gate length (nm) No. of Metal levels Wiring pitch (nm)

A/R (Cu)

A/R (Via)

Effective Resistivity (𝜇 Ω-cm) VDD (Volt) 𝑇𝑜𝑥 (nm) Effective dielectric constant (𝑘𝑒𝑓 𝑓 ) Average dielectric constant (𝑘𝑎𝑣𝑔 )

2015 25.26

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Fig. 3. Crosstalk delay waveform for 2 mm long copper interconnect in 15 nm technology node. (a) Crosstalk delay waveform as obtained from SPICE and proposed model when aggressor and victim nets switch in opposite direction. (b) Zoomed crosstalk delay waveform.

TABLE X. CROSSTALK NOISE COMPARISON IN INTERMEDIATE LEVEL INTERCONNECTS IN 15 𝑛𝑚 NODE

TABLE XII. CROSSTALK NOISE COMPARISON IN GLOBAL LEVEL INTERCONNECTS IN 15 𝑛𝑚 NODE Length

Length 10 𝜇m 50 𝜇m 100 𝜇m 500 𝜇m 1 mm

NP(mV) NW(ns) NA(V-ps) SPICE Model SPICE Model SPICE Model % diff 2.35 2.33 1.49 1.49 1.75 1.74 0.57 9.78 9.66 5.37 5.37 26.3 26 1.14 18.44 18.2 10.5 10.5 96.5 95 1.55 75.53 74.6 60 59.7 2260 2220 1.77 125.99 125 145 143 9130 8980 1.64 Average simulation time in SPICE is ∼114 sec and our model takes ∼2.35 sec. So our model is in average ∼ 48.5 times faster than SPICE.

TABLE XI. CROSSTALK NOISE COMPARISON IN GLOBAL LEVEL INTERCONNECTS IN 21 𝑛𝑚 NODE Length 100 𝜇m 500 𝜇m 1 mm 1.5 mm 2 mm

NP(mV) NW(ns) NA(V-ps) SPICE Model SPICE Model SPICE Model % diff 29.38 29.1 0.875 0.875 12.9 12.7 1.55 105.74 105 4.39 4.36 232 228 1.72 167.54 167 10.7 10.6 898 883 1.67 209.66 210 19.3 19 2020 1990 1.48 240.34 241 30.1 29.6 3620 3560 1.66 Average simulation time in SPICE is ∼121 sec and our model takes ∼3.9 sec. So our model is in average ∼ 31 times faster than SPICE.

calculated the delay values due to the crosstalk for two cases : (a) 𝑇 1𝑃 𝐿𝐻 : when aggressor and victim nets switch in the same direction, from low to high, and (b) 𝑇 2𝑃 𝐿𝐻 : when aggressor and victim nets switch in the opposite direction, victim net switches from low to high and aggressor nets switch from high to low. Fig. 3(a) shows crosstalk delay waveforms as obtained by SPICE simulations and proposed model when the nets switch in opposite direction. The difference between the waveforms is shown in Fig. 3(b).

100 𝜇m 500 𝜇m 1 mm 1.5 mm 2 mm

NP(mV) NW(ns) NA(V-ps) SPICE Model SPICE Model SPICE Model % diff 21.56 21.3 1.9 1.9 20.5 20.2 1.46 82.41 81.4 10.2 10.1 420 412 1.9 134.16 133 24.7 24.5 1660 1630 1.81 170.49 170 44.1 43.5 3760 3700 1.6 197.46 198 68.3 67.2 6740 6640 1.48 Average simulation time in SPICE is ∼101 sec and our model takes ∼2.25 sec. So our model is in average ∼ 45 times faster than SPICE.

C. Results of Crosstalk noise analysis Table IX, X, XI and XII show the crosstalk noise values for various technology nodes and level of interconnects in three identically coupled copper interconnect system. Our model has accuracy within ∼2.38% of SPICE and in an average 40 times faster than SPICE. We have calculated various noise parameters to characterize the crosstalk induced noise. These parameters include Noise peak amplitude (NP), Noise width (NW) and Noise Area (NA). NA is calculated as, 𝑁 𝐴 = 12 𝑁 𝑃 × 𝑁 𝑊 . In all these simulations, the victim net remains at low and aggressor nets switch from low to high, thus inducing a noise in the victim net. Fig. 4(a) shows crosstalk noise waveforms as obtained by SPICE simulations and proposed model. It can be observed that the waveforms obtained using SPICE and the proposed model is nearly the same. The difference between the waveforms is shown in the Fig. 4(b). V. C ONCLUSIONS In this work, an analytical model for crosstalk induced delay and noise has been presented for identically coupled copper based interconnects for various interconnect levels and technology nodes in the nanometer regime. The result shows that the proposed model is almost 100% accurate as SPICE. It is shown that the proposed crosstalk delay model is in an

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Fig. 4. Crosstalk noise waveform for 2 mm long copper interconnect in 15 nm technology node. (a) Crosstalk noise waveform as obtained from SPICE and proposed model when victim net remains quiet at ground and aggressor nets switch. (b) Zoomed crosstalk noise waveform.

average ∼22 times and crosstalk noise model is ∼40 times faster than SPICE. It is also shown that the crosstalk noise peak voltage reduces as we move towards scaled technology nodes but noise width increases with scaling. It is also observed that the noise area increases as we scale more which is a concern for the overall signal integrity in the nanometer technology nodes. All the noise parameters increase with the length of the interconnect. It is also observed that the crosstalk delay increases monotonically with the interconnect length. The crosstalk delay increases as we scale deeper. Hence, we may conclude that the crosstalk noise and delay will be a concern for the performance and integrity of the copper based nanointerconnects in future IC technology nodes. R EFERENCES [1] E. E. Davidson, B. D. McCredie, and W. V. Vilkelis, “Long lossy lines (𝐿3 ) and their impact upon large chip performance,” IEEE Trans. Components, Packaging and Manufacturing Technology, Part B: Advanced Packaging, vol. 20, pp. 361-375, Nov. 1998. [2] A. Deutsch et. al., “When are transmission-line effects important for onchip interconnections?,” IEEE Trans. Microwave Theory Tech., vol. 45, pp. 1836-1846, Oct. 1997. [3] K. Banerjee and A. Mehrotra, “Analysis of On-Chip Inductance Effects for Distributed RLC Interconnects”, IEEE TCAD, vol. 21, pp. 904-915, Aug. 2002. [4] K. T. Tang and E. G. Friedman, “Peak Crosstalk Noise Estimation in CMOS VLSI Circuits”, IEEE ICECS, pp. 1539-1542, September 1999. [5] J. A. Davis and J. D. Meindl, “Compact distributed RLC models for multilevel interconnect networks,” Symp. VLSI Technol. Dig. Techn. Papers, 1999, pp. 165-166. [6] J. A. Davis and J. D. Meindl, “Compact distributed RLC interconnect models-Part II. Coupled line transient expressions and peak crosstalk in multilevel networks,” IEEE Trans. Electron. Devices, vol. 47, pp. 20782087, Nov. 2000. [7] D. Das and H. Rahaman, “Unified Model for Analyzing Timing Delay and Crosstalk Effects in Carbon Nanotube Interconnects”, IEEE ASQED, pp. 100-109, 2012. [8] A. K. Palit, V. Meyer, W. Anheier and J. Chloeffel, “ABCD modeling of crosstalk coupling noise to analyze the signal integrity losses on the victim interconnect in DSM chips”, IEEE 18th International Conference on VLSI Design, 2005. [9] A. K. Palit, S. Hasan and W. Anheier, “Decoupled Victim Model for the Analysis of Crosstalk Noise between On-chip Coupled Interconnects,” 11th Electronics Packaging Technology Conference, pp. 697-701, 2009.

[10] J. Zhang and E. G. Friedman, “Decoupling Technique and Crosstalk Analysis for Coupled RLC Interconnects”, IEEE ISCAS, pp. 521524,2004. [11] M. Sahoo, P. Ghosal and H. Rahaman, “An ABCD parameter based Modeling and Analysis of Crosstalk Induced Effects in Single-Walled Carbon Nanotube Bundle Interconnects”, IEEE ASQED, Aug. 2013. [12] M. Sahoo, P. Ghosal and H. Rahaman, “An ABCD Parameter Based Modeling and Analysis of Crosstalk Induced Effects in Multiwalled Carbon Nanotube Bundle Interconnects”, IEEE 27𝑡ℎ International Conference on VLSI Design, 2014 (accepted). [13] M. Sahoo and H. Rahaman, “Analytical Modeling of Crosstalk Effects in Coupled Copper Interconnects in Deep Sub Micron Technology,” 5𝑡ℎ International Conference on Computers and Devices for Communication, 2012. [14] International Technology Roadmap for Semiconductors (ITRS-2011) Reports, [Online]. Available: http://www.itrs.net/reports.html. [15] Predictive Technology Model [Online]. Available: http://ptm.asu.edu/. [16] T. Sakurai, “Approximation of Wiring Delay in MOSFET LSI,” IEEE JSSC, vol. SC-18, no. 4, Aug. 1983.