IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 56, NO. 4, AUGUST 2009
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Modeling the Radiation Response of Fully-Depleted SOI n-Channel MOSFETs I. S. Esqueda, Student Member, IEEE, H. J. Barnaby, Senior Member, IEEE, M. L. McLain, Student Member, IEEE, P. C. Adell, Member, IEEE, F. E. Mamouni, Student Member, IEEE, S. K. Dixit, Member, IEEE, R. D. Schrimpf, Fellow, IEEE, and W. Xiong, Member, IEEE
Abstract—A continuous analytical model for radiation-induced degradation in fully-depleted (FD) silicon on insulator (SOI) n-channel MOSFETs is presented. The combined effects of defect buildup in the buried oxide and band-to-band tunneling (BBT) have been shown to be the primary mechanisms that determine the radiation effects on the electrical characteristics. Closed-form expressions for the front and back-gate surface potential incorporate these effects, thereby enabling accurate modeling of the degraded current voltage characteristics that result from ionizing radiation exposure. Index Terms—Band-to-band tunneling (BBT), fully-depleted silicon on Insulator (FDSOI), metal oxide semiconductor field effect transistor (MOSFET), total ionizing dose (TID). Fig. 1. Cross-section illustrating three current processes related to the radiation response on I-V characteristics of FD-SOI transistor [5].
I. INTRODUCTION
ECENT studies have shown that the combined impact of band-to-band tunneling (BBT) and positive trapped in the buried oxide is a significant factor in the charge radiation response of some FD-SOI n-channel MOSFETs [1], [2]. Energy deposition from ionizing radiation can lead to an in appreciable increase in the density of trapped charge the relatively thick buried oxide (BOX) layer as well as traps along the active silicon to BOX interface. The contribution is fixed and positive while the charge conof charge from tributed by interface traps will vary with surface potential (i.e., with external bias) [3], [4]. Net positive charge in the BOX will shift the back-side flatband voltage, inducing negative front-side threshold shifts as well as drain-to-source leakage current along the back-side channel [5]–[7]. The role of impact ionization in enhancing the radiation-induced leakage currents at negative gate voltages for FD SOI devices with floating bodies has been presented by Schwank et al. in [7]. In that work, the authors
R
Manuscript received September 09, 2008; revised January 05, 2009. Current version published August 12, 2009. I. S. Esqueda, H. Barnaby, and M. L. McLain are with the Department of Electrical Engineering, Arizona State University, Tempe, AZ 85287-5706 USA (e-mail:
[email protected];
[email protected];
[email protected]). P. C. Adell is with the Jet Propulsion Laboratory, Pasadena, CA 91101 USA (e-mail:
[email protected]). F. El Mamouni, S. K. Dixit, and R. D. Schrimpf are with the Electrical Engineering and Computer Science Department, Vanderbilt University, Nashville, TN 37201 USA (e-mail:
[email protected];
[email protected];
[email protected]). W. Xiong is with Texas Instruments Inc., Dallas, TX 75201 USA (e-mail:
[email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TNS.2009.2012709
explained how, for high drain biases, the combination of positive trapped charge in the BOX and generation of electron-hole pairs through impact ionization could establish a positive feedback mechanism that would result in high currents [7]. However, the precise mechanism that causes this effect is still a matter of debate and it likely depends on the technology as well as the operating conditions. In [1], Adell et al. demonstrated through the use of TCAD simulations that gate-induced-drain-leakage (GIDL) caused by BBT near the drain-body junction will enhance back-side leakage current for large negative gate-to-drain voltages . Fig. 1 schematically summarizes the effects of BBT-inin the BOX on the duced currents and the buildup of drain-to-source currents. Hole transport towards the source is represented as the arrow labeled “1” in Fig. 1. The back-injection of electrons into the body across the forward-biased body-source junction is represented by the arrow labeled “2”, and flow of electrons along the back-gate interface (back side leakage current) due to charge buildup in the BOX is shown by arrow labeled “3”. The arrows in Fig. 1 represent the fluxes of holes and electrons assuming a negative gate-to-drain bias, a floating body, a positive drain-to-source bias, and positive charge buildup in the BOX [1]. A piece-wise continuous threshold-voltage-based model anwas alytically describing the combined effects of BBT and recently presented in [2]. In this paper, we present a fully continuous model based on solutions to the implicit function for surface potential along the front and back interfaces. Surface-potential-based models have been shown to reproduce accurately the I-V characteristics of un-irradiated FD-SOI devices [8], [9]. In this work, we extend these models to capture the combined impact of BBT and defect buildup in the BOX to simulate the
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III. ANALYTICAL MODEL The model is based on the first integration of the one-dimensional (1-D) Poisson equation given by
(1)
Fig. 2. Plot of I vs. V characteristics obtained experimentally at various m and W : m for V : V, TID levels for a device with L V V V.
=
=0
=1
= 0 150
=14
radiation response characteristics in these devices. The model is validated via comparisons to I-V measurements (drain current vs. front gate voltage) on FD-SOI n-channel MOSFETs exposed to 10 keV x-rays.
where is the electrostatic potential, is the electronic charge, is the dielectric permittivity of Si, is the intrinsic carrier is the body potenconcentration, is the thermal voltage, is the acceptor concentration (assumed uniform) tial, and [8]. By applying Gauss’ Law at the front and back interfaces, we obtain the front- and back-side boundary conditions which, when utilized with the integration of (1), gives an implicit equaand back surface tion for the potentials at the front surface . The implicit equation is given by
II. EXPERIMENTAL DETAILS The experimental data were obtained from radiation experiments performed on MESA-isolated FD-SOI devices ( m and m) exposed to 10 keV x-rays. Standard UNIBOND® SOI wafers were used as the starting material. The silicon film thickness and the BOX thickness were 58 nm and 150 nm, respectively. The silicon top layer was -type cm ). The active patterning follows a FinFET flow: Silicon “fins” are patterned and etched from the starting SOI material [10]. The devices considered in this paper are sufficiently wide and a standard planar SOI operation is assumed. After active patterning, the wafers went through a 700 C H anneal at 600 mTorr to smooth the etched surface and round the Si corners for the MESA isolations. A 2-nm SiO gate dielectric was grown by in-situ steam oxidation at 975 C. A 7 nm TiSiN gate-electrode layer was deposited by LPCVD and capped with 100 nm of poly-Si. Implanted source/drain dopants were activated by a 1000 C, 10 s RTA anneal. A conventional single level metal (AlSi) back end of line was used [11]. The devices were exposed to 10 keV x-rays in an ARACOR system up to 100 krad(SiO ) at a dose rate of 31.5 krad(SiO )/min. In-situ - characterization was performed immediately after irradiating to each total ionizing dose (TID) level with devices kept at room temperature. The bias conditions during irradiation were floating body, front gate voltage of 0.8 V, back gate voltage of 3.0 V, with source and drain grounded. The positive voltage on the back gate enhances the defect buildup in the BOX. - measurements were taken ranging from to V to for front gate voltages , with reveal the effects of BBT with various drain biases and back gate grounded. Fig. 2 is a plot source of the vs. characteristics obtained experimentally at m various TID levels for a device with gate length of m for V, and width of V [11].
(2) where is the front gate voltage, is the front gate metalis the front gate semiconductor workfunction difference, is the BOX thickness, is the back gate oxide thickness, voltage, is back gate metal-semiconductor workfunction is the defect potential expressed as difference and
(3) is assumed where the energy distribution of interface traps uniform [13]. In (2), is the body effect coefficient given by
(4) where
is the front gate oxide capacitance per unit area [6]. is defined as
(5) and
as
(6) is the Fermi potential [8]. where and comes from inteThe second equation relating grating Poisson’s equation in the Si film (assumed fully depleted) and is given by
(7)
ESQUEDA et al.: MODELING THE RADIATION RESPONSE OF FULLY-DEPLETED SOI n-CHANNEL MOSFETS
where is the silicon film thickness and at the back-side interface given by
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is the electric field
(8) where is the back gate oxide capacitance per unit area [12]. The BBT effect is modeled as an increase in the floating body due to the forward biased source-body junction. potential The forward bias across this junction can be expressed as
(9) is the distance between the source-body junction where and the source contact (assumed much less than the diffusion is the source doping, is the hole diffusivity, length), is the hole current density in the body (i.e., and GIDL) induced by band-to-band tunneling at the drain given . Here, is the width of the high by is the band-to-band tunneling carrier field region and generation rate given by
(10) where is a constant related to the effective mass of the electron V .s cm ), is the transition constant ( for ( MV/cm) and Si), is the tunneling probability constant ( is the magnitude of the local electric field [1], [2], [14]. is obtained by solving an implicit surface potential equation at the drain overlap region for negative gate-to-drain voltages [2]. Front- and back-side surface potentials at the source end of obtained using the body are computed using (2)–(10) where (9) is used as the body potential. On the drain end, surface potentials are computed with (2)–(10), where the body potential, in (2), (5), (6) and (8) is replaced with to capture the impact of drain voltage. The resulting front- and back-side and drain ends of surface potentials at the source the channel are inserted into the charge sheet model closed-form given by [15] expression for the drift current
(11) and into the charge sheet model closed-form expression for difgiven by [15] fusion current
(12) Here, is the gate width, is the gate length and is the elecand are replaced with tron mobility.
Fig. 3. Plot of I vs. V characteristics obtained experimentally (symbols) : V. as well as the simulated curves (solid lines) with V
= 0 05
and
, respectively, for the front gate and and , respectively, for the back gate. Using (11) and (12) we compute the total drain current contributions from the front and the back gates as functions of bias and defect density (i.e., , and ). The combination of the currents associated with the front and back gates give the total current, but can also be analyzed individually to observe their contributions to the radiation-induced drain current degradation. The plot in Fig. 3 shows the drain current vs. front gate voltage characteristics obtained experimentally (pre-irradiation and after various levels of TID exposure) as well as the simulated curves obtained from the continuous analytical model. V, V and . The The results are for plots in Fig. 3 show that the model accurately fits the pre- and post-irradiation I-V characteristics of the FD-SOI n-channel MOSFETs investigated here. The model reproduces the negative front-side threshold shifts caused by positive trapped charge buildup in the buried oxide as well as the stretch-out in the I-V characteristics due to the charging of the interface traps as a function of the back surface potential. Fig. 4 plots the drain current vs. front gate voltage characteristics obtained experimentally (pre-irradiation and after various levels of total ionizing dose exposure) as well as the simulated V, V and . The recurves for sults show that the model reproduces the increase in negative bias drain current caused by the combined effects of the trapped charges and BBT [1], [2]. Analysis of the experimental data has shown that for total dose levels below 60 krad, the increase in negative bias drain current is dominated by direct gate tunneling currents and not GIDL. Notice that gate tunneling currents are not included in this model and these are curve-fitted with an for the lower levels of TID. exponential dependence on and in the model Table I summarizes the values used for for obtaining the results in Figs. 3 and 4. Fig. 5 plots the simulated drain current contributions at a front V (sub-threshold region) from the gate bias of front (circles) and back gate (diamonds) as functions of at the BOX and for . For the pre-irradiation condition , the contributions from the back gate are negligible and the total drain current is equal to the drain current associated with the front gate. Conduction associated with both the as front and back gates contributes more significantly to increases, especially in the sub-threshold region. Fig. 5 shows
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SUMMARY OF
N
TABLE I VALUES USED IN MODEL
AND
D
buildup in the BOX, stretch-out of the I-V characteristics by and increased drain-to-source current for negative due to gate voltages due to BBT enhancement of radiation-induced back-side leakage current. Using the presented model it is possible to analyze the contributions on radiation-induced drain current degradation from the front and back gates independently. This analysis also verifies the coupling of the gates for and ) and trapped various conditions of biasing (i.e., charges ( and ). ACKNOWLEDGMENT
I
V
Fig. 4. Plot of vs. characteristics obtained experimentally (symbols) V. as well as the simulated curves (solid lines) with
V = 1:4
The authors would like to thank K. LaBel of NASA and K. Reinhardt of AFOSR for their support of this research. REFERENCES
V = 00:3
Fig. 5. Plot of simulated drain current contributions at V (subthreshold region) from the front (circles) and back gate (diamonds) as a function on and for .
N
D =0
that although the contributions associated with both the front and back gate increase with (i.e., due to gate coupling), the contributions from the back-gate eventually overcome those of cm ). The the front gate (at approximately inclusion of slightly shifts the curves in Fig. 5 down since for interface traps contribute net negative charge. Notice this that in the sub-threshold region the condition of both the front and back surfaces is most likely in depletion [11]. Thereby, coupling between the two gates will occur as seen in Fig. 5 by the increase in drain current contributions from both the front and back gates. IV. CONCLUSION A continuous surface-potential-based model that includes the effects of radiation damage and BBT enhancement of leakage currents for FDSOI transistors has been presented. A comparison to experimental data demonstrates that the model accurately reproduces negative threshold voltage shifts caused
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