Modeling the single-gate, double-gate, and gate-all-around tunnel ...

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Tunnel field-effect transistors TFETs are potential successors of metal-oxide-semiconductor FETs ... termines the tunnel current of a single-gate TFET, but there.
JOURNAL OF APPLIED PHYSICS 107, 024518 共2010兲

Modeling the single-gate, double-gate, and gate-all-around tunnel field-effect transistor Anne S. Verhulst,1,2,a兲 Bart Sorée,2 Daniele Leonelli,2 William G. Vandenberghe,2 and Guido Groeseneken2 1

IMEC, Kapeldreef 75, 3001 Leuven, Belgium Department of Electrical Engineering, K.U.Leuven, Kasteelpark Arenberg 10, 3001 Leuven, Belgium

2

共Received 18 August 2009; accepted 30 November 2009; published online 28 January 2010兲 Tunnel field-effect transistors 共TFETs兲 are potential successors of metal-oxide-semiconductor FETs because scaling the supply voltage below 1 V is possible due to the absence of a subthreshold-swing limit of 60 mV/decade. The modeling of the TFET performance, however, is still preliminary. We have developed models allowing a direct comparison between the single-gate, double-gate, and gate-all-around configuration at high drain voltage, when the drain-voltage dependence is negligible, and we provide improved insight in the TFET physics. The dependence of the tunnel current on device parameters is analyzed, in particular, the scaling with gate-dielectric thickness, channel thickness, and dielectric constants of gate dielectric and channel material. We show that scaling the gate-dielectric thickness improves the TFET performance more than scaling the channel thickness and that improvements are often overestimated. There is qualitative agreement between our model and our experimental data. © 2010 American Institute of Physics. 关doi:10.1063/1.3277044兴 I. INTRODUCTION

A potential candidate to replace the metal-oxidesemiconductor field-effect transistor 共MOSFET兲 in future technology nodes is the tunnel-FET 共TFET兲.1–11 Due to the absence of a subthreshold-slope limit of 60 mV/decade, the TFET can go beyond the supply voltage plateau of 1 V, which currently prevents further scaling of the MOSFET power consumption.12 However, despite the recent increase in TFET publications, the physical understanding of the TFET mechanism is still very limited, especially for morethan-one-dimensional TFETs. A first model has been introduced for TFETs 共Ref. 13兲 but this model has a few shortcomings. First, the model assumes that the tunnel path length at the onset of tunneling equals the MOSFET screening length. Yet, at onset of tunneling in TFETs, the tunnel path is first very long 共only limited by the channel length兲 and then, as the gate-source voltage increases, the tunnel path length becomes shorter and of lengths comparable to the screening length. Second, the screening length is only an approximation of the potential variation length in the channel, which has proven to accurately model the MOSFET performance.14 However, for a TFET model, it is important that the potential profile is determined as accurately as possible, given the exponential dependence of the tunnel current on the tunnel path length. Third, the screening-length picture does not consider a dependence on the source doping, even though it is known from simulations that the source doping strongly impacts the TFET performance. Finally, in this model, the screening length keeps increasing with increasing channel thickness instead of saturating at some point to a length applicable to a single-gate configuration. a兲

Electronic mail: [email protected].

0021-8979/2010/107共2兲/024518/8/$30.00

A second more recent TFET model is based on the exact potential profile of the TFET configuration.15 This model determines the tunnel current of a single-gate TFET, but there is no straightforward extension of the model to other gate configurations. In our article, we develop a new modeling framework, starting from the same assumptions as Ref. 15 and making a simplification, such that a direct comparison between a single-gate, double-gate, and gate-all-around 共GAA兲 configuration can be made. Our article also gives insight in the impact of the choice of tunnel path in two- or three-dimensional TFET configurations. Based on our developed models, the dependence is analyzed of the tunnel current on design parameters like gatedielectric thickness, channel thickness, and dielectric constants of gate dielectric and channel material. We show that not only the impact of these parameters at a fixed gate voltage but also the shift in the full I − V curve should be considered when determining the design-based improvements of the TFET performance. Finally, we compare our model with our experimental data of TFET FinFETs with varying fin width and show qualitative agreement. II. MODEL DERIVATION

The tunneling process of our model is described by the widely used Kane model, which determines the generation rate per unit volume GKane of carriers tunneling from valence band to conduction band, GKane = PKane exp共− BKaneE3/2 g /E兲,

共1兲

= PKane exp共− BKaneq冑Eglpath兲,

共2兲

where PKane is the material-dependent and voltage-dependent prefactor of Kane’s model, BKane is the material-dependent constant, Eg is the bandgap, E is the average electric field

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over the tunnel path 共E = qg / lpath, with q the elementary charge兲, and lpath is the length of the tunnel path.16 The source-drain tunnel current of a three-dimensional TFET is then given by Ids,tun = q

=q





共3兲

GKanedV,

PKane exp共− BKaneq冑Eglpath兲dV,

共4兲

where V is the three-dimensional volume inside the device where tunnel paths start 共or where tunnel paths end兲. The volume integration in Eq. 共4兲 does not allow for the derivation of a compact analytical model of the tunnel current in the case of a double-gate and GAA configuration. We therefore simplify Eq. 共4兲 to

⬘ exp共− BKaneq冑Eglshortest Ids,tun ⬇ PKane

path兲,

共5兲

where PKane ⬘ is a modified prefactor 共PKane ⬘ = 1 is used for calculations兲. This simplification is based on the observation that the generation rate GKane consists of a prefactor and an exponential factor. If we assume that the variation in the exponential factor dominates, as is the case in the subthreshold regime of the tunnel current, Eq. 共4兲 reduces to an integration of an exponential factor only. Because integrations retain an exponential and assuming that the exponential factor corresponding to the shortest tunnel path dominates, as is the case for the single-gate configuration of Ref. 15, Eq. 共4兲 can be simplified to Eq. 共5兲. Unlike Eq. 共4兲, Eq. 共5兲 only depends on the choice of the shortest tunnel path instead of all tunnel paths, which allows for a more flexible comparison between different device configurations. To determine the shortest tunnel path, as required for Eq. 共5兲, we determine the exact electrostatic profile of the given TFET configuration, making the same assumptions as Ref. 15, namely, •

that the TFET has a source region with an extremely high doping, such that the potential drop across the source region is negligible; • that the influence of the charge in the channel region on the channel potential can be neglected, an assumption which is valid for high enough drain-source voltages such that no inversion layer builds up in the channel; • that gate dielectrics with identical effective thicknesses result in identical potential profiles in the channel region 共this assumption can be proven to be correct for a single-gate configuration兲; and • that the source electrode extends along the gate dielectric all the way to the gate electrode. In other words, the TFET configuration is modeled as a capacitor with source electrode and gate electrode 共and drain electrode兲. A. Remarks on model accuracy

For two- and three-dimensional TFET configurations, the calculation of the tunnel current, when based on the

FIG. 1. 共Color online兲 共a兲 The single-gate TFET configuration used for our model derivation: p-type doped source region, n-type doped drain region assumed to be located at infinity, undoped channel region treated as dielectric and including both the actual channel region and the effective gate dielectric. 共b兲 Equipotential lines 共solid, through the origin兲 and electric field lines 共dashed兲 corresponding to the configuration of 共a兲. The black solid horizontal represents the channel-gate-dielectric interface. 共c兲 Positions of the conduction and valence band edges along the shortest electric field line 关curved line ending in a dot in 共a兲兴.

widely used Eq. 共3兲, inherently leads to a qualitative model. This is because such a calculation is semiclassical: the tunnel process is reduced from its full quantum mechanical description with incoming wave function, transmission probability and outgoing wave function to a point-to-point process. However, except for one-dimensional configurations, a full quantum mechanical treatment is extremely complicated and beyond the scope of our article. The reduction of the tunnel process to a point-to-point process also results in a major impact of the exact choice of tunnel paths on the calculated current, as will be illustrated in Sec. III D. The latter statement is especially important when evaluating the TFET performance with simulation packages. A poor choice of the tunnel path by the simulation software may lead to inaccurate or incorrect predictions of the tunnel current dependence on device parameters. The impact of the drain voltage VD is not fully incorporated in our model. It is not sufficient to include the impact of VD on the electrostatic profile, as will be done for the GAA configuration. It should also be considered that when inversion sets in the channel, the channel charge can no longer be neglected. This is a new effect, beyond the scope of this article. B. Single-gate

The single-gate configuration is shown in Fig. 1共a兲, with the corresponding electrostatic profile in Fig. 1共b兲. When considering circular tunnel paths, this is tunnel paths parallel to electric field lines, the shortest tunnel path ends at the black dot in Fig. 1共a兲, which is at the crossing of the channelgate-dielectric interface with the equipotential line corresponding to a band bending of one time the bandgap. At the absolute onset of tunneling, when the latter equipotential line coincides with the gate electrode, the tunnel path is infinitely long 共in practice limited by the channel length兲. As the gatesource voltage increases, this equipotential line correspond-

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ing to a band bending of one time the bandgap turns toward the source electrode and the tunnel paths shorten, whereby both onset and end point of the tunnel paths move toward the intersection of the source-channel interface with the gate electrode. The tunnel current according to our model of Eq. 共5兲 is then for a p-type source TFET 共top sign兲 and n-type source TFET 共bottom sign兲 circ = exp共− BKaneq冑Egr0␪0兲, Isingle



=exp

− BKaneq冑Egtgd,eff



⬘ − Eg ␲ ⫾qVgs sin 2 ⫾qVgs ⬘

with tgd,eff = tgd



共6兲



␲Eg , ⬘ ⫾2qVgs

共7兲

⑀ch , ⑀gd

共8兲

⬘ = Vgs − VFB , with Vgs

共9兲

where r0 is the radius of the shortest circular tunnel path, ␪0 is the angle between the equipotential line of the sourcechannel interface 共considered to be at source voltage Vs兲 and the equipotential line at a voltage of Vs ⫾ Eg / q, tgd,eff is the effective gate-dielectric thickness, Vgs is the gate-source voltage, tgd is the gate-dielectric thickness, ⑀gd 共⑀ch兲 is the relative dielectric constant of the gate dielectric 共channel material兲, and VFB is the flatband voltage. Another equally realistic choice of tunnel paths is to consider paths parallel to the gate dielectric, such that the shortest tunnel path is the path along the channel-gatedielectric interface 共dashed line in Fig. 1兲 starting at the crossing with the source-channel interface and ending at the black dot in Fig. 1共a兲, which is at the crossing with the equipotential line corresponding to a band bending of one time the bandgap. Equation 共5兲 then becomes straight = exp关− BKaneq冑Egtgd,eff tan共␪0兲兴 Isingle





=exp − BKaneq冑Egtgd,eff tan

␲Eg ⬘ ⫾2qVgs

冊册

共10兲 共11兲

The tunnel current according to Eq. 共11兲 is always larger than the current according to Eq. 共7兲 because the straight tunnel path is always shorter than the circular tunnel path 共full discussion in Sec. III D兲.

The double-gate configuration is shown in Fig. 2共a兲. The first step in the model derivation is again the determination of the electrostatic profile 关see Fig. 2共b兲兴, which is determined from the solution of the Laplace equation for the configuration of Fig. 2共a兲 and is given by





⬘ 2Vgs sinh共y ␲/T兲 atan , ␲ sin共x␲/T兲

共12兲

共13兲

with T = 2tgd,eff + tch ,

where tch is the channel thickness, and with the origin of the xy-plane at the crossing of the gate electrode with the source electrode. The equipotential lines are curved, whereby the tangents to the equipotential lines in the origin represent the equipotential lines of the single-gate configuration. Each equipotential line is therefore closer to the source electrode than in the single-gate configuration such that tunnel paths are shorter, independent of the choice of tunnel path and therefore, the tunnel currents are larger. Differences in electrostatic profile are the largest in the tunneling onset region for which the tunnel paths are the largest 共full discussion in Sec. III兲. In a second step, the shortest tunnel path is determined. Straight tunnel paths are assumed, such that the shortest one runs along the channel-gate-dielectric interface, starting at the crossing with the source-channel interface and ending at the crossing with the equipotential line corresponding to a band bending of one time the bandgap lshortest,straight =

冋 冉 冊 冉 冊册

Eg ␲ tgd,eff␲ T asinh tan sin ␲ 2 T ⬘ qVgs

. 共14兲

The model of Eq. 共5兲 therefore becomes



straight = exp − BKaneq冑Eg Idouble

2tgd,eff + tch ␲

冋 冉 冊冉

⫻asinh tan

C. Double-gate

V共x,y兲 =

FIG. 2. 共Color online兲 共a兲 The double-gate TFET configuration used for our model derivation: p-type doped source region, undoped channel region treated as dielectric and including both the actual channel region and the effective gate dielectric. The channel is assumed to be infinitely long. 共b兲 Equipotential lines 共solid, through the origin兲 and electric field lines 共dashed兲 corresponding to the configuration of 共a兲. The black solid horizontals represent the channel-gate-dielectric interface.

tgd,eff␲ Eg ␲ sin 2tgd,eff + tch ⬘ 2 qVgs

冊册冎

共15兲

For a TFET in planar silicon-on-insulator 共SOI兲 configuration, with a thick bottom oxide and no active back gate, the electrostatic profile corresponds to half of the profile of a double-gate configuration with channel thickness equal to two times the SOI silicon thickness tSi. The tunnel current according to our model is therefore, given by Eq. 共15兲, with tgd,eff the effective gate-dielectric thickness and with tch = 2tSi.

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FIG. 3. 共Color online兲 共a兲 Cross section of TFET configuration used for the cylindrical GAA model derivation: p-type doped source region, n-type doped drain region, undoped channel region treated as dielectric and including both the actual channel region and the effective gate dielectric. 共b兲 3D view on the GAA configuration: the bottom plane is at a source voltage VS, the top electrode at a drain voltage VD, and the cylindrical surface is at a gate voltage VG⬘ .

D. GAA

The GAA configuration is shown in Fig. 3共a兲. The first step in the model derivation is again the determination of the electrostatic profile, which is determined from the solution to the Laplace equation in cylindrical coordinates, corresponding to the configuration of Fig. 3共b兲 ⬁

⬘ + V共r,z兲 = Vgs



⬘ ⬘ − Vds兲 2共Vgs 2Vgs An共r,z兲 + 兺 兺 Bn共r,z兲, R n=1 R n=1 共16兲

with An共r,z兲 =

with Bn共r,z兲 =

sinh关冑␭0n共z − L兲兴 J0共冑␭0nr兲

冑␭0n sinh共冑␭0nL兲 J1共冑␭0nR兲 , sinh关冑␭0n共− z兲兴 J0共冑␭0nr兲

冑␭0n sinh共冑␭0nL兲 J1共冑␭0nR兲 ,

共17兲

FIG. 5. 共Color online兲 Tunnel current as a function of gate-dielectric thickness according to Eq. 共11兲 共single-gate兲, Eq. 共15兲 共double-gate, tch = 10 nm兲, and the numerically defined tunnel current according to the potential profile of Eq. 共16兲 共GAA, Rch = 5 nm, L = 5 ␮m兲.

example of the equipotential profile is displayed in Fig. 4. Just like in the double-gate configuration, the equipotential lines are curved and therefore closer to the source electrode than in the single-gate configuration. The curvature and therefore the impact on the tunnel paths, is stronger than for the double-gate configuration. In a second step, the shortest tunnel path is determined. Just like in the double-gate configuration, a straight tunnel path is assumed. Because the formula of Eq. 共17兲 has an infinite summation, the shortest tunnel path is determined numerically. In particular, we calculate the potential profile along the interface of the channel with the gate dielectric, V共Rch , z兲, and determine numerically the position z = lshortest,straight at which this potential profile has increased 共decreased兲 with an amount Eg / q. Inserting lshortest,straight in Eq. 共5兲 provides us with a model for the GAA configuration.

共18兲

with 0 = Jo共冑␭0nR兲 defining ␭0n ,

共19兲

with R = tgd,eff + Rch ,

共20兲

where L is the channel length, Rch is the channel radius, and J0共 兲 and J1共 兲 are the Bessel functions of the first kind. An

III. MODEL-BASED ANALYSIS OF TFET PERFORMANCE

In this section, we analyze the dependence of the tunnel current and subthreshold swing on design and operation parameters.

A. Impact of gate-dielectric thickness

Figure 5 displays the tunnel current as a function of gatedielectric thickness according to our models for a singlegate, double-gate, and GAA TFET configuration. The parameters of Table I are used in the calculations. The tunnel current increases exponentially 共single-gate兲 or faster than TABLE I. TFET’s default design parameters representative for a configuration with a silicon channel and a realistic hafnium-oxide gate dielectric. Symbol FIG. 4. Equipotential profile 共16-color greyscale兲 corresponding to the circular GAA configuration of Fig. 3. The x-axis corresponds to a voltage VS, the right vertical axis to a voltage VG⬘ ,. The channel length L is long 共5 ␮m兲, such that the impact of the VD on the profile is negligible.

⑀gd ⑀ch Eg BKane

Default value

Unit

15 11.9 1.12 2.8⫻ 1037

eV V / 共m J3/2兲

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FIG. 6. 共Color online兲 Tunnel current as a function of the square root of the channel thickness according to Eq. 共15兲 共double-gate兲. The shaded region indicates the region where quantum confinement effects should be considered.

exponentially 共GAA兲 with decreasing gate-dielectric thickness. Scaling the gate dielectric is therefore very important for all TFET configurations. The impact of decreasing the gate-dielectric thickness is the strongest at onset 共black curves兲 when the tunnel paths are the longest 关see exponential dependence on tunnel path length, e.g., in Eq. 共5兲兴. At very small dielectric thicknesses, the thickness impact for the double-gate and GAA configurations increases and the curves start to coincide because the current is dominantly determined by the electrostatic profile very close to the gate electrode, where in the limit all configurations resemble a single-gate configuration.

B. Impact of channel thickness

Figure 6 displays the tunnel current as a function of the square root of the channel thickness according to our doublegate model and using the parameters of Table I. At large channel thicknesses, the double-gate configuration effectively acts as a single-gate configuration. This is because the potential profile close to the gate dielectric, where the shortest tunnel path is determined, is not affected by the second gate. At smaller channel thicknesses, when the effective gate-dielectric thickness tgd,eff is no longer negligible with respect to the total thickness T, a rather linear dependence is observed on the log-冑tch scale. The latter dependence is confirmed by our experimental data 共see Fig. 10, discussion in Sec. IV兲. At the smallest channel thicknesses, when tgd,eff is the dominant term in the total thickness T, the tunnel distance levels off to a nonzero value. The model therefore predicts that the tunnel current saturates. However, the impact of the tunnel volume can no longer be neglected 关see Eq. 共4兲兴, as zero channel thickness implies of course no current. At the same time, a full quantum mechanical description is required at the smallest channel thicknesses because quantum confinement effects occur in silicon for tch ⱗ 3 nm. Our modeling framework is therefore not very accurate for the thinnest channels. Figure 6 also shows that the impact of the channel thickness decreases as the gate-source voltage increases. This is

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FIG. 7. 共Color online兲 Tunnel current as a function of the square root of the channel thickness according to Eq. 共15兲 共double-gate兲 and based on the potential profile of Eq. 共16兲 共GAA, L = 5 ␮m兲. The shaded region indicates the region where quantum confinement effects should be considered.

because the tunnel paths become shorter and the electrostatic profile in a region closer to the source-channel interface is closer to the single-gate profile. Figure 7 displays a comparison between the double-gate and GAA configuration as a function of the square root of the channel thickness and using the parameters of Table I. At large channel thicknesses, the double-gate and GAA configuration have identical tunnel currents 共also identical to the single-gate configuration兲. However, due to the stronger curvature of the equipotential lines in the GAA TFET, the tunnel current improvement starts at larger channel thicknesses than in the double-gate TFET, even when the strongest channel thickness impact 关⬃exp共−冑tch兲兴 is rather in the same region of channel thicknesses. Note that the impact of scaling the channel thickness is much weaker than of scaling the above-discussed gatedielectric thickness. C. Impact of dielectric constants ⑀gd and ⑀ch

There is a 共nearly兲 exponential scaling of the tunnel current with 1 / ⑀gd and ⑀ch, similar to the scaling with gatedielectric thickness tgd 共see Fig. 5兲. This is because the tunnel current models are dependent on the dielectric constants through tgd,eff only 关see definition in Eq. 共8兲兴. D. Impact of applied gate-source voltage

Figure 8 displays the tunnel current as a function of effective gate-source voltage. The tunnel current is characterized by an absolute onset voltage 共Vgs ⬘ = Eg / q兲 at which the induced band bending in the channel is equal to one time the bandgap only in the extreme case of an infinitely thin gate dielectric and an infinitely long channel. For a realistic device configuration, Vgs ⬘ ⬎ Eg / q applies before tunneling starts. The shortest tunnel path is first very long 共only limited by the channel length兲 implying a small tunnel current. With increasing Vgs ⬘ , the tunnel path then shortens fast and due to the exponential dependence 关see Eq. 共5兲兴, this results in a steep onset of the tunnel current. At larger Vgs ⬘ , the tunnel path is sufficiently short, that the exponential factor approaches 1 and the tunnel current saturates.

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FIG. 8. 共Color online兲 Tunnel current as a function of effective gate-source voltage according to Eq. 共7兲 共single-gate, circular兲, Eq. 共11兲 共single-gate, straight兲, Eq. 共15兲 共double-gate兲 and the numerically defined tunnel current according to the potential profile of Eq. 共16兲 共GAA, L = 5 ␮m兲. The dashed vertical line indicates the absolute onset voltage for tunneling.

Figure 8 compares the tunnel current of the single-gate, double-gate, and GAA configuration. The difference in tunnel current is the largest at onset, when the electrostatic profile differences are the largest 共for large tunnel paths兲. However, the figure also shows that the improvement is in part resulting from a shift in the I − V curves and therefore the apparent current increase is larger than the effective increase, which considers the effective voltage window required to go from a fixed off-current level to a fixed on-current level. This shift is discussed in-depth with Fig. 9. Figure 8 also illustrates the sensitivity of the calculated tunnel current to the tunnel path choice 共see single-gate

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curves兲. As expected, the model based on the shorter straight tunnel paths results in the largest current. The biggest difference occurs at onset, when the paths are the longest. Assuming, e.g., the off-state at I = 10−9, tunnel current differences at onset amount up to two orders of magnitude with a shift in onset voltage of about 70 mV. It is therefore very important to be aware of the choice of tunnel path when comparing TFET performance predictions of different models or device simulators. Figures 9共a兲 and 9共b兲 display the Ids − Vgs curves for respectively different gate-dielectric and channel thicknesses of a GAA configuration. When the original curves are shifted such that they coincide at a tunnel current of 10−9 共representative for the off-state兲, the impact of the design variations is decreased. This is because the apparent tunnel current improvement at one particular gate-source voltage, as analyzed in Secs. III A and III B, is in part due to a shift in the Ids − Vgs curve. Such a shift does not result in an effective Ion / Ioff increase at a fixed supply voltage window. The effective impact of scaling tgd is only close to the apparent impact at advanced thicknesses tgd ⬍ 3 nm 关Fig. 9共a兲兴, while the effective impact of scaling Rch is only significant below Rch = 5 nm 关Fig. 9共b兲兴. However, Fig. 9 also shows that the effective impact of scaling gate-dielectric thickness is still much stronger than scaling channel thickness. Figure 9 further illustrates that tunnel current improvement also implies subthreshold-slope improvement 共consider, e.g., a threshold voltage linked to I = 10−3兲. The increase in the subthreshold-slope steepness is mainly due to the existence of an absolute onset voltage for tunneling, where the subthreshold slope is locally infinitely steep. The curves also indicate that extreme scaling allows to go beyond the 60 mV/decade subthreshold-swing limit of MOSFETs 关see top curves in Figs. 9共a兲 and 9共b兲兴. Even though the example of the GAA configuration is used in Fig. 9, similar observations apply to the single-gate and double-gate configuration.

IV. MODEL-EXPERIMENT COMPARISON

FIG. 9. 共Color online兲 The Ids − Vgs curves of the GAA configuration for 共a兲 different gate-dielectric thicknesses and 共b兲 different channel diameters 共see legends兲. The dashed curves are shifted versions of the top and bottom solid curves such that all curves coincide at Ids = 10−9.

We have performed measurements on FinFET TFETs 共Refs. 17 and 18兲 with varying fin width Wfin 共see Fig. 10兲. The currents are normalized with respect to the fin perimeter 关2ⴱ共fin height兲 + Wfin兴. Figure 10共a兲 shows a strong current increase with decreasing Wfin, although this current increase is almost entirely an apparent increase 关see nearly coinciding shifted curves in the inset to Fig. 10共a兲兴, in agreement with our model predictions. Figure 10共b兲 shows the current as a function of the square root of the channel thickness. The theoretically predicted linear dependence on the log-冑tch scale 共see Fig. 6兲 is also observed experimentally. To model the fin configuration, we consider the fin top section 共three narrowest fins兲 or side sections 共two widest fins兲 as half of a cylindrical configuration 共see Table II for information on corresponding diameter兲. For the three narrowest fin configurations, the remaining fin side walls are modeled as a double-gate configuration. For the two widest fin configurations, the remaining top section is modeled as an

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FIG. 10. 共Color online兲 Experimental data of FinFET TFETs on 300 mm wafers. 共a兲 Ids − Vgs curves for different fin widths. Inset: shifted curves such that all curves cross the 兵−0.9 V , 10−11 A / ␮m其 data point. 共b兲 Current as a function of 冑tch 共second column of Table II兲 at different gate-source voltages. Device parameters: channel length of 150 nm, fin height of 65 nm, gate dielectric consisting of 3 nm hafnium oxide 共⑀ ⬇ 15兲 and 1 nm silicon dioxide, and titanium nitride gate metal 共Ref. 18兲. The source 共n-doped, simulated doping gradient of approximately 5 nm/decade兲 is grounded and the drain 共p-doped兲 is at ⫺0.9 V.

SOI double-gate configuration. Each component of the tunnel current is divided by the corresponding perimeter before summation. The modeling results are displayed in Fig. 11. There is only qualitative agreement between experiment 关Fig. 10共a兲兴 and model: the experimental data are shifted more strongly with varying fin width than the model predicts. This result indicates that the dependence of the band-to-band tunneling process on the fin width is not the only parameter determining the changing characteristics with changing fin width. Either the same processing has not resulted in the exact same device parameters 共like doping, doping profile, defect concentration, gate work function, etc.兲 with varying fin width, or there is an aspect of the TFET physics which is not yet incorporated in the model. V. CONCLUSIONS

We have developed a modeling framework allowing a direct comparison between single-gate, double-gate, and GAA TFETs. The tighter gate action of the double-gate and GAA configuration improves the TFET performance but improvements are only significant at small channel thicknesses 共below about 10 nm兲. Compared to scaling the body thickness, scaling the gate-dielectric thickness has a much stronger impact on the TFET current and subthreshold slope, even though improvements are often overestimated because the shift in the Ids − Vgs curve is not considered. We highlight that large differences in TFET performance will be predicted by different semiclassical models or device simulators if the TABLE II. Modeling parameters for FinFET TFETs 关fin corners have curvature of 2.5 nm radius 共Ref. 17兲兴. All data in nm. Wfin

Diameter cylinder

Remaining fin height

Remaining top section

10 20 40 250 1000

5 + 5ⴱ冑2 = 12 5 + 15ⴱ冑2 = 26 5 + 35ⴱ冑2 = 54 5 + 125ⴱ冑2 = 182 5 + 125ⴱ冑2 = 182

60 55 45 0 0

0 0 0 120 870

FIG. 11. 共Color online兲 Ids − Vgs curves according to our models and corresponding to the experimental data of Fig. 10.

choice of tunnel paths is different. Finally, there is qualitative agreement between our model and our experimental data of FinFET TFETs with varying fin width.

ACKNOWLEDGMENTS

The authors acknowledge R. Rooyackers and A. De Keersgieter for additional information on the experimental structures. A. Verhulst gratefully acknowledges the support of a postdoctoral fellowship of the Fund for Scientific Research-Flanders. W. Vandenberghe gratefully acknowledges the support of a Ph.D. stipend from the Institute for the Promotion of Innovation through Science and Technology in Flanders 共IWT-Vlaanderen兲. This work was also supported by IMEC’s Industrial Affiliation Program and by the EU Program No. NODE 015783. 1

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