Jul 20, 2012 - AbstractâIn this letter, a drain current noise model that in- cludes the ... CONTINUED scaling of technology and the demand for extremely low ...
IEEE ELECTRON DEVICE LETTERS, VOL. 33, NO. 8, AUGUST 2012
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MOSFET Drain Current Noise Modeling With Effective Gate Overdrive and Junction Noise L. H. K. Chan, K. S. Yeo, K. W. J. Chew, S. N. Ong, X. S. Loo, C. C. Boon, and M. A. Do
Abstract—In this letter, a drain current noise model that includes the channel thermal noise and the shot noise generated at the source–bulk junction and the drain–bulk junction is presented. A unified analytical expression is derived to ensure excellent continuity with smooth transition of drain current noise from weakto strong-inversion regimes, including the moderate-inversion region. Excellent agreement between simulated and extracted noise data has shown that the proposed model is accurate over different dimensions and operating conditions. Index Terms—High-frequency noise, moderate inversion (MI), MOSFET, subthreshold, thermal noise.
MOSFETs can be expressed as [5] Sid = δ4kT
δ≡
C
II. M ODEL F ORMULATION By including the channel length modulation effect and the effective mobility, the channel thermal noise of short-channel Manuscript received May 11, 2012; accepted May 23, 2012. Date of publication July 10, 2012; date of current version July 20, 2012. This work was supported in part by GLOBALFOUNDRIES Singapore Pte. Ltd. The review of this letter was arranged by Editor L. Selmi. L. H. K. Chan, K. S. Yeo, C. C. Boon, and M. A. Do are with the School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 639798. K. W. J. Chew, S. N. Ong, and X. S. Loo are with the School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 639798, and also with GLOBALFOUNDRIES Singapore Pte. Ltd., Singapore 738406. Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/LED.2012.2203781
(1)
where VGT = VGS − VT is the gate overdrive, with the threshold voltage VT = VT 0 − ηVDS , which includes the draininduced barrier lowering (DIBL) effect [1]. δ is the noise parameter defined as
I. I NTRODUCTION ONTINUED scaling of technology and the demand for extremely low power applications have driven the design to have CMOS devices operating in low-inversion regime. The difficulty in subthreshold RFIC design lies in the presence of noise that required accurate models. To date, many reported models [1]–[5] are derived based on piecewise channel charge density models which cannot ensure continuity from stronginversion (SI) to weak-inversion (WI) regimes. Although some publications [6]–[10] have been generated for noise modeling in all operating region, the diffusion-current-based thermal noise model or the shot noise model presented underestimates the noise level in the subthreshold region due to the presence of junction noise [13]. In this letter, a new unified high-frequency drain current noise model for deep-submicrometer MOSFETs is presented, by including a new effective gate overdrive equation and junction noise model. The model was experimentally verified to be continuous and accurate from the subthreshold to SI regions. With this model, RF designers will be able to simulate the noise performance of their RF circuits and examine the impact of this parameter on their circuit.
W µeff Cox VGT Leff
1 − u + u2 /3 . 1 − u/2
(2)
Here, u = αVDSeff /VGT , with α being the bulk charge coefficient and VDSeff being the drain bias smoothening function of BSIM4 [11] to guarantee the continuity from the nonsaturation region to the saturation region. Since the impact of velocity saturation and hot carrier effects on channel thermal noise are counterbalanced, both of them can be ignored [4]. With the field-dependent effective mobility µeff [5] and the gradual channel length Leff [11], (1) can accurately predict the channel thermal noise of short-channel MOSFETs, particularly in the drain bias domain. However, (1) is only valid in SI regime and fails in the WI region. To make (1) valid in both SI and WI regimes, a novel modification is done on the smoothening function VGST,eff presented in [11]. As a result, a new VGTeff is proposed as VGTeff = θ≡
2nvth ln(1 + eVGT /2nvth ) 2n 1 + θ(n−1) e−(VGT −2Voff )/2nvth
(3)
1 + e−VDS /vth 2δ
(4)
where vth = kT /q is the thermal voltage, n is the subthreshold slope factor, and Voff = VT,sub − VT is the offset voltage to characterize the leakage current at zero gate bias. The parameter Voff can be extracted from the measured I–V characteristics in the subthreshold region. With VGTeff in (3) replacing VGT in (1), the single-region channel thermal noise model is given by Sid = δ4kT
W µeff Cox VGTeff . Leff
(5)
In SI where VGS > VT , the denominator of (3) approaches one and the numerator of (3) approaches VGT , and hence, (5) approaches (1). In WI where VGS − VT < 2Voff , 1 + x in
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IEEE ELECTRON DEVICE LETTERS, VOL. 33, NO. 8, AUGUST 2012
the denominator of (3) approaches x and ln(1 + ex ) in the numerator of (3) approaches ex , such that VGTeff approaches VGTeff = θ(n − 1)vth e(VGT −Voff )/nvth
(6)
and the channel thermal noise in (5) reduces to the well-known WI noise model [1] Sid = 2qIsat (1 + e−VDS /vth ) Isat ≡ µeff
W 2 (VGT −Voff )/nvth C (n − 1)vth e Leff ox
(7) (8)
where Isat is the current flat part of the IDS –VDS curve. However, in [13], the drain current noise behavior has been reported to deviate from (7) at RF frequencies. Contrary to the common assumption that drain current exhibits only the white channel thermal noise contributions, Chan et al. [13] demonstrate that the source–bulk and drain–bulk junctions generate thermal fluctuations that produce additional drain current noise, amplified by the source–bulk and drain–bulk junction capacitances. The junction noise produces another plateau in the noise spectrum of the drain current, given by [13] Sid,junction = 4kT gSB + 4kT gDB
Fig. 1. (Symbols) Measured and (lines) modeled drain current noise Sid values versus gate bias VGS characteristic of the 0.13-µm NMOS. The proposed model which is (13) is accurate throughout the WI, MI, and SI regions of NMOS.
(9)
where gSB and gDB are the ac conductances of the source–bulk and drain–bulk junctions. Each junction was modeled as a capacitor C in series with a resistor R and thus given by [13] gjunction =
ω2 C 2 R . 1 + ω 2 C 2 R2
(10)
It has been observed that the capacitor C and the resistor R are functions of the voltage drop across the junction V (11) C = C0 / V + Φi (12) R = R0 V + Φi . In [13], the values of C and R were extracted by performing simple Y -parameter characterization in the subthreshold region on a fixed drain bias of 1.2 V. The same extraction process is repeated on different drain biases. C0 and R0 can be extracted from the slope of 1/C 2 −VDS and R2 −VDS curves, while the built-in potential Φi can be determined from the intercept of axis VDS = 0. By including the channel thermal noise and the junction noise, the final unified drain current noise model is given by W µeff Cox VGTeff Sid = δ4kT Leff ω 2 C02 R0 1 1 √ +√ +4kT . (13) 1 + ω 2 C02 R02 Φi VDS + Φi
III. R ESULTS AND D ISCUSSION Fig. 1 shows the comparison of the simulated and extracted Sid values of the 0.13-µm NMOS. In the WI region, the noise generated by the ac conductances of the source–bulk and drain–bulk regions dominates the drain current noise, and the
Fig. 2. (Symbols) Measured and (lines) modeled first-order derivatives of the drain current noise Sid versus gate bias VGS characteristic of the 0.13-µm NMOS. The model shows excellent continuity characteristics.
contribution of channel noise becomes negligible. With additional noise from junctions taken into account, the proposed model which is (13) can fit the data accurately from the WI region to the SI region as well as the moderate-inversion (MI) region. In Fig. 2, the comparison of the first-order derivatives of Sid between the model (13) and experimental data is shown from the WI to SI region. The model exhibits a smooth transition at the boundary of the two regions. It emphasizes the model accuracy and continuity in the MI and WI regions. The advanced feature of the model makes it very attractive and promising in circuit simulation since the WI region is becoming more important for low-voltage and low-power circuit application. The comparison between the model (13) and extracted Sid values versus drain bias of the 0.13-µm NMOS is shown in Fig. 3. The drain bias dependence of Sid in the SI region is due to the factor δ and other short-channel effects discussed in [5]. In the MI region, the channel thermal noise decreases with VDS when the operation point is translating from the linear region to the saturation region. On the other hand, Sid increases with VDS in the saturation region due to the DIBL effect. In the WI region, with VGS = 0.1 V, for instance, the junction noise dominates the channel noise which can be√observed in Fig. 1, and thus, Sid is inversely proportional to VDS . In the case when VGS = 0.2 V, both the channel thermal noise and the junction noise are significant. Therefore, in such particular operating condition, the nonsaturation effect, short-channel effects like DIBL, and
CHAN et al.: DRAIN CURRENT NOISE MODELING WITH EFFECTIVE GATE OVERDRIVE AND JUNCTION NOISE
Fig. 3. (Symbols) Measured and (lines) modeled drain current noise Sid values versus drain bias VDS characteristic of the 0.13-µm NMOS biased in SI, MI, and WI regions.
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Fig. 5. (Symbols) Measured and (lines) simulated thermal noise excess factors γ = Sid /(4kT gm ) versus gate bias VGS characteristic of the NMOS with different gate lengths L = 0.13, 0.25, and 0.50 µm.
dously. The continuity and smoothness of the proposed model have been demonstrated with continuous partial derivatives. The model has unified expression for all regions and successfully verified with excellent match to 0.13-µm technology. R EFERENCES
Fig. 4. (Symbols) Measured and (lines) simulated spectral densities of the drain current noise Sid versus gate bias VGS characteristic of the NMOS with different gate lengths L = 0.13, 0.25, and 0.50 µm. This figure shows that the model is scalable across different gate lengths in the whole region.
the junction condition need to be accounted in order to predict the drain current noise accurately across the drain bias. Figs. 4 and 5 show the drain current noise Sid and the thermal noise excess factor γ = Sid /(4kT gm ), respectively, for NMOS with different channel lengths. The noise performance of the device improves when the operating point moves from the SI to WI region. However, γ becomes large when the device operates in the subthreshold region. In this region, the transconductance decreases exponentially as the gate bias decreases while the drain current noise saturates, as shown in Fig. 4, resulting in an exponential increment of gamma. The simulated result has excellent agreement with experimental data, indicating that the model is scalable across different gate lengths, and is valid from WI to MI to SI regions. IV. C ONCLUSION The introduction of an effective gate overdrive which includes the noise parameters allows channel thermal noise being modeled accurately across drain bias for WI, MI, and SI regimes. With incorporation of the junction noise, the accuracy of the subthreshold drain current noise model improves tremen-
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