Mostly Digital Wireless UltraWide Band Communication ... - IEEE Xplore

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Mostly Digital Wireless UltraWide Band Communication Architecture for Software Defined Radio Thomas Beluch, Florian Perget, Julien Henaut, Daniela Dragomirescu, and Robert Plana

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he objective of this competition was to design, construct and demonstrate a working wireless communication architecture for software defined radio (SDR). The implementation had to contain at least one programmable device, the front-end analog RF circuitry, an analog-to-digital converter (ADC), and an analog output. This SDR student design contest required multiple disciplines. There was a need for skills in RF analog design and wave propagation for the front-end and the antennas, digital signal processing (DSP) for the physical layer, and network setup and protocols for the medium access control (MAC). A coordinated design effort in the different disciplines was necessary to ensure that the different parts work together. The main criteria for judging were innovation and success of

reaching the goals that the student team had set. The target of this subject was based on a real aeronautic industry demand concerning real time, synchronized and high data-rate instrumentation wireless sensor network for in-flight aircraft test. This demonstrator was built for proving feasibility of the digital base-band capabilities in terms of achievable data-rate and reduction of the synchronization error between measurements on different network nodes. The desired goals of this system were to reach a 100 Mb/s data rate, and to obtain measurement trigger synchronization under 500 ns between the nodes.

Proposed Demonstrator The implementation of this demonstrator had to be performed on a board including a field programmable

Thomas Beluch ([email protected]), Florian Perget, Julien Henaut, Daniela Dragomirescu, and Robert Plana are with CNRS, LAAS, 7 Avenue du Colonel Roche, F-31077 and the Université de Toulouse, UPS, INSA, INP, ISAE; UT1, UTM, LAAS, F-31077 Toulouse, France. Digital Object Identifier 10.1109/MMM.2011.2174121 Date of publication: 13 January 2012

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1527-3342/12/$31.00©2012 IEEE

January/February 2012

gate array (FPGA) and fast ADC and digital-to-anaThis SDR student design contest log converter (DAC). The RedRapids 365 [1] boards required multiple disciplines. include a Virtex 5 SX50T FPGA along with the Texas Instruments ADS5474 14-b ADC and 16-b DAC5682 DAC. A specific version of this board, clocked at 500 MHz, is used for this demonstration. The RedRapids TX board is connected to the anaUWB-OFDM Analog TX PHY Layer log RF front-end composed RF Front-End of connectorized circuits. A separate external power supMAC LO Synchronization Layer ply is used to power the RF front-end modules. Analog RX RX The block diagram of RF Front-End UWB-OFDM the whole demonstrator is PHY Layer shown in Figure 1. In the following, we will present the RedRapids FPGA Board design of each part of our demonstration. This article Figure 1. Block diagram of the proposed demonstrator. is organized as a bottom-up explanation—from the RF front-end to the MAC layer—of the chalenges we not be filtered afterwards. This is why we chose a balfaced during the design of this system. anced mixer, which provides a high LO-to-RF isolation. Furthermore, the ultrawideband (UWB)-orthogonal frequency division multiplexing (OFDM) modulation Analog RF Front End used in the physical layer has a high power-average-toThe goals of the RF front-end design for this contest peak ratio (PAPR) because of the high number of subwere simplicity and size. We planned to use conneccarriers used [2]. Therefore, we chose a passive mixer torized RF components to build an RF front end. The for its high output linearity whose conversion gain is number of elements included in our front end had to 27 dB. With the baseband output power of 213 dBm, be as small as possible for transport. For this reason, this transmitter exhibits a power output of 28 dBm. we chose a direct conversion transmitter and receiver architecture, as they use a small number of components, while still providing good performance and the flexibility needed by the ongoing design of the other parts 20 dBm of the system. The adopted architecture is pictured in 5–10 GHz VCO Figures 2 and 3. The transmitter receives the signal from the DAC on the left and mixes it with a local oscillator (LO) signal generated by the voltage controlled oscillator (VCO) at 500 Msps 6–8 GHz 6-b DAC the top for the up-conversion. The power amplifier (PA) 8 dB Gain 10 dBm P1dB then boosts this signal before sending it in the air by the antenna. In this direct up conversion architecture, the LO signals falls into the RF signal band, and thus canFigure 2. Transmitter RF front-end architecture.

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The ultrawideband (UWB)-orthogonal frequency division multiplexing (OFDM) modulation used in the physical layer has a high power-average-to-peak ratio (PAPR) because of the high number of subcarriers used. At the receiver, the signal received by the antenna on the left is amplified by a low-noise amplifier (LNA) and then mixed with another LO for the down-conversion. This signal is then fed to a passive low-pass filter followed by two cascaded baseband amplifiers, which boost the signal until it reaches the full scale of the ADC. A digital low-pass filter is also implemented inside the FPGA in order to narrow the 250 MHz digitized signal to the actual 125 MHz bandwidth. The requirements for the antenna were a very large bandwidth (5 to 10 GHz), a moderate to high gain (between 5 dBi and 15 dBi) and a small size. This led us to choose a microstrip-fed Vivaldi slot antenna design [3] [4], as it can be made with both a high gain (in our case 9 dBi) and a large bandwidth. This receiver has a gain of 45 dB and a noise figure of 6.15 dB as calculated in the following equation: NFRx 5 NFA1 1 1

NFMix NFLPF NFA2 1 1 GA1 GA1 1 GMix GA1 1 GMix 1 GLPF

NFA3 . GA1 1 GMix 1 GLPF 1 GA2

This receiver front-end still lacks automatic gain control (AGC) and then requires manual tuning by spacing the antennas appropriately to guarantee full scale at the input of the ADC. However, for the purpose of the demonstration, this operation can be performed on site.

High Level Synthesis Physical Layer Design In the design presented in this contest, the constraints are imposed by the precise requirements edited by the final users in the aerospace industry. Classical wireless sensor network radio stacks (ZigBee for example) or Wireless personal area network physical layers (Bluetooth) are not suitable for such applications. Neither Zigbee nor Bluetooth achieve a 100 Mb/s data rate. The physical layer is a full custom in-house development. UWB-OFDM is the only solution that could meet the constraints required by the application (high data rate essentially). The other main requirement that lead to this choice was the necessity to avoid transmitting in industrial, scientific, and medical (ISM) bands allocated to critical aerospace systems. The proposed OFDM physical layer uses 128 carriers. Indeed, it is seen as the best compromise between

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performance and complexity in literature. This fact has been validated by the means of Simulink model simulations [5]. This UWB-OFDM modulation scheme has therefore been chosen for this project (Figure 4). In order to keep low complexity and easy decoding, each of the subcarrier is quadrature phase-shift keying (QPSK) modulated. Two synchronization symbols are added prior to any communication to perform the detection of the start of each frame. These symbols are also used to time stamp the data for the wireless deterministic clock synchronization (WiDeCS [8]) scheme. In order to achieve the best link quality, two levels of error correcting codes have been included. The first level, a four-register convolutional code has been chosen as the best compromise between the size of the generated module and the error correction performance. Such an encoder only adds 625 look up tables (LUTs) to the synthesized design for a tenfold decrease of the bit error rate (BER). The second level, a Reed Solomon block code, is used to improve the correction, and to check the data integrity before passing it to the MAC layer. To design such a complex UWB-OFDM physical layer, including multiple fast Fourier transform (FFT), a high-level synthesis (HLS)-based design flow has been chosen. Synplicity Inc (now part of Synopsys group) proposes a powerful platforms for HLS design with Synphony Model Compiler [6]. This tool is an add-on to MatLab Simulink [7]. The software offers a specific library, and provides the designer with an automated path from highlevel design and simulation to an architecturally optimized, synthesizable, system-level hardware description language (HDL) implementation. The blockset offers basic mathematic functions as well as more complex signal processing modules such as FFT or error correcting encoder/decoders. The generated output is synthesizable HDL code [real-time logic (RTL) level]. Many system-level optimizations such as retiming, folding and multichannelization are available and improve the generated code. This software also offers an automatic HDL test bench generator to match high level with RTL simulations. The Virtex 5 SX50T FPGA has been chosen as the best compromise for the target application. An implementation of the OFDM physical layer has been developed including many improvements on the signal processing (Figure 4).

Medium Access Control Design Although the physical layer modulates binary data into an analog signal for transmission through the wireless link, a MAC layer is needed when there is more than a single speaking node. The choice of a MAC protocol has been driven by the following requirements. First, it


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is necessary for the system to know the various delays involved in the transmission. This requirement is due to its use in the aerospace industry. Second, the number of nodes composing this network will not change over the time. A Carrier Sense based MAC protocol would induce too much unknown delays while waiting for a free slot before sending the data and is not feasible regarding the requirements. A time-division multiple access (TDMA) MAC protocol, with a fixed number of slots does reach both the two requirements cited above. Moreover, this protocol offers a good knowledge of every delay involved in the network except for the delays caused by underlying layers such as physical layer and RF and propagation. These delays will be treated in the following section concerning the synchronization service.

Synchronization Service For Wireless Sensor Networks The main applications require time accurate measurements. This means that measurements have to be taken at the same time with the lowest delay between all the measurements. It is thus necessary to produce a trigger signal on every node to trigger the measurement of the physical value. In order for these signals to be as accurate as possible, a synchronization service has been designed and implemented as a cross-layer service shared between the MAC and PHY layers. This service has been named WiDeCS for Wireless Deterministic Clock Synchronization [8]. WiDeCS protocol is based on the planning of transmissions, and the respect of this planning. It is designed for propagating the master clock of a star network to all the slaves. The synchronization protocol measures delays between expected receiving time and the actual one. The different delays in communication architecture

are detailed in Figure 5. WiDeCS uses time stamping at the time of the first effective bit at the output of the physical (PHY) layer in emission, and the first effective bit in input of the PHY layer in reception. These flags then enable precise measurement of the propagation time except for the jitter linked to RF front-ends. The synchronization process in itself is performed in two main steps: • Phase 1: Presynchronization: Every slave joining the network performs this step. The function of the master is to create and regularly send a preamble for the TDMA frames. The slaves, when reset, or desynchronized, switch to reception only mode, and wait for the master node to indicate the beginning of the frame. When this message is detected, the slave roughly corrects its own timer in order to transmit data in its own allocated slot. When this step is passed, the slave switches to phase 2 of the synchronization process. • Phase 2: Fine-synchronization: Once presynchronized, the nodes have a clock offset under 1us compared to the master clock. This offset is low enough to avoid transmitting in other time slots. However, it is still higher than 100 ns, which would be an acceptable error. This step consists in determining the offset with the greatest precision possible. When the slave is allowed to transmit data, it does it at one precise moment ti of the slot. This date is coded in the protocol and is known by every slave, and more importantly by the master. Data is sent to the PHY layer at this precise moment and a capture of the timer is done when the first bit of data really is sent. The delay between the planned transmission date and the real measured one is stored in: dti 5 ti transmitted 2 ti planned.

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Figure 5. Latencies involved in a wireless transmission.

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On the receiving side, the timer is captured at the time of reception of the first bit of data in the PHY layer. The delay between the expected receiving date and the actual one is stored in: Dti 5 ti received 2 ti planned. The same calculation is performed on master frames and are stored by each slave as Dtm and dtm. Considering that the propagation time is almost symmetrical. The clock offset Dtclk can be determined with this equation Dtclk 5

1 Dti 1 dtm 2 2 1 dti 1 Dtm 2 2

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The correction offset is applied to the timer, forcing rollback if necessary. WiDeCS can be used in every frame to regularly update the correction, and then reduce its sensitivity to node movement. Another possibility is to train the slave with an optimal number of frames, and then turn the reception module in sleep mode for as long as blindness is allowed in the network.

Future improvements of this project include the development of a full reconfigurable system on chip, including the presented work, a microprocessor core, and data acquisition interfaces. two Acquisys eInstruments-DAQ Node boxes. The RF front-end, composed of connectorized circuits, is plugged at the DAC output and ADC input of these cards. A LeCroy SDA 8Zi scope is used for the measurement trigger signals on a digital IO of the Red Rapids boards, the baseband signal at the analog output, as well as RF signal at the input of the antenna. Figure 7 shows the baseband UWB-OFDM spectrum composed of individual carriers gathered in sub-blocks. Unused carriers appear in the spectrum analysis as gaps between used carriers. The two demonstrated nodes are both transmitting data in their respective slot. This proves that the entire transceiver

The complete demonstration setup has been built and tested in a lab room. A patch antenna has been placed on a plane metallic surface to mockup the surface of a wing, and a horn antenna is placed at 4 m (LOS). Another antenna setup has been used for live demonstration at the 2011 IEEE MTT-S International Microwave Symposium (IMS2011). This one uses Vivaldi antennas with a 20 cm space between them. The Fig ure 6 shows the complete proposed demonstrator including two Red Rapids boards mounted in

© LAURENT BARY 2011

Results

Figure 6. Complete demonstration setup presented at IMS2011.

Figure 7. Spectrum analysis of the generated signal.


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Figure 8. Scope capture of the demonstration setup.

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is working enough for the slave to reach the mastercreated TDMA frame. The two measurement triggers are rising simultaneously, or at least with the smallest possible offset. It is also interesting to build a histogram of the measured offset between these triggers to determine the performance of this system. These two checks have been gathered in a single scope display for the purpose of the demonstration. The pink and yellow channels display the signal transmitted by both the master node (yellow) and the slave node (pink). The histogram logs the offset values recorded over 1h time. This offset is below 60 ns for 95% of the measurements.

urable system on chip, including the presented work, a microprocessor core, and data acquisition interfaces. A specific RF front-end is also in the process of being developed.

Conclusion

References

This project involves multiples disciplines in order to reach a system-level objective. We had to develop a complete SDR demonstrator that solves a real industry problem: Build a high data-rate synchronized Wireless Sensor Network for real-time instrumentation measurement. The proposed demonstrator is built using a FPGA development board for the digital UWB-OFDM modulation and demodulation, as well as the MAC layer and synchronization service. The RF front-end is built by assembling connectorized development boards containing each RF element separately. The whole demonstration has been tested in a Lab room. The achieved trigger offset is 60 ns for 95% of the measurements. The frequency band used by this whole system is 125 MHz centered at 6.8 GHz. Considering that the result of this project is an academic demonstrator, it still lacks components that would improve its performances. Future improvements of this project include the development of a full reconfig-

[1] Red Rapids. Channel Express 365 datasheet. [Online]. Available: http://www.redrapids.com/Products/Datasheets/Model365.pdf 2009 [2] H. Ochiai and H. Imai, “On the distribution of the peak-to-average power ratio in OFDM signals,” IEEE Trans. Commun., vol. 49, no. 2, pp. 282–289, 2001. [3] P. J Gibson, “The Vivaldi aerial,” in Proc. 9th European Microwave Conf., 1979, pp. 101–105. [4] J. Shin and D. H. Schaubert, “A parameter study of stripline-fed Vivaldi notch-antenna arrays,” IEEE Trans. Antennas Propagat., vol. 47, no. 5, pp. 879–886, May 1999. [5] J. Henaut, D. Dragomirescu, and R. Plana, “FPGA based high date rate radio interfaces for aerospace wireless sensor systems,” in Proc. 4th Int. Conf. Systems (ICONS ‘09), 2009, pp. 173–178. [6] Synopsys. Synphony HLS tools web page. [Online]. Available: http://www.synopsys.com/SYSTEMS/BLOCKDESIGN/HLS/ 2011 [7] MathWorks. SimuLink web page. [Online]. Available: http:// www.mathworks.com/products/simulink/ 2011 [8] T. Beluch, D. Dragomirescu, F. Perget, and R. Plana, “Cross-layered synchronization protocol for wireless sensor networks,” 2010, pp. 167–172.

Acknowledgments We would like to thank our advisor, Dr. Daniela Dragomirescu, for mentoring this project. We would also thank the French Defense Agency (DGA) for funding the doctoral studies of Thomas Beluch and Florian Perget, Synopsys for providing the software used for this project and for the technical support, and RedRapids for their technical support of the FPGA boards.
