Multichannel ultrathin silicon-on-sapphire optical ... - IEEE Xplore

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IEEE JOURNAL OF SELECTED TOPICS IN QUANTUM ELECTRONICS, VOL. 9, NO. 2, MARCH/APRIL 2003

Multichannel Ultrathin Silicon-on-Sapphire Optical Interconnects J. Jiang Liu, Senior Member, IEEE, Zaven Kalayjian, Brian Riely, Wayne Chang, Member, IEEE, George J. Simonis, Senior Member, IEEE, Alyssa Apsel, Member, IEEE, and Andreas Andreou, Associate Member, IEEE

Abstract—Multichannel optical interconnects were developed using vertical-cavity surface-emitting laser (VCSEL) arrays and metal-semiconductor-metal photodetector (PD) arrays and driven by complementary metal-oxide-semiconductor circuits that were fabricated using ultrathin silicon-on-sapphire (SOS) technology. Low-threshold oxide-confined top-emitting VCSEL 8 8 arrays were designed and fabricated with off-site contact bonding pads. The arrays were flip-chip bonded to driver arrays on sapphire substrates and mounted on high-speed printed-circuit boards as optical transmitter arrays. The laser output was transmitted through the transparent sapphire substrate and coupled to MSM PD arrays and the SOS receiver. This optical interconnect system was demonstrated to operate at a data rate of 1.0 Gb/s per channel with a power consumption of 28 mW for each channel including transmitter and receiver. Index Terms—Optical interconnect, oxide aperture, photodetector (PD), sapphire substrate, silicon-on-sapphire (SOS), vertical-cavity surface-emitting laser (VCSEL).

I. INTRODUCTION

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N THE development of next generation board-to-board and chip-to-chip level optoelectronic (OE) interconnects, highdensity two-dimensional (2-D) optical links that are composed of VCSEL and photodetector (PD) arrays integrated with highspeed drivers and receivers offer promising solutions to achieve high-bandwidth, low-power-consumption, and parallel digital data communication and switching [1]–[3]. These new optical interconnects can also significantly enhance and change the fundamental architectures for future datalinking systems [4]. To improve the operating speed and power consumption of transmitters, VCSELs are usually made with low-resistance electrical contacts and oxide-confined apertures for lower lasing current thresholds [5]–[8]. Recently, the new evolving technology of ultrathin silicon-on-sapphire (SOS) CMOS was applied to fabricate high-bandwidth driving circuits [9]. CMOS circuits fabricated on ultrathin silicon films deposited on sapphire substrate are becoming an attractive technology for ultrafast drivers and receivers. Because of the insulating properties of the sapphire substrate, this CMOS process reduces parasitic capacitance and enables very fast circuitry (projected up to 40 GHz for 0.13- m processing) [10]. bandwidth limit Manuscript received November 8, 2002; revised February 17, 2003. J. J. Liu, Z. Kalayjian, B. Riely, W. Chang, and G. J. Simonis are with the U.S. Army Research Laboratory, Adelphi, MD 20783 USA (e-mail: [email protected]). A. Apsel and A. Andreou are with the Department of Electrical and Computer Engineering, The Johns Hopkins University, Baltimore, MD 21218 USA. Digital Object Identifier 10.1109/JSTQE.2003.814182

Since these drivers and receivers are fabricated on a transparent substrate, 850-nm top-emitting VCSELs and top-receiving PDs can be flip-chip bonded onto them and transmit/receive through the plane of circuitry, without extra device processing steps for substrate removal. The thermally conductive sapphire substrate also provides a better heat sink for the electrical driving circuitries than the SiO used in other silicon-on-insulator (SOI) technologies. Another obvious advantage of the optical interconnects composed of transparent transmitters and receivers is that they can easily evolve to bidirectional and three-dimensional cascade links [11]. The simplicity in device processing and hybridization of these interconnects will significantly lower the manufacturing cost. In this paper, we report our fabrication of 8 8 top-emitting 850-nm VCSEL arrays and 1 12 metal-semiconductor-metal (MSM) PD arrays, their hybridization with SOS drivers and receivers, and integration to produce complete optical interconnects. Electrical and optical properties of the devices as well as the interconnect system were investigated. These optical interconnects were demonstrated to operate up to a bandwidth of 1.0 Gb/s per channel at a bias voltage of 3.3 V. The electrical power consumption was measured only 28 mW per channel. II. SOS TRANSMITTER Our optical transmitters are composed of oxide-aperture-confined 850-nm top-emitting VCSEL arrays and SOS drivers. The VCSEL structure was grown inhouse at the U.S. Army Research Laboratory on n-type GaAs substrates by molecular beam epitaxy (MBE). Driver circuits were customer designed and fabricated on sapphire substrates through the MOSIS Foundry Service using 0.5- m SOS-processing technology. A. 850-nm Top-Emitting VCSEL Array Our VCSEL structure was grown on an n-type GaAs substrate by MBE. The VCSEL epitaxial structure consists of a 35-pair n-doped Al Ga As/Al Ga As bottom cavity, and a 25-pair distributed Bragg reflector (DBR), a p-doped Al Ga As/Al Ga As top DBR. The active GaAs quantum wells with 70 region consists of three 70 Al Ga As barriers. The heavy-hole exciton resonant energy of the quantum well was designed with a gain offset of 15 meV above the cavity resonant energy to account for the band-gap narrowing at high carrier concentrations. This ensures a good match between the gain spectrum and the cavity characteristics during actual device operation. Test structures for this design were repeatedly grown and characterized by

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LIU et al.: MULTICHANNEL ULTRATHIN SOS OPTICAL INTERCONNECTS

photoreflectance and photoluminescence spectroscopies until the precise growth condition and epitaxial structure were achieved. The first two pairs of the DBRs (both the p-DBR and the n-DBR) close to the active region are lightly doped (5 10 cm ) to reduce the free carrier absorption. Two 300 -thick Al Ga As layers for oxidation were embedded in the first period of the p- and n-DBRs and aligned with the node of the standing wave to reduce the scattering loss. The rest of the DBRs were modulation doped with (for p-type, beryllium) maximum doping of 1 10 cm (for n-type, silicon) at the nodes and and 4 10 cm minimum doping of 1 10 cm for both n- and p-type at the antinodes. Quadratically graded layers with a thickness were inserted at the hetrojunctions of the DBRs of 250 to reduce the series resistance. The grading layers consist of Al Ga As/Al Ga As and Al Ga As/AlAs short period superlattices. A 400 Al Ga As layer followed by a 100 GaAs layer, both p-doped to 1 10 cm , were deposited on the top of DBRs to achieve good ohmic contact. The device processing starts with an N-contact metal depoCl reactive sition on the top DBR contact layer. A BCl ion etching (RIE) process produced 32- m-diameter, 4- m-tall, and 125- m-pitch 8 8 VCSEL mesa arrays with the AlAs oxidation layers exposed. Wet oxidation process was carried out to form the oxide confinement aperture. The resultant mesas were passivated by low-temperature plasma-enhanced chemical vapor deposition (PECVD) of 5000 SiO layer. Spin coated cyclotene (BCB) resin was applied on the mesa structure for planarization. As a special design for future flip-chip bonding of the device, we used an interconnecting metal deposition process to form offset electrical contacts to the p-contacts of the mesas. Patterned Indium bumps of 40 m in diameter were deposited by e-beam evaporation on top of the offset electrical contacts for flip-chip bonding. Fig. 1 shows a processed top-emitting VCSEL 8 8 array with a detailed callout of several devices. A cross sectional view of the structure of an individual VCSEL is illustrated in Fig. 2. The N-contact for the VCSEL was placed on the backside of the GaAs substrate by depositing Ge/Ni/Au metal film. After these fabrication procedures, the 8 8 VCSEL arrays were diced out and prepared for hybridization with driver chips. Average lasing threshold around 250 A were found on these devices both before and after they were wire bonded in a pingrid-array (PGA) package. Fig. 3 shows the characteristics of current-voltage-light output power (I-V-L) of one of those 850 nm VCSELs. The center emission wavelength of the VCSEL at the room temperature, as shown was measured at 8352 in the insert of Fig. 3. The diameter of the oxide confinement aperture was measured to be 5.6 m from a high-resolution near-field intensity pattern. The maximum power output obtained from this device was 175 W at the injection current of 2.2 mA. The maximum differential quantum slope efficiency was calculated to be about 12%. B. SOS VCSEL Drivers To host VCSEL arrays, the CMOS driver circuits fabricated on the transparent sapphire substrate also contained matching

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Fig. 1. Complete 8 8 top-emitting 850-nm VCSEL array. The callout detail shows their offsite bond pads with deposited Indium bumps.

Fig. 2. Schematic crosssectional illustration of a top-emitting 850-nm VCSEL device.

8 8 array contact pads and 125- m pitches. The addressable 8 8 array of VCSEL driver circuits was fabricated through the MOSIS foundry service in a 0.5- m SOI technology. This particular SOI process, manufactured by Peregrine Semiconductor Corporation, San Diego, CA, uses sapphire as an electrically insulating substrate, and hence, is known as SOS CMOS. This SOS process features oxide-isolated transistors integrated on a 100-nm ultrathin layer of epitaxially grown silicon. Negligible device parasitic capacitances and crosstalks resulted from this of these driver circuits was process. The bandwidth limit

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Fig. 5. Schematic illustration of the SOS optical transmitter in which a top-emitting VCSEL array is flip-chip bonded on the sapphire driver substrate. Fig. 3. Characteristics of current-voltage-light power (I–V–L) of an 850-nm VCSEL.

Fig. 4.

Micrograph and a single cell architecture of the SOS driver chip.

measured to be above 3 Gb/s under current condition and will be extended to 40 Gb/s as the processing moves to 0.13- m schemes [10]. The driver chip micrograph and cell architecture is shown in Fig. 4. Each cell in the 8 8 array contains a bump-bond pad for hybridization and a VCSEL driver circuit. The driver circuit has two parallel current paths for controlling VCSEL current, controls the dc bias current and controls the current flow when a VCSEL in the array is selected. Global biases of OnBias and OffBias set the dc and “on” currents for all cells in the array. A NAND gate in each cell receives inputs from the 16 peripheral and , . When both the select lines and inputs to a driver cell are high, the switch transistor is turned on and current flows through . Otherwise, . High-speed on-chip the unselected VCSEL is biased by and select lines. Simulations from the buffers drive the input pad showed an operation bandwidth up to 3 Gb/s using this addressing scheme. C. Hybridization of VCSEL With SOS Driver To improve the bonding contact with those indium bumps on the VCSEL chip, contact pads on the driver circuits were further coated with a thin layer of gold film using an electroless plating process. The flip-chip bonding process was performed on a Research Devices Inc. M-8 flip-chip bonder. A special

Fig. 6. Example of flip-chip bonded VCSEL array with the transparent SOS driver viewed from (a) the top VCSEL side and (b) through the sapphire substrate.

device holder was fabricated for the 1-mm size VCSEL chips. An average bonding force of ten g/bump was carefully applied on the VCSEL chip and the sapphire driver substrate. This flip-chip bonding procedure was investigated in separate experiments using a daisy-chain structure for the purpose of prescreening the bonding yield. The results proved that a nearly 100% yield for a 128 continuous electrical contact can be achieved under our device hybridization scheme. The average contact resistance was found to be below 0.1 ohms/bump. Fig. 5 schematically illustrates the crosssection of a flip-chip bonded top-emitting VCSEL array on the sapphire driver substrate. VCSEL mesas with top p-contact rings are positioned between the spaces of offset bonding pads, which allow optical outputs of the VCSEL’s transmit through the transparent sapphire substrate. Two photographs of an actual flip-chip bonded VCSEL array with the sapphire driver substrate, viewing from the VCSEL chip side and through the substrate, are shown in Fig. 6. The hybridized device was then directly packaged onto a high-speed printed circuit board (PCB) and electrically con-


Fig. 7. Completely packaged SOS transmitter set up for the free-space optical interconnects operation.

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Fig. 9. Operational characteristics of a typical MSM PD. The insert is a micrograph of a part of the PD device.

analysis has been reported in a previous paper [12]. The input stage of the transimpedance amplifier (TIA) of the receiver is designed with 4.5 k on chip feedback resistors and a bandwidth of 600 MHz when used with a 0.5-pf PD. The amplification stages have a gain of 1.3 and a bandwidth of nearly 1GHz. Functions of the receiver array were confirmed by both electrical and optical tests in which the receiver array was wire bonded with a commercial linear array of MSM PDs and optically driven by VCSEL sources. B. 850-nm MSM PD

Fig. 8.

Micrograph of the SOS receiver chip.

nected by wire bonds. An optical window was created on the PCB for the output of the VCSEL array beams. Fig. 7 shows a completely packaged SOS transmitter set up for free-space optical interconnects operation. III. SOS OPTICAL RECEIVER AND MSM PHOTODETECTOR ARRAY A. 850-nm SOS Receiver The receiving part of the optical interconnect is composed of a 1 6 multistage differential SOS CMOS array receiver chip with an MSM linear PD array flip-chip bonded on top of it. The receiver chip was fabricated using a 0.5- m ultrathin SOS CMOS process through MOSIS foundry. The SOS process enables the design of high-speed circuits with very low power consumption and no substrate crosstalk. Fig. 8 shows a microscope photograph of the SOS receiver chip. A detailed description and

We designed interdigitated finger MSM schottky-barrier PD arrays to integrate with the SOS photoreceiver chip. The PD array was fabricated on a semiinsulating GaAs (dopant level cm ) substrate. The 100 100 m active area of of 4 10 each PD contains 25 interdigitated fingers. Each finger has a width of 0.2 m and is separated by a 2.0- m interfinger space. E-beam evaporated Au/Pt films were used to form the active area and p-n contact electrodes. The PD array has the receivermatching 1 12 pattern and common n-contact electrodes. A photograph showing a part of such PD array is displayed as an insert in Fig. 9. Prehybridization characterization was carried out on these PD arrays using a commercial laser source. The output currents from the PDs were measured directly without amplification. Fig. 9 shows the responsivity characteristics of a typical MSM PD under 5-mW laser illumination. An external responsivity of 0.32 A/W was measured with a bias starting even below 2.0 V. The dark current of these PDs was found only in the range of a few pA. This result was quite satisfactory since the receiver circuitry can provide around 3.0 V during the operation. For the purpose of flip-chip bonding integration, both electrical contact pads of the PDs were deposited with 6- m-high Indium bumps. An extra row of Indium bumps were also deposited in parallel to the PDs to insure the precise leveling of the PD chip to the receiver chip during the flip-chip bonding process. Under the similar procedure of hybridizing the VCSEL transmitter, we bonded the MSM PD array to the SOS receiver

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Fig. 12. Eye diagram from a single channel of the SOS optical interconnects operating at 1 Gb/s. Fig. 10. Micrograph of the hybridized photoreceiver viewing through the sapphire substrate.

Fig. 11. Schematic illustration of the SOS substrate-to-substrate coupling optical interconnects.

array using the M-8 flip-chip bonder. A micrograph of the hybridized photoreceiver viewing through the sapphire substrate is shown in Fig. 10. IV. OPERATION OF SOS INTERCONNECTS We integrated and operated our multichannel SOS optical interconnects under free-space configuration. The PC board-mounted SOS VCSEL transmitter and photoreceiver arrays were optically aligned from substrate-to-substrate using a compound-coupling lens, as illustrated in Fig. 11. Initial testing of this OE link was performed using a Hewlett-Packard 3.0-GHz pulse generator and a 20-GHz digital oscilloscope. The optical output of the VCSEL transmitter was modulated by the pulse generator and transmitted through the transparent sapphire substrate. Such output will be coupled through the sapphire substrate of the photoreceiver to the MSM PDs. Both the modulation signal and the electrical output from the photoreceiver were displayed and analyzed on the 20-GHz digital oscilloscope. At the time of preparing this paper, we encountered some packaging problems of the back-illuminated

SOS photoreceiver. We used a wire-bonded PD array on the same SOS receiver and measured output of the transmitter from front illumination. Fig. 12 shows an eye diagram measured at an operating data rate of 1 Gb/s from a single channel of this SOS optical receiver. Bit-error-rate (BER) under this pseudorandom-bit-sequence (PRBS) operating mode was measured to be better than 10 . Due to the nature that the VCSEL output transmits through the sapphire substrate to reach the photoreceiver, the surface reflection from the sapphire may have contributed to a part of the noise we observed in the eye diagram. Quantitative data regarding this effect is yet to be investigated. We have found that the optical crosstalk in such interconnects system was not a concern [5]. Our previous measurement indicated that the crosstalk was under 27 dB for a misalignment of 70 m. Further utilization of the microlens array to replace the compound lens for optical imaging and alignment would definitely improve the performance of the system. Wire bonds and some other packaging factors on the PC boards can also be modified to reduce the BER during operation. From the test results of these individual devices, we believe that the performance of the SOS optical interconnects reached early design specifications of the driver and receiver chips. During the above operation, both SOS driver and receiver were using a bias of 3.3 V. Electrical currents drawn by each driver and receiver channel were measured to be 6.5 and 2.0 mA, respectively [13]. This yielded a total power consumption of only 28 mW for a single interconnect channel. The results presented display significant advantages of the low-threshold optical interconnects over the electrical interconnect systems. V. SUMMARY We designed and built a complete 2-D optical interconnects using the advanced SOS driver and receiver technology. Lowthreshold VCSEL arrays and high-performance MSM PD arrays were also fabricated and hybridized with drivers and receivers under the flip-chip bonding scheme. Our results demonstrated a very encouraging optical interconnects system that can


deliver fast and parallel data rate with very low power consumption. Our second generation of 8 8 SOS drivers and receivers has recently been fabricated. Hybridization and characterization of the new optical transmitters and photoreceivers are currently under way. Multigigabits bandwidth operations through single and aggregated channels are expected from such parallel optical interconnects.

ACKNOWLEDGMENT The authors would like to acknowledge ARL colleagues, Dr. P. Shen, Dr. N. Das, Dr. G. Dang, and Dr. K. Aliberti, for designing, processing, and testing VCSELs and MSM PDs and K. Olver and T. Taylor for technical supports in device packaging.

REFERENCES [1] N. Savage, “Linking with light,” IEEE Spectrum, vol. 39, pp. 32–36, Aug. 2002. [2] D. V. Plant and A. G. Kirk, “Optical interconnects at the chip and board level: Challenges and solutions,” Proc. IEEE, vol. 88, pp. 806–817, June 2000. [3] H. Tsuda, T. Nakahara, and T. Kurokawa, “Hybrid-Integrated smart pixels for dense optical interconnects,” IEICE Trans. Electron., vol. E84C, no. 12, pp. 1771–1777, 2001. [4] K. Iga, “Vertical-cavity surface-emitting laser—Progress and prospects,” IEICE Trans. Electron., vol. E85C, no. 1, pp. 10–20, 2002. [5] J. Pham, G. J. Simonis, J. Pamulapati, B. Lawler, P. Shen, J. Liu, W. Chang, P. Newman, M. Taysing-Lara, B. Koley, and M. Dagenais, “8 8 arrays of VCSEL/CMOS and photodetectors optoelectronic interconnects,” Proc. SPIE, vol. 3714, pp. 24–30, 1999. [6] G. J. Simonis, J. Liu, B. Koley, M. Dagenais, J. Mait, P. Newman, W. Lawler, W. Chang, P. Shen, M. Taysing-Lara, and M. Datta, “Research on VCSEL interconnects and OE processing at army research laboratory,” Proc. SPIE, vol. 3946, pp. 172–186, 2000. [7] J. J. Liu, Z. Kalayjian, B. Riely, B. Gollsneider, W. Lawler, W. Chang, P. H. Shen, M. Taysing-Lara, P. G. Newman, and G. J. Simonis, “HighBandwidth multi-channel optoelectronic interconnects for parallel data and image transmission and processing,” Proc. SPIE, vol. 4292, pp. 52–61, 2001. [8] F. Mederer, I. Ecker, J. Joos, M. Kicherer, H. J. Unold, K. J. Ebeling, M. Grabherr, R. Jager, R. King, and D. Wiedenmann, “High performance selectively oxidized VCSELs and arrays for parallel high-speed optical interconnects,” IEEE Trans. Adv. Packag., vol. 24, pp. 442–449, Nov. 2001. [9] C. B. Kuznia, D. J. Albares, M. Wong, M. Pendleton, J. Green, J. Cable, R. Athale, and R. E. Reedy, “Flip chip bonded optoelectronic devices on ultra-thin silicon-on-sapphire,” in Proc. Tech. Dig. Opt. Fiber Conf., Mar. 2001, pp. TuR4.1–3. [10] C. B. Kuznia, M. Wong, M. Pendleton, P. Bachta, T. Le, M. P. Divakar, S. Thai, M. Englekirk, D. Pommer, R. Hagen, J. Cable, R. Athale, R. E. Reedy, and D. J. Albares, “Flip chip bonded optoelectronic devices on ultra-thin silicon-on-sapphire for short reach networking applications,” in Tech. Dig., Opt. Soc. Amer., Oct. 2001. [11] A. G. Andreou, Z. K. Kalayjian, A. Apsel, P. O. Pouliquen, R. A. Athale, G. Simonis, and R. Reedy, “Silicon on sapphire CMOS for optoelectronic microsystems,” IEEE Circuits Syst. Mag., vol. 1, no. 3, pp. 22–30, 2001. [12] A. Apsel and A. G. Andreou, “A 5mW Gigabit/s silicon on sapphire CMOS optical receiver,” Electron. Lett., vol. 37, no. 19, pp. 1186–1188, 2001. [13] A. Apsel, A. Andreou, and J. J. Liu, “A 6 channel array of 5 mW, 500 MHz optical receivers in 0.5 m SOS CMOS,” in Proc. Int. Symp. Circuits Syst., vol. 5, May 2002, pp. 433–436.

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J. Jiang Liu (M’85–SM’02) received the B.S. and M.S. degrees in optics and laser physics from Peking University, Beijing, China, in 1982 and 1984, respectively, and the Ph.D. degree in solid state physics from The Pennsylvania State University, University Park, in 1991. He was a Research Associate and Senior Researcher in the Department of Materials Sciences and Engineering, North Carolina State University, Raleigh, and the North Carolina Microelectronics Center, from 1991 to 1994, working on the development of advanced vacuum microelectronics high power RF amplifiers and flat-panel displays. He joined the U.S. Army Research Laboratory, Ft. Monmouth, NJ, as a National Research Council Associate, in 1995. Currently, he is a Research Electronics Engineer in the Sensors and Electron Devices Directorate, Adelphi Laboratory Center, U.S. Army Research, Adelphi, MD. He is a Project Leader and Principle Investigator in the development of high-bandwidth multichannel parallel optoelectronic interconnects, new photonic devices, and optical sensor systems. He has authored and coauthored over 60 technical papers and book chapters in U.S. and internationally circulated scientific journals. He holds two U.S. patents in the microelectronics area. His research interests include 2-D CMOS-hybridized vertical-cavity surface-emitting laser transmitter and photoreceiver arrays, OE interconnects, high-efficiency luminescent materials and devices. His expertise extends to device microfabrication, characterization, and integration, automated data acquisition, processing, reconstruction, and transmission using OE interconnect systems. Dr. Liu is a Reviewer for the Journal of Applied Physics, Applied Physics Letters, and the Journal of Vacuum Sciences and Technology.

Zaven Kalayjian, photograph and biography not available at time of publication.

Brain Riely, photograph and biography not available at time of publication.

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Wayne Chang (M’80) received the B.S. degree in chemical engineering from the National Taiwan University, Taipei, Taiwan, R.O.C. in 1965 and the M.S. degree from the University of Maryland, College Park, in 1976. In 1976, he joined Comsat Laboratories, Clarksburg, MD, to work on the GaAs devices as well as microwave integrated circuits, monolithic microwave integrated circuits, and optical integrated circuits. He joined the Adelphi Laboratory Center, U.S. Army Research, Adelphi, MD, in 1989, where he has been working on optoelectronic devices and device fabrication technology. He is currently the Team Leader of VCSEL and Optical Interconnect, with responsibility for research and development on the related projects.

George J. Simonis (M’78–SM’01) received the B.S. degree in physics and math from Wisconsin State University, Platteville, in 1968 and the Ph.D. degree in physics and solid-state raman spectroscopy, from Kansas State University, Manhattan, in 1973. He was commissioned in the U.S. Army, Ordnance Branch, in active duty at Harry Diamond Laboratories as a research Physicist for two years on infrared gas lasers and IR nonlinear processes. He has held civil service positions at Harry Diamond Laboratories, LABCOM, and ARL, Adelphia, MD, as a Research Physicist since 1974, working on infrared gas lasers, IR nonlinear processes, solid state and semiconductor lasers, semiconductor-laser gas spectroscopy, far infrared and millimeter-wave properties of materials, RF photonics, semiconductor-waveguide integrated optics, semiconductor reflection modulators, vertical-cavity surface-emitting lasers (VCSEL), VCSEL optoelectronic interconnects, and VCSEL optoelectronic processing. He was the Chief of the Microphotonics Branch from 1997 to 2000, the Acting Chief of the ElectroOptics and Photonics Division, Sensors and Electron Devices Directorate, ARL from 2000 to 2003, and is now the Chief of the Microphotonics Branch.

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Alyssa Apsel (M’86) received the B.S. degree with distinction from Swarthmore College, Swarthmore, PA, in 1995, the M.S. degree from California Institute of Technology, Pasadena, in 1996, and the Ph.D. degree from The Johns Hopkins University, Baltimore, MD, in 2002. She is currently the Clare Luce Boothe Assistant Professor of Electrical and Computer Engineering, Cornell University, Ithaca, NY. Her dissertation research focused on the design, implementation, and analysis of optoelectronic systems in silicon on sapphire very large scale integration (VLSI). Her current research interests include analog, high-speed, and optoelectric VLSI. Prof. Aspel received a Caltech Institute Fellowship in 1995, an Aspel Wolman Fellowship in 1997, and a Clare Luce Boothe Professorship in 2002. She is also the recipient of the Best Student Paper Award for the 2000 Midwest Symposium on Circuits and Systems.

Andreas Andreou (S’00–A’00), photograph and biography not available at time of publication.